# SiliconCompiler

> A modular hardware build system -- "make for silicon". It compiles RTL to GDSII
> (ASIC) or a bitstream (FPGA) by driving pluggable flows over open-source and
> commercial EDA tools. Everything is configuration in a single versioned schema,
> and the Python API is a typed surface over that schema.

This file follows the [llms.txt](https://llmstxt.org) convention. It exists
because most of the material written about SiliconCompiler describes an API that
was removed in 2025, so an assistant answering from memory will usually be
wrong. The sections below state what is current; the index that follows links
every page on the documentation site.

## The current API

Import from `siliconcompiler`. A **`Design`** describes source code and is
reusable; a **project** describes one compilation of it.

Use one of the named project classes -- **`ASIC`, `FPGA`, `Lint` or `Sim`** --
rather than the bare `Project`. Choosing the class is how you say what kind of
build this is, and each named class carries the schema, constraints and metrics
for its domain. `Project` is only the base class they extend; a build script
written against it has no domain schema and will not fit the target or flow you
want.

```python
from siliconcompiler import ASIC, Design
from siliconcompiler.targets import skywater130_demo

design = Design("heartbeat")
design.set_dataroot("heartbeat", __file__)          # the root for files below
design.set_topmodule("heartbeat", fileset="rtl")
design.add_file("heartbeat.v", dataroot="heartbeat", fileset="rtl")
design.add_file("heartbeat.sdc", dataroot="heartbeat", fileset="sdc")

project = ASIC(design)
project.add_fileset(["rtl", "sdc"])                 # which filesets to compile
skywater130_demo(project)                           # PDK, libraries and flow
project.run()
project.summary()
```

Four conventions this example encodes:

- **Files live in named filesets** (`rtl`, `sdc`, `xdc`, `testbench`) rather than
  one flat list. `Design.add_file` assigns one; `Project.add_fileset` selects
  which the run uses.
- **Paths are rooted at a dataroot**, not the working directory. Passing
  `__file__` roots them at the directory holding the script -- a file path is
  accepted and its parent directory used -- so the build works from anywhere. An
  environment variable dataroot (`set_dataroot("foundry", "$FOUNDRY_ROOT/...")`)
  is how foundry data is referenced without committing it.
- **Prefer typed accessors to raw keypaths.** `project.option.set_remote(True)`
  and `project.set('option', 'remote', True)` reach the same value; the accessor
  is the supported interface. Use a keypath when no accessor exists, which mostly
  means reading metrics and records: `project.get('metric', 'cellarea',
  step='synthesis', index='0')`.
- **A target is a function you call** with the project. Flows, tool tasks,
  libraries and PDKs are classes you subclass.

Top-level exports, in full: `Design`, `Project`, `ASIC`, `FPGA`, `Lint`, `Sim`,
`PDK`, `StdCellLibrary`, `FPGADevice`, `Flowgraph`, `Checklist`, `Task`,
`TaskSkip`, `OpenTask`, `ShowTask`, `ScreenshotTask`, `NodeStatus`, `sc_open`,
`__version__`.

## What no longer exists

This section is the reason the file is worth fetching.

- **There is no `Chip` class.** `Chip('design')`, `chip.set(...)`,
  `chip.input(...)`, `chip.use(...)`, `chip.register_source(...)` and
  `chip.load_target(...)` were removed in **v0.35.0** (October 2025). They are
  what most training data contains. The replacement is `Design` + a project
  class; every old name is mapped in the migration guide linked below.
- **There is no `sc` command.** The console scripts are `sc-config`,
  `sc-issue`, `sc-remote`, `sc-show`, `sc-install` and `smake` -- that is the
  complete list. A `sc -target asic_demo` invocation is from the pre-0.35 CLI
  and fails with `command not found`. To run something from a shell, use a Python
  script, `smake`, or `python3 -m siliconcompiler.demos.asic_demo`. The web
  dashboard is `python3 -m siliconcompiler.apps.utils.dashboard`, and the
  remote job server is `python3 -m siliconcompiler.remote.server`.
- **`FPGA` changed meaning.** It used to be the FPGA device class; it is now the
  FPGA *project* class. The device is `FPGADevice`.
- **Manifests are `.pkg.json`**, not `.cfg`. The `.cfg` extension predates
  v0.20 and any script or command using it is stale.
- **`package=` is now `dataroot=`** on every path parameter (schema 0.52.0).
- **The `option,mode` parameter is gone** -- pick the project class instead.

## Where new code goes

A frequent request is "add a PDK to SiliconCompiler", and the answer is usually
that it does not go in this repository:

- **Open-source PDKs and standard cell libraries** go in the separate
  [`lambdapdk`](https://github.com/siliconcompiler/lambdapdk) package.
- **Closed or proprietary PDKs and IP** go in your own pip-installable package,
  with foundry data referenced through environment-variable dataroots and never
  committed.
- **Tool drivers, flows and targets** go in-tree, under `siliconcompiler/`.

`siliconcompiler/pdks/` and `siliconcompiler/libs/` do not exist and should not
be created. In-tree module directories are `tools/`, `flows/`, `targets/` and
`checklists/`.

## Two version numbers

The package version and the schema version are independent. The schema version
(`schemaversion`) is recorded in every manifest and has its own changelog, which
is the authoritative record of what was added, renamed or removed at each
version -- see "Schema Changes" in the index below.

## Machine-readable schema

`schema.json` at the root of this site is a generated dump of the schema for each
project class: every parameter with its keypath, type, default, scope and help
text. Prefer it over scraping the HTML reference.

## Repository

Source, issues and discussions:
<https://github.com/siliconcompiler/siliconcompiler>. The repository root carries
an `AGENTS.md` with the same orientation aimed at editing the code rather than
using it. Working, tested designs are under `examples/`.

The remainder of this file is the full text of every hand-written page on the documentation site. The generated reference -- the schema, the Python API, the CLI apps and the module catalogues -- is not included; see https://docs.siliconcompiler.com/en/latest/schema.json for the machine-readable schema and the links above for the rest.


---

Source: https://docs.siliconcompiler.com/en/latest/index.html

## Welcome to SiliconCompiler's Documentation!

**Version**:
0.38.11

**Useful Links**:
[What is SiliconCompiler?](https://docs.siliconcompiler.com/en/latest/user_guide/what_is_sc.html#what-is-sc) | [Installation](https://docs.siliconcompiler.com/en/latest/user_guide/installation.html#installation) | [GitHub Repo](https://github.com/siliconcompiler/siliconcompiler) | [File an Issue](https://github.com/siliconcompiler/siliconcompiler/issues)

SiliconCompiler is an open source, modular build system that automates translation
from hardware design source code to silicon ("make for silicon").


## Getting started

**New here?**

[Install it](https://docs.siliconcompiler.com/en/latest/user_guide/installation.html#installation), then [run the demo](https://docs.siliconcompiler.com/en/latest/user_guide/quickstart.html#quickstart-guide)
-- [RTL](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-RTL) to [GDS](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-GDSII) in thirteen lines.
[What is SiliconCompiler?](https://docs.siliconcompiler.com/en/latest/user_guide/what_is_sc.html#what-is-sc)

**Bringing your own design?**

The [User Guide](https://docs.siliconcompiler.com/en/latest/user_guide/index.html#user-guide) runs pre-defined flows on your own RTL.
Start by [bringing your own design](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/own_design.html#own-design-tutorial), or
[lint it](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/lint.html#lint-tutorial) first -- no EDA tools needed.

**Looking something up?**

The [Reference Manual](https://docs.siliconcompiler.com/en/latest/reference_manual/index.html#reference-manual) has the
[schema](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#schema) and the [Python API](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#schema-api).
[How do I...?](https://docs.siliconcompiler.com/en/latest/user_guide/howto.html#howto) and the [FAQ](https://docs.siliconcompiler.com/en/latest/user_guide/faq.html#faq) answer by task.

**Extending SiliconCompiler?**

The [Development Guide](https://docs.siliconcompiler.com/en/latest/development_guide/index.html#development-guide) covers your own tools,
flows, targets, PDKs and libraries, and
[packaging them](https://docs.siliconcompiler.com/en/latest/development_guide/external_libraries.html#dev-external-libraries).
[Contributing](https://docs.siliconcompiler.com/en/latest/development_guide/contribution.html#contributing) covers review.


## I want to...

Every page below is one click from here, grouped by what you are trying to do.


### Get something running

- [Install SiliconCompiler](https://docs.siliconcompiler.com/en/latest/user_guide/installation.html#installation) -- `pip install siliconcompiler`, plus the tools a local flow needs.
- [Run the demo build](https://docs.siliconcompiler.com/en/latest/user_guide/quickstart.html#quickstart-guide) -- RTL to GDS, walked through line by line.
- [Check my RTL for mistakes](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/lint.html#lint-tutorial) -- the quickest thing to try: the default linter needs no EDA tools at all.
- [Simulate, or prove a property formally](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/simulate.html#simulate-tutorial) -- Verilator, Icarus, cocotb, and viewing the waveform.
- [Build my own design](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/own_design.html#own-design-tutorial) -- what to change when the design is yours.
- [Work out why a run failed](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/debug.html#debug-tutorial) -- reading logs, metrics and the failing node.


### Run it somewhere else

- [Run remotely](https://docs.siliconcompiler.com/en/latest/user_guide/remote_processing.html#remote-processing) -- compile against a server you or your organization operates.
- [Run inside a container](https://docs.siliconcompiler.com/en/latest/user_guide/docker.html#docker) -- the supported route on Windows.
- [Run steps in parallel](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/parallel.html#parallel-execution) -- more than one node at a time.
- [Run on a cluster](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/cluster.html#cluster-tutorial) -- Slurm and friends.
- [Run builds in CI](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/ci.html#ci-tutorial) -- keeping a design building on every commit.
- [Watch a build while it runs](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/dashboard_tutorial.html#dashboard-tutorial) -- the web dashboard.
- [Get an email when a job finishes](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/emails.html#emails) -- job status notifications.


### Take a design further

- [Build an SoC with a memory](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/picorv32_ram.html#picorv32-example) -- a processor and an SRAM macro.
- [Target an FPGA](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/fpga.html#fpga-tutorial) -- [bitstreams](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-bitstream) instead of masks.
- [Wrap a design in an IO pad ring](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/padring.html#padring-tutorial) -- pads, corners, bond pads and a core power grid.
- [Reuse a block that is already hardened](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/hardened.html#hardened-modules) -- instantiating a macro.
- [Harden a parameterized module](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/uniquify.html#uniquify-modules) -- one module, several configurations.
- [Write RTL in something other than Verilog](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/hw_frontends.html#hw-frontends) -- Chisel, Migen/Amaranth, Bluespec and more.
- [Turn a machine learning model into silicon](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/soda.html#soda-tutorial) -- MLIR in, GDSII out, via SODA Synthesizer.
- [Improve the parasitic estimate](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/pex_calibration.html#pex-calibration) -- calibrating against a golden extraction.
- [Sweep a parameter across many jobs](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/multi_job_flows.html#multi-job-flows) -- multi-job flows and automation.
- [Build my own flow](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/custom_flow.html#custom-flow-tutorial) -- wiring tasks into a graph of your own.
- [Use commercial tools](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/commercial_tools.html#commercial-tools) -- Synopsys, Cadence and Siemens flows.
- [Browse the example designs](https://docs.siliconcompiler.com/en/latest/user_guide/examples.html#examples) -- every example in the repository, built and pictured.


### When something is wrong

- [Frequently asked questions](https://docs.siliconcompiler.com/en/latest/user_guide/faq.html#faq) -- the questions that come up most.
- [How do I...?](https://docs.siliconcompiler.com/en/latest/user_guide/howto.html#howto) -- a task-oriented index of the calls you need.
- [Look up a term](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#glossary) -- the glossary.
- [Port code written against the Chip API](https://docs.siliconcompiler.com/en/latest/user_guide/migration.html#migration-guide) -- `Chip` was removed in 0.35.0; this maps the old calls to the current ones.
- [File an issue](https://github.com/siliconcompiler/siliconcompiler/issues) -- if you cannot find something, or something is not working, the SiliconCompiler team is happy to help.


### Extend it

- [Add a tool, flow, target, PDK or library](https://docs.siliconcompiler.com/en/latest/development_guide/index.html#development-guide) -- the Development Guide.
- [Package a library so others can install it](https://docs.siliconcompiler.com/en/latest/development_guide/external_libraries.html#dev-external-libraries) -- turning modules into a `pip`-installable distribution.
- [Contribute to SiliconCompiler](https://docs.siliconcompiler.com/en/latest/development_guide/contribution.html#contributing) -- where a new module belongs, and how to get it reviewed.


## Supported technologies

| Type | Supported |
| --- | --- |
| Languages | C, Verilog, SV, VHDL, Chisel, Migen/Amaranth, Bluespec, [MLIR](https://en.wikipedia.org/wiki/MLIR_(software)) |
| Simulation | Verilator, Icarus, GHDL, Xyce |
| Synthesis | Yosys, Vivado, Synopsys, Cadence |
| ASIC APR | OpenROAD, Synopsys, Cadence |
| FPGA APR | VPR, nextpnr, Vivado |
| Layout Viewer | Klayout, OpenROAD, Cadence, Synopsys |
| DRC/LVS | Klayout, Magic, Synopsys, Siemens |
| Open PDKs | sky130, ihp130, gf180, asap7, freepdk45, gt2n, icsprout55, interposer -- all shipped by [lambdapdk](https://github.com/siliconcompiler/lambdapdk) |
| Foundry PDKs | gf12lp, gf22fdx, intel16 -- require a foundry agreement; see [packaging an external library](https://docs.siliconcompiler.com/en/latest/development_guide/external_libraries.html#dev-external-libraries) |


## Authors

SiliconCompiler project authors in chronological order: Andreas Olofsson, William Ransohoff, Noah Moroze, Zachary Yedidia, Massimiliano Giacometti, Kimia Talaei, Peter Gadfort, Aulihan Teng, Peter Grossmann, Gabriel Aguirre, Martin Troiber, Ciprian Antoci.


---

Source: https://docs.siliconcompiler.com/en/latest/user_guide/index.html

## User Guide

This guide provides an overview for users.
You will also want to look at API References for details.

Getting Started[What is SiliconCompiler?](https://docs.siliconcompiler.com/en/latest/user_guide/what_is_sc.html)[Installation](https://docs.siliconcompiler.com/en/latest/user_guide/installation.html)[Quickstart guide](https://docs.siliconcompiler.com/en/latest/user_guide/quickstart.html)[Docker guide](https://docs.siliconcompiler.com/en/latest/user_guide/docker.html)[Running remotely](https://docs.siliconcompiler.com/en/latest/user_guide/remote_processing.html)

Fundamentals[Design & compilation data](https://docs.siliconcompiler.com/en/latest/user_guide/data_model.html)[Compilation process](https://docs.siliconcompiler.com/en/latest/user_guide/execution_model.html)[Directory structures](https://docs.siliconcompiler.com/en/latest/user_guide/directories.html)[Checklists and signoff](https://docs.siliconcompiler.com/en/latest/user_guide/checklist.html)

Tutorials: First runs[Lint your RTL](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/lint.html)[Simulate and verify](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/simulate.html)[Bringing your own design](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/own_design.html)[When a run fails](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/debug.html)

Tutorials: Real designs[Building your own SoC](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/picorv32_ram.html)[Build for an FPGA](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/fpga.html)[Hardware design frontends](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/hw_frontends.html)[From a model to silicon (SODA)](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/soda.html)[Implementing an IO pad ring](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/padring.html)[Instantiating a hardened module in a design](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/hardened.html)[Hardening parameterized modules (uniquify)](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/uniquify.html)[Calibrating the parasitic estimate (PEX)](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/pex_calibration.html)

Tutorials: Scaling up[Multi-job flows and automation](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/multi_job_flows.html)[Parallel job execution](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/parallel.html)[Running on a cluster](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/cluster.html)[Running builds in CI](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/ci.html)[Authoring a custom flow](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/custom_flow.html)[Using commercial tools](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/commercial_tools.html)[Using the dashboard](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/dashboard_tutorial.html)[Job status emails](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/emails.html)

Examples[Example designs](https://docs.siliconcompiler.com/en/latest/user_guide/examples.html)

Appendix[Glossary](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html)[Frequently asked questions](https://docs.siliconcompiler.com/en/latest/user_guide/faq.html)[How do I...?](https://docs.siliconcompiler.com/en/latest/user_guide/howto.html)[Migrating from the Chip API](https://docs.siliconcompiler.com/en/latest/user_guide/migration.html)


---

Source: https://docs.siliconcompiler.com/en/latest/user_guide/what_is_sc.html

## What is SiliconCompiler?

SiliconCompiler is an open source, modular, build system that automates translation from hardware design source code to silicon ("make for silicon").

> **Seealso**
> The [glossary](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#glossary) defines the vocabulary used throughout this
> documentation -- both SiliconCompiler concepts such as [fileset](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-fileset) and
> [flowgraph](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-flowgraph), and the hardware design terms such as [RTL](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-RTL) and
> [GDSII](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-GDSII) that appear in tool output.


### Motivation

Silicon had an enormous positive impact on the world over the last 50 years and it is a social imperative that we surf the exponential [Moore's Law](https://en.wikipedia.org/wiki/Moore%27s_law) as long as possible.
Extreme hardware specialization is the only viable path for extending the current exponential electronics improvement trajectory indefinitely, but the path is currently blocked by the high engineering effort of chip design.

Hardware specialization for a long tail of future applications will require the creation of completely automated end-to-end compilers that are orders of magnitude faster than today's tools.
The enormity of these challenges means single machine execution and monolithic single company efforts are unlikely to be sufficient.
In this work, we take a distributed systems approach to compilers, with the goal of creating infrastructure that scales to thousands of developers and millions of servers.


### Our Approach

The SiliconCompiler project is based on a standardized [Schema](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#schema) that supports orthogonal combinations of [design](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-design), [tools](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-tool), and Process Design Kits ([PDKs](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-PDK)). The schema design philosophy is to "make the complex possible while keeping the simple simple".

To simplify [flow](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-flow) development, the project incorporates a simple object oriented [Python API](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#schema-api). The API includes abstracted set/get access to the Schema, a [flowgraph](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-flowgraph) based parallel programming model, and a suite of utility functions for compilation setup and [metric](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-metric) tracking.

The expansive data schema, standardized plug-in interfaces, and built-in dynamic module search functionality enables SiliconCompiler to scale effectively to a large number of tools and PDKs.
The reference manual serves as a good starting point for folks who want to add their own PDKs and tools.

To further reduce design access barriers, the project also supports a [client-server](https://docs.siliconcompiler.com/en/latest/user_guide/remote_processing.html#remote-processing) execution model that leverages the cloud to: 1) reduce tool installation barriers, 2) reduce the barrier to massively parallel elastic compute, and 3) address the NDA barrier for PDK and EDA tools.


### Supported Technologies

| Type | Supported |
| --- | --- |
| Languages | C, Verilog, SV, VHDL, Chisel, Migen/Amaranth, Bluespec, [MLIR](https://en.wikipedia.org/wiki/MLIR_(software)) |
| Simulation | Verilator, Icarus, GHDL, Xyce |
| Synthesis | Yosys, Vivado, Synopsys, Cadence |
| ASIC APR | OpenROAD, Synopsys, Cadence |
| FPGA APR | VPR, nextpnr, Vivado |
| Layout Viewer | Klayout, OpenROAD, Cadence, Synopsys |
| DRC/LVS | Klayout, Magic, Synopsys, Siemens |
| Open PDKs | sky130, ihp130, gf180, asap7, freepdk45, gt2n, icsprout55, interposer -- all shipped by [lambdapdk](https://github.com/siliconcompiler/lambdapdk) |
| Foundry PDKs | gf12lp, gf22fdx, intel16 -- require a foundry agreement; see [packaging an external library](https://docs.siliconcompiler.com/en/latest/development_guide/external_libraries.html#dev-external-libraries) |


### Authors

SiliconCompiler project authors in chronological order: Andreas Olofsson, William Ransohoff, Noah Moroze, Zachary Yedidia, Massimiliano Giacometti, Kimia Talaei, Peter Gadfort, Aulihan Teng, Peter Grossmann, Gabriel Aguirre, Martin Troiber, Ciprian Antoci.


---

Source: https://docs.siliconcompiler.com/en/latest/user_guide/installation.html

## Installation


### Installing Python

Before installing the SiliconCompiler package you will need to set up a Python environment.
The following sections will walk you through how to install the appropriate python dependencies and start a [Python virtual environment](https://docs.python.org/3/library/venv.html).
Note that at any time, if you need to exit the Python virtual environment, type 'deactivate' and hit enter.


#### Ubuntu (>=22.04)

Open up a terminal and enter the following command sequence.

> **Note**
> SiliconCompiler requires Python 3.10 or newer. Ubuntu 22.04 is the first
> release to ship a compatible `python3` by default. For Ubuntu 20.04, see the
> section below.

```bash
python3 --version                                      # check for Python 3.10+
sudo apt update                                        # update package information
sudo apt install python3-dev python3-pip python3-venv  # install dependencies
python3 -m venv  ./venv                                # create a virtual env
source ./venv/bin/activate                             # active virtual env (bash/zsh)
```

> **Note**
> If you plan to generate any docs or create any flowgraphs, you'll also need to install Graphviz.
> You can make sure you have this dependency by running `sudo apt install graphviz xdot`.

Skip ahead to SC Install.


#### Ubuntu 20.04

> **Warning**
> Ubuntu 20.04 is only minimally supported. Pre-built tool scripts
> (`sc-install`) still exist for it but are no longer actively maintained, so
> some tools may fail to build. Installing the SiliconCompiler Python package
> itself works, but consider upgrading to Ubuntu 22.04 or newer.

Ubuntu 20.04 ships Python 3.8 by default, which is older than the Python 3.10
required by SiliconCompiler. Install a newer interpreter from the `deadsnakes`
PPA, then create the virtual environment with it.

```bash
sudo apt update                                            # update package information
sudo apt install software-properties-common               # provides add-apt-repository
sudo add-apt-repository ppa:deadsnakes/ppa                 # add the deadsnakes PPA
sudo apt update
sudo apt install python3.11 python3.11-dev python3.11-venv # install Python 3.11
python3.11 --version                                       # check for Python 3.10+
python3.11 -m venv ./venv                                  # create a virtual env
source ./venv/bin/activate                                 # active virtual env (bash/zsh)
```

> **Note**
> If you plan to generate any docs or create any flowgraphs, you'll also need to install Graphviz.
> You can make sure you have this dependency by running `sudo apt install graphviz xdot`.

Skip ahead to SC Install.


#### RHEL (>=RHEL 8)

Open up a terminal and enter the following command sequence. This also applies to
compatible distributions such as Rocky Linux and AlmaLinux.

> **Note**
> SiliconCompiler requires Python 3.10 or newer. The default `python3` on RHEL 8
> and RHEL 9 is older than this, so install a newer interpreter (for example,
> `python3.11`) as shown below.

```bash
sudo dnf install python3.11 python3.11-pip  # install Python 3.11
python3.11 --version                        # check for Python 3.10+
python3.11 -m venv ./venv                   # create a virtual env
source ./venv/bin/activate                  # active virtual env (bash/zsh)
```

> **Note**
> If you plan to generate any docs or create any flowgraphs, you'll also need to install Graphviz.
> You can make sure you have this dependency by running `sudo dnf install graphviz xdot`

Skip ahead to SC Install.


#### macOS

Open up a terminal and enter the following command sequence.

> **Note**
> These instructions use [Homebrew](https://brew.sh), which supports only the
> most recent macOS releases. Both Apple Silicon and Intel Macs are supported,
> but they install Homebrew to different prefixes -- the installer prints the
> correct `shellenv` line for your machine under "Next steps".

```bash
/bin/bash -c "$(curl -fsSL https://raw.githubusercontent.com/Homebrew/install/HEAD/install.sh)"
# /opt/homebrew on Apple Silicon, /usr/local on Intel -- try both
eval "$(/opt/homebrew/bin/brew shellenv 2>/dev/null || /usr/local/bin/brew shellenv)"
brew update
brew install python
python3 --version                                      # check for Python 3.10+
python3 -m venv  ./venv                                # create a virtual env
source ./venv/bin/activate                             # active virtual env
```

> **Note**
> If you plan to generate any docs or create any flowgraphs, you'll also need to install Graphviz.
> You can make sure you have this dependency by running `brew install graphviz xdot`

Skip ahead to SC Install.


#### Windows (>= Windows 10)

Install the latest Python package from [Python.org](https://www.python.org/downloads) using the Windows installer.
Open up a Windows shell by:

1. Pressing the 'Windows' key
2. Typing 'cmd', and pressing enter.

From the command shell, enter the following sequence to create and activate a virtual environment.
Note that the Python.org installer provides `python`, not `python3` -- on Windows, `python3` usually opens the Microsoft Store instead of running the interpreter.

```doscon
python --version                                       # check for Python 3.10+
python -m venv  .\venv
.\venv\Scripts\activate
```

> **Note**
> If you plan to generate any docs or create any flowgraphs, you'll also need to [install Graphviz](https://graphviz.org/download/#windows).


### Installing SiliconCompiler

After you've got the python dependencies installed, you will need to install SiliconCompiler.
There are a few different ways to do this:

1. The recommended method is to install the last stable version published to [pypi.org](https://pypi.org/project/siliconcompiler/), or
2. You can install directly from the git repository (best for developers).


#### Install from pypi.org

SiliconCompiler can be installed directly from [pypi.org](https://pypi.org/project/siliconcompiler/) using pip.
Activate your [Python Virtual Environment](https://docs.python.org/3/library/venv.html) and follow the instructions below.

```bash
(venv) pip install --upgrade siliconcompiler    # install SiliconCompiler in venv
(venv) pip show siliconcompiler                 # will display SiliconCompiler package information
```

To confirm your installation:

```bash
(venv) python3 -c "import siliconcompiler;print(siliconcompiler.__version__)"
```

The expected version should be printed to the display:

```
0.38.11
```

Skip to asic demo.


#### Install from GitHub Repo (Linux/MacOS)

You can also install SiliconCompiler from the latest [SiliconCompiler GitHub Repository](https://github.com/siliconcompiler/siliconcompiler).

**Install SiliconCompiler**

Finally, to clone and install SiliconCompiler, run the following:

```
(venv) git clone -b v0.38.11 https://github.com/siliconcompiler/siliconcompiler
(venv) cd siliconcompiler
(venv) pip install --upgrade pip
(venv) pip install -e .
```

To confirm your installation:

```bash
(venv) python3 -c "import siliconcompiler;print(siliconcompiler.__version__)"
```

The expected version should be printed to the display:

```
0.38.11
```


### Optional features

A default install carries what a local flow needs and nothing more. The
features below are packaged as extras, installed by naming them in brackets:

```bash
(venv) pip install --upgrade "siliconcompiler[dashboard]"       # one extra
(venv) pip install --upgrade "siliconcompiler[dashboard,server]"  # several
```

| Extra | Adds |
| --- | --- |
| `dashboard` | The [web dashboard](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/dashboard_tutorial.html#dashboard-tutorial), and the `pandas` DataFrames returned by [`MetricSchema.summary_table()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.metric.MetricSchema.summary_table) and `report.make_metric_dataframe()`. Printing a summary with [`Project.summary()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.project.Project.summary) needs neither. |
| `server` | Running your own [remote server](https://docs.siliconcompiler.com/en/latest/user_guide/remote_processing.html#custom-servers) with [sc-server](https://docs.siliconcompiler.com/en/latest/reference_manual/apps.html#app-sc-server). Submitting jobs to someone else's server does not need it. |
| `s3` | Fetching a [dataroot](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-dataroot) from an `s3://` source: Amazon S3, or a store that speaks its API. See [Dataroot: fetch from S3 or an S3-compatible store](https://docs.siliconcompiler.com/en/latest/user_guide/howto.html#howto-s3-dataroot). |
| `cocotb` | The [cocotb](https://www.cocotb.org/) testbench flow. |
| `optimizer` | Parameter optimization through [google-vizier](https://github.com/google/vizier). |
| `docs` | Building this documentation. |
| `test` | Running the test suite. Tests covering an extra that is not installed report themselves as skipped. |

SiliconCompiler itself keeps working whether or not any of these are present;
only the feature stops. There is no `pip uninstall` of an extra, though:
extras are requirement groups rather than something pip records and can later
remove as a unit, and the packages one pulls in are shared with anything else
in the environment that needs them, so removing them by hand can break that
other software. To try an extra out without committing to it, install it into
a throwaway virtual environment.


### ASIC Demo

Now that you have installed SiliconCompiler, you can test your installation by running a quick demo through the ASIC design flow.
The demo runs the EDA tools in containers with the [Docker scheduler](https://docs.siliconcompiler.com/en/latest/user_guide/docker.html#docker), so nothing beyond Docker and SiliconCompiler needs to be installed -- see [Using SiliconCompiler with Docker](https://docs.siliconcompiler.com/en/latest/user_guide/docker.html#docker) if Docker is not running on your machine yet.

```bash
python -m siliconcompiler.demos.asic_demo -scheduler docker
```

`python` rather than `python3`: a virtual environment provides both on every
platform, and Windows has only `python`. Outside an activated environment on
Linux or macOS, use `python3`.

The first run also pulls the container image, so it takes a few minutes.
It should end with a results directory where you can find `png` file which displays your results.
It should look something like this:

See [Quickstart guide](https://docs.siliconcompiler.com/en/latest/user_guide/quickstart.html#quickstart-guide) next to go through the design and run details of the quick demo above.


### External Tools

If you wish to run the tools natively instead of in containers as in the quick asic demo target above, there will be some tools you need to install first.
You can use the provided [sc-install](https://docs.siliconcompiler.com/en/latest/reference_manual/apps.html#app-sc-install) application to install the tools or view the scripts directly in the list below.

> **Note**
> To install the recommended tools for an asic flow, use: `sc-install -group asic` or for an fpga flow `sc-install -group fpga`.
> To see a full list of supported groups see [sc-install](https://docs.siliconcompiler.com/en/latest/reference_manual/apps.html#app-sc-install).
> Links to individual tool installation instructions and platform limitations can be found in the [pre-defined tool drivers](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/tools.html#builtin-tools).
>
> We have provided the following helper install scripts for this minimum toolset for the ASIC flow as well as other external tools, but keep in mind that they are for reference only.
> If you should run into issues, please consult the official download instructions for the tool itself.
> All official tool documentation links can be found in the [pre-defined tool drivers](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/tools.html#builtin-tools) section.

**Root access.** `sc-install` installs into `~/.local` by default, which
needs no root of its own, and root is needed only if a tool's prerequisite
packages are missing. Each script asks the package manager what is already
installed -- `dpkg-query` on Ubuntu, `rpm` on RHEL -- and calls `sudo` only
for what is not there. A machine whose prerequisites are already in place -- a
shared server, for instance -- can therefore have its tools installed and updated
by an ordinary user. A handful of scripts still need root regardless, because
they install a system package rather than build into the prefix; KLayout is the
main one.

**Reading the table.** Each row is a tool; each column is a platform. A cell
links to the install script for that combination, and a **blank cell means no
script is provided** -- not that the tool is unavailable. You may still be able
to install it from your distribution's packages or from the tool's own
instructions, linked from the [pre-defined tool drivers](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/tools.html#builtin-tools).

Coverage is not uniform, and the gaps matter for the ASIC flow:

- **RHEL 9, Ubuntu 22.04 / 24.04 / 26.04** have scripts for the full ASIC
  toolchain.
- **RHEL 8 and Ubuntu 20.04** have scripts for KLayout only. There are no
  scripts for Yosys, OpenROAD or OpenSTA on those platforms, so the ASIC flow
  cannot be installed this way -- use a newer distribution, the
  [Docker image](https://docs.siliconcompiler.com/en/latest/user_guide/docker.html#docker), or a [remote run](https://docs.siliconcompiler.com/en/latest/user_guide/remote_processing.html#remote-processing).

|  |  |  |  |  |  |  |
| --- | --- | --- | --- | --- | --- | --- |
| tool | rhel8 | rhel9 | ubuntu20 | ubuntu22 | ubuntu24 | ubuntu26 |
| [bambu](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/tools.html#tool-bambu) |  |  | [ubuntu20](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu20/install-bambu.sh) | [ubuntu22](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu22/install-bambu.sh) | [ubuntu24](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu24/install-bambu.sh) | [ubuntu26](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu26/install-bambu.sh) |
| [bluespec](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/tools.html#tool-bluespec) |  |  | [ubuntu20](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu20/install-bluespec.sh) | [ubuntu22](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu22/install-bluespec.sh) | [ubuntu24](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu24/install-bluespec.sh) | [ubuntu26](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu26/install-bluespec.sh) |
| [chisel](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/tools.html#tool-chisel) | [rhel8](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/rhel8/install-chisel.sh) | [rhel9](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/rhel9/install-chisel.sh) | [ubuntu20](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu20/install-chisel.sh) | [ubuntu22](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu22/install-chisel.sh) | [ubuntu24](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu24/install-chisel.sh) | [ubuntu26](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu26/install-chisel.sh) |
| [ghdl](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/tools.html#tool-ghdl) |  |  | [ubuntu20](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu20/install-ghdl.sh) | [ubuntu22](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu22/install-ghdl.sh) | [ubuntu24](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu24/install-ghdl.sh) | [ubuntu26](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu26/install-ghdl.sh) |
| [gtkwave](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/tools.html#tool-gtkwave) |  | [rhel9](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/rhel9/install-gtkwave.sh) | [ubuntu20](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu20/install-gtkwave.sh) | [ubuntu22](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu22/install-gtkwave.sh) | [ubuntu24](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu24/install-gtkwave.sh) | [ubuntu26](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu26/install-gtkwave.sh) |
| [icarus](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/tools.html#tool-icarus) | [rhel8](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/rhel8/install-icarus.sh) | [rhel9](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/rhel9/install-icarus.sh) | [ubuntu20](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu20/install-icarus.sh) | [ubuntu22](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu22/install-icarus.sh) | [ubuntu24](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu24/install-icarus.sh) | [ubuntu26](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu26/install-icarus.sh) |
| [icepack](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/tools.html#tool-icepack) |  |  | [ubuntu20](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu20/install-icepack.sh) | [ubuntu22](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu22/install-icepack.sh) | [ubuntu24](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu24/install-icepack.sh) | [ubuntu26](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu26/install-icepack.sh) |
| [keplerformal](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/tools.html#tool-keplerformal) |  |  |  | [ubuntu22](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu22/install-keplerformal.sh) | [ubuntu24](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu24/install-keplerformal.sh) | [ubuntu26](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu26/install-keplerformal.sh) |
| [klayout](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/tools.html#tool-klayout) | [rhel8](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/rhel8/install-klayout.sh) | [rhel9](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/rhel9/install-klayout.sh) | [ubuntu20](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu20/install-klayout.sh) | [ubuntu22](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu22/install-klayout.sh) | [ubuntu24](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu24/install-klayout.sh) | [ubuntu26](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu26/install-klayout.sh) |
| [magic](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/tools.html#tool-magic) | [rhel8](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/rhel8/install-magic.sh) | [rhel9](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/rhel9/install-magic.sh) | [ubuntu20](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu20/install-magic.sh) | [ubuntu22](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu22/install-magic.sh) | [ubuntu24](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu24/install-magic.sh) | [ubuntu26](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu26/install-magic.sh) |
| [mlir](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/tools.html#tool-mlir) |  |  | [ubuntu20](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu20/install-mlir.sh) | [ubuntu22](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu22/install-mlir.sh) | [ubuntu24](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu24/install-mlir.sh) | [ubuntu26](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu26/install-mlir.sh) |
| [montage](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/tools.html#tool-montage) | [rhel8](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/rhel8/install-montage.sh) | [rhel9](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/rhel9/install-montage.sh) | [ubuntu20](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu20/install-montage.sh) | [ubuntu22](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu22/install-montage.sh) | [ubuntu24](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu24/install-montage.sh) | [ubuntu26](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu26/install-montage.sh) |
| [netgen](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/tools.html#tool-netgen) | [rhel8](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/rhel8/install-netgen.sh) | [rhel9](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/rhel9/install-netgen.sh) | [ubuntu20](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu20/install-netgen.sh) | [ubuntu22](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu22/install-netgen.sh) | [ubuntu24](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu24/install-netgen.sh) | [ubuntu26](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu26/install-netgen.sh) |
| [nextpnr](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/tools.html#tool-nextpnr) |  |  | [ubuntu20](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu20/install-nextpnr.sh) | [ubuntu22](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu22/install-nextpnr.sh) | [ubuntu24](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu24/install-nextpnr.sh) | [ubuntu26](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu26/install-nextpnr.sh) |
| [openroad](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/tools.html#tool-openroad) |  | [rhel9](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/rhel9/install-openroad.sh) |  | [ubuntu22](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu22/install-openroad.sh) | [ubuntu24](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu24/install-openroad.sh) | [ubuntu26](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu26/install-openroad.sh) |
| [opensta](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/tools.html#tool-opensta) |  | [rhel9](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/rhel9/install-opensta.sh) |  | [ubuntu22](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu22/install-opensta.sh) | [ubuntu24](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu24/install-opensta.sh) | [ubuntu26](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu26/install-opensta.sh) |
| [sby](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/tools.html#tool-sby) |  |  |  | [ubuntu22](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu22/install-sby.sh) | [ubuntu24](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu24/install-sby.sh) | [ubuntu26](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu26/install-sby.sh) |
| slurm |  |  | [ubuntu20](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu20/install-slurm.sh) | [ubuntu22](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu22/install-slurm.sh) | [ubuntu24](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu24/install-slurm.sh) | [ubuntu26](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu26/install-slurm.sh) |
| [soda](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/tools.html#tool-soda) |  |  | [ubuntu20](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu20/install-soda.sh) | [ubuntu22](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu22/install-soda.sh) | [ubuntu24](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu24/install-soda.sh) | [ubuntu26](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu26/install-soda.sh) |
| [surelog](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/tools.html#tool-surelog) |  | [rhel9](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/rhel9/install-surelog.sh) | [ubuntu20](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu20/install-surelog.sh) | [ubuntu22](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu22/install-surelog.sh) | [ubuntu24](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu24/install-surelog.sh) | [ubuntu26](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu26/install-surelog.sh) |
| [surfer](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/tools.html#tool-surfer) |  |  |  | [ubuntu22](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu22/install-surfer.sh) | [ubuntu24](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu24/install-surfer.sh) | [ubuntu26](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu26/install-surfer.sh) |
| [sv2v](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/tools.html#tool-sv2v) | [rhel8](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/rhel8/install-sv2v.sh) | [rhel9](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/rhel9/install-sv2v.sh) | [ubuntu20](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu20/install-sv2v.sh) | [ubuntu22](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu22/install-sv2v.sh) | [ubuntu24](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu24/install-sv2v.sh) | [ubuntu26](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu26/install-sv2v.sh) |
| vcd2fst |  |  |  | [ubuntu22](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu22/install-vcd2fst.sh) | [ubuntu24](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu24/install-vcd2fst.sh) | [ubuntu26](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu26/install-vcd2fst.sh) |
| verible | [rhel8](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/rhel8/install-verible.sh) | [rhel9](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/rhel9/install-verible.sh) | [ubuntu20](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu20/install-verible.sh) | [ubuntu22](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu22/install-verible.sh) | [ubuntu24](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu24/install-verible.sh) | [ubuntu26](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu26/install-verible.sh) |
| [verilator](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/tools.html#tool-verilator) | [rhel8](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/rhel8/install-verilator.sh) | [rhel9](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/rhel9/install-verilator.sh) | [ubuntu20](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu20/install-verilator.sh) | [ubuntu22](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu22/install-verilator.sh) | [ubuntu24](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu24/install-verilator.sh) | [ubuntu26](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu26/install-verilator.sh) |
| [vpr](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/tools.html#tool-vpr) |  | [rhel9](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/rhel9/install-vpr.sh) |  | [ubuntu22](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu22/install-vpr.sh) | [ubuntu24](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu24/install-vpr.sh) | [ubuntu26](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu26/install-vpr.sh) |
| wildebeest |  | [rhel9](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/rhel9/install-wildebeest.sh) |  | [ubuntu22](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu22/install-wildebeest.sh) | [ubuntu24](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu24/install-wildebeest.sh) | [ubuntu26](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu26/install-wildebeest.sh) |
| [xdm](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/tools.html#tool-xdm) | [rhel8](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/rhel8/install-xdm.sh) | [rhel9](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/rhel9/install-xdm.sh) | [ubuntu20](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu20/install-xdm.sh) | [ubuntu22](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu22/install-xdm.sh) | [ubuntu24](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu24/install-xdm.sh) | [ubuntu26](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu26/install-xdm.sh) |
| [xyce](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/tools.html#tool-xyce) |  | [rhel9](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/rhel9/install-xyce.sh) | [ubuntu20](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu20/install-xyce.sh) | [ubuntu22](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu22/install-xyce.sh) | [ubuntu24](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu24/install-xyce.sh) | [ubuntu26](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu26/install-xyce.sh) |
| [yosys](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/tools.html#tool-yosys) |  | [rhel9](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/rhel9/install-yosys.sh) |  | [ubuntu22](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu22/install-yosys.sh) | [ubuntu24](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu24/install-yosys.sh) | [ubuntu26](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu26/install-yosys.sh) |
| yosys-moosic |  | [rhel9](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/rhel9/install-yosys-moosic.sh) |  | [ubuntu22](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu22/install-yosys-moosic.sh) | [ubuntu24](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu24/install-yosys-moosic.sh) | [ubuntu26](https://github.com/siliconcompiler/siliconcompiler/blob/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/siliconcompiler/toolscripts/ubuntu26/install-yosys-moosic.sh) |

The following entries have an install script but no driver page, so they appear above without a link. They are supporting tools rather than flow steps:

**`slurm`**

  Workload manager for HPC clusters. SiliconCompiler dispatches jobs to it rather than driving it as a compilation tool; see the Slurm setup appendix.

**`vcd2fst`**

  Converts VCD waveform files to the more compact FST format. Invoked by other tasks rather than run directly.

**`verible`**

  SystemVerilog parser, style linter and formatter. Used by SiliconCompiler's own lint gate in CI, not by any compilation flow.

**`wildebeest`**

  FPGA synthesis tool, built on Yosys.

**`yosys-moosic`**

  Yosys plugin for logic locking and supply-chain security. Installed alongside Yosys and driven through it.

> **Note**
> **Windows.** SiliconCompiler itself installs and runs on Windows, and is
> tested there on every commit, but that testing does not cover running EDA
> tools. No install scripts are provided for Windows and the local flows are
> not supported on it.
>
> To compile a design from Windows, use a [remote run](https://docs.siliconcompiler.com/en/latest/user_guide/remote_processing.html#remote-processing),
> the [Docker image](https://docs.siliconcompiler.com/en/latest/user_guide/docker.html#docker), or WSL. KLayout is the exception worth
> installing natively: it has Windows builds, and [sc-show](https://docs.siliconcompiler.com/en/latest/reference_manual/apps.html#app-sc-show)
> will use it to view results downloaded from a remote run.

See [Quickstart guide](https://docs.siliconcompiler.com/en/latest/user_guide/quickstart.html#quickstart-guide) next to see how to run locally on your machine with these tools.


---

Source: https://docs.siliconcompiler.com/en/latest/user_guide/quickstart.html

## Quickstart guide

If you've completed the [Installation](https://docs.siliconcompiler.com/en/latest/user_guide/installation.html#installation) section and were able to run the [ASIC Demo](https://docs.siliconcompiler.com/en/latest/user_guide/installation.html#asic-demo), you will have completed a simple containerized run through an [ASIC](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-ASIC) design flow!

In the following sections, you will find more details about the design, the flow and the results of the run.


### Where the compilation runs

The same script runs either against containerized tools or against tools
installed natively. One line decides which, and it is worth choosing
deliberately before you start:

|  | Docker | Native |
| --- | --- | --- |
| Setup | [Docker](https://docs.siliconcompiler.com/en/latest/user_guide/docker.html#docker) installed and running; nothing else beyond `pip install siliconcompiler`. | Four EDA tools: [Yosys](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/tools.html#tool-yosys), [OpenROAD](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/tools.html#tool-openroad), [OpenSTA](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/tools.html#tool-opensta) and [KLayout](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/tools.html#tool-klayout). See [external tools](https://docs.siliconcompiler.com/en/latest/user_guide/installation.html#external-tools). |
| Where the tools come from | The `sc_runner` image -- one container per [flowgraph node](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-flowgraph-node), started and stopped by SiliconCompiler. | Your own machine. |
| Needs | A network connection the first time, to pull the image. | Nothing; runs offline once the [PDK](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-PDK) is cached. |
| Enable with | `project.option.scheduler.set_name("docker")`, or `-scheduler docker`. | Nothing -- native is the default. |

Either way your design never leaves your machine: both modes read and write your
working directory and nothing else.

Docker is the quickest way to a first result, which is why the
[ASIC Demo](https://docs.siliconcompiler.com/en/latest/user_guide/installation.html#asic-demo) uses it. Native tools are the better default once
you are iterating on a design, and avoid the container startup cost on every
node.


### Design Details

The simple design that was used in the [demo target](https://docs.siliconcompiler.com/en/latest/user_guide/installation.html#asic-demo) is a single clock cycle pulse ("heartbeat") generated by a counter.

examples/heartbeat/heartbeat.v

```verilog
module heartbeat #(
    parameter N = 8
) (
    //inputs
    input      clk,     // clock
    input      nreset,  //async active low reset
    //outputs
    output reg out      //heartbeat
);

    reg [N-1:0] counter_reg;

    always @(posedge clk or negedge nreset) begin
        if (!nreset) begin
            counter_reg <= {(N) {1'b0}};
            out <= 1'b0;
        end else begin
            counter_reg <= counter_reg + 1'b1;
            out <= (counter_reg == {(N) {1'b1}});
        end
    end

endmodule

```

The clock constraint that goes with it is
[heartbeat.sdc](https://github.com/siliconcompiler/siliconcompiler/blob/main/examples/heartbeat/heartbeat.sdc).


### Run Setup

SiliconCompiler includes a Python API to simplify the hardware compilation flow process.
The following code snippet below shows how the [demo design](https://docs.siliconcompiler.com/en/latest/user_guide/installation.html#asic-demo) was loaded in and run through the Python API.

heartbeat.py (remote run)

```python
#!/usr/bin/env python3

from siliconcompiler import ASIC, Design                   # import python package
from siliconcompiler.targets import skywater130_demo

if __name__ == "__main__":
    design = Design("heartbeat")                           # create design object
    design.set_topmodule("heartbeat", fileset="rtl")       # set top module
    design.add_file("heartbeat.v", fileset="rtl")          # add input sources
    design.add_file("heartbeat.sdc", fileset="sdc")        # add input sources
    project = ASIC(design)                                 # create project
    project.add_fileset(["rtl", "sdc"])                    # enable filesets
    skywater130_demo(project)                              # load a pre-defined target
    project.option.scheduler.set_name("docker")            # run the tools in containers
    project.run()                                          # run compilation
    project.summary()                                      # print summary
    project.show()                                         # show layout
```

The following sub-sections will describe each line in more detail.


#### Project and Design Creation

The hardware build flow centers around two main objects: the [`Design`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Design), which holds design-specific information, and the [`ASIC`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.ASIC), which manages project settings and execution.

```python
from siliconcompiler import ASIC, Design

design = Design("heartbeat")
project = ASIC(design)
```


#### Defining the Design

Once the objects are created, we specify the design's top module and add its source files. In this case, heartbeat.v is the Verilog [RTL](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-RTL), and heartbeat.sdc is the [Synopsys Design Constraints](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-SDC) file, which defines the clock.

```python
design.set_topmodule("heartbeat", fileset="rtl")
design.add_file("heartbeat.v", fileset="rtl")
design.add_file("heartbeat.sdc", fileset="sdc")
project.add_fileset(["rtl", "sdc"])
```

`rtl` and `sdc` here are [filesets](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-fileset) -- named groups of input
files that a design carries and a run selects among.


#### Loading a Target

Next, we load a [target](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-target), which bundles a Process Design Kit ([PDK](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-PDK)), [standard cell](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-standard-cell) [libraries](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-library), and a pre-configured compilation [flow](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-flow).

```python
from siliconcompiler.targets import skywater130_demo

skywater130_demo(project)
```


#### Configuring the Run

[`Project.option`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.project.Project.option) is used to configure various settings.
This is the line that chooses between the two modes described above:

```python
project.option.scheduler.set_name("docker")   # run the tools in containers
```

Delete it and the identical script runs the tools installed natively on your own
machine instead:

```python
project.option.scheduler.set_name(None)       # use native tools (the default)
```

Nothing else in the script changes between the two.


#### Executing the Flow

Finally, we execute the flow.
The [`Project.run()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.project.Project.run) method starts the compilation, [`Project.summary()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.project.Project.summary) prints a table of results, and [`Project.show()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.project.Project.show) opens the final layout in a viewer.

```python
project.run()
project.summary()
project.show()
```


### Run Flow

Running this python script directly produces the same results as the [ASIC Demo](https://docs.siliconcompiler.com/en/latest/user_guide/installation.html#asic-demo) target.

```bash
python3 heartbeat.py
```


### Remote Run Controls

When your job starts on a remote server, it will log a job ID which you can use to query your job if you close the terminal window or otherwise interrupt the run before it completes:

```
| INFO    | job0  | remote     | 0  | Your job's reference ID is: 0123456789abcdeffedcba9876543210
```

The job ID is recorded in the job's manifest, which is how the
[sc-remote](https://docs.siliconcompiler.com/en/latest/reference_manual/apps.html#app-sc-remote) CLI app identifies the job -- point it at that
manifest to interact with a running job:

```bash
# Check on a job's progress.
sc-remote -cfg build/<design>/<jobname>/<design>.pkg.json

# Cancel a running job.
sc-remote -cfg build/<design>/<jobname>/<design>.pkg.json -cancel

# Ask the server to delete a job from its active records.
sc-remote -cfg build/<design>/<jobname>/<design>.pkg.json -delete

# Reconnect to an active job.
sc-remote -cfg build/<design>/<jobname>/<design>.pkg.json -reconnect
```

The [sc-remote](https://docs.siliconcompiler.com/en/latest/reference_manual/apps.html#app-sc-remote) app also accepts a -credentials input parameter which works the same way as the [`[option,credentials]`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-project-option-credentials) parameter.

> **Seealso**
> [Directory structures](https://docs.siliconcompiler.com/en/latest/user_guide/directories.html#directory-structures) explains the build tree
> these paths refer to, and where else a run writes.


### Run Results

Your run will first show the SiliconCompiler banner/info, followed by design INFO messages.

As the run goes through each step of the flow, a message will be printed to the screen every 5 seconds.

Then, at the end of the run, a summary table will be printed similar to the one shown below.
This table is generated by calling the [`Project.summary()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.project.Project.summary) function call in your python script above.

All design outputs are located in `build/<design>/<jobname>` -- see
[Directory structures](https://docs.siliconcompiler.com/en/latest/user_guide/directories.html#build-directory) for what is in there.
On a remote run, results are downloaded node by node as each one completes, so when the job finishes your local build directory holds the full results -- the tool logs, reports and output files for every step, including the final [GDS](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-GDSII) -- along with a screenshot of the finished design, `heartbeat.png`:


### Other Ways to Run

Beyond the two modes compared above, there are two more:

- [Remote](https://docs.siliconcompiler.com/en/latest/user_guide/remote_processing.html#remote-processing) -- send the job to a server you or your
  organization operates, for pre-configured tool installations, elastic compute
  or NDA-protected [PDKs](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-PDK).
- [Cluster schedulers](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/cluster.html#cluster-tutorial) -- dispatch
  each node through Slurm, LSF or SGE.


#### Local Run Results

By default, only the summary of each step is printed, in order to not clutter up the screen with tool-specific output.
If you wish to see the output from each tool, you can find the log files associated with each tool in: `build/<design>/<jobname>/<step>/<index>/<step>.log`

If you wish to see all the tool-specific information printed onto the screen, you can turn the [`[option,quiet]`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-project-option-quiet) option off.


#### View Design

For viewing IC layout files ([DEF](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-DEF), GDSII) we recommend installing the open source multi-platform [Klayout viewer](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/tools.html#tool-klayout)  (available for Windows, Linux, and macOS).
Installation instructions for Klayout can be found in the [tools directory](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/tools.html#tool-klayout).

If you have Klayout installed, you can browse your completed design by calling [sc-show](https://docs.siliconcompiler.com/en/latest/reference_manual/apps.html#app-sc-show) directly from the command line as shown below:

```bash
(venv) sc-show -design heartbeat
```

If you want to have this window pop up automatically at the end of your script, you can add [`Project.show()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.project.Project.show) to the end of your python script.

```python
project.show()      # pops open a window with the layout
```


### What Next?

Now that you've quickly run a simple example, you can proceed to a larger example like [building your own soc](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/picorv32_ram.html#picorv32-example), or you can dive deeper into the SiliconCompiler build flow you ran from this quickstart ([asic_demo](https://github.com/siliconcompiler/siliconcompiler/blob/main/siliconcompiler/demos/asic_demo.py)) by looking through how the flow is constructed with the [Design and Compilation Data](https://docs.siliconcompiler.com/en/latest/user_guide/data_model.html#data-model) and [Compilation Process](https://docs.siliconcompiler.com/en/latest/user_guide/execution_model.html#execution-model) in the Fundamentals section.


---

Source: https://docs.siliconcompiler.com/en/latest/user_guide/docker.html

## Using SiliconCompiler with Docker

To run SiliconCompiler flows using our pre-built Docker image, you first need to have Docker installed and running on your system.


### Two ways to use the image

The same image, `ghcr.io/siliconcompiler/sc_runner`, is used in two different
ways, and they are easy to confuse because both are "running SiliconCompiler in
Docker". They differ in *what* goes in the container:

|  | Docker **scheduler** | `docker run` **the whole script** |
| --- | --- | --- |
| Looks like | `project.option.scheduler.set_name("docker")`, or `-scheduler docker` | `docker run --rm -v "$(pwd):/sc_work" ghcr.io/siliconcompiler/sc_runner:latest python3 make.py` |
| What runs in the container | Each [flowgraph node](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-flowgraph-node) -- one container per node, started and stopped by SiliconCompiler | Everything, including SiliconCompiler itself -- one container for the run |
| What runs on your machine | SiliconCompiler, in your own Python environment | Only Docker |
| Needs SiliconCompiler installed? | Yes (`pip install siliconcompiler`) | No |
| Version you get | Yours drives the flow; the image supplies the tools | Whatever the image ships |

**Use the scheduler** for normal work. You keep your own Python environment, your
own SiliconCompiler version, and the dashboard, while the EDA tools come from the
container -- so there is nothing to install and nothing to keep in sync.

**Use** `docker run` when you want to run a script on a machine with nothing
installed but Docker, or to reproduce a result against a pinned image. The
mounted directory (`/sc_work` above) is where the build tree is written, so
results land in your working directory as usual.

The rest of this page sets up the scheduler.

> **Note**
> The scheduler picks its image from [`[option,scheduler,queue]`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-project-option-scheduler-queue) if set,
> then the `SC_DOCKER_IMAGE` environment variable, then
> `ghcr.io/siliconcompiler/sc_runner:v<version>` matching your installed
> SiliconCompiler. Because `queue` is per-node, different steps can run in
> different images.


### 1. Install Docker Desktop

The first step is to install Docker Desktop, which provides an easy-to-use environment for managing containers.
Please follow the official installation instructions for your operating system:

- [Install on Linux](https://docs.docker.com/desktop/setup/install/linux/)
- [Install on Windows](https://docs.docker.com/desktop/setup/install/windows-install/)
- [Install on macOS](https://docs.docker.com/desktop/setup/install/mac-install/)

After installation, start Docker Desktop. We recommend using the default settings when prompted.


### 2. Set Up Your Project

Next, open your preferred command-line terminal and run the commands below that correspond to your operating system.
These commands will create a Python virtual environment, activate it, and install siliconcompiler.


#### Linux / macOS

On a standard terminal (bash or zsh):

```bash
# Create and activate a Python virtual environment
python3 -m venv .venv
source .venv/bin/activate

# Install SiliconCompiler
pip install siliconcompiler
```


#### Windows

On a PowerShell terminal:

```powershell
# Create and activate a Python virtual environment
python -m venv .venv
.\.venv\Scripts\Activate.ps1

# Install SiliconCompiler
pip install siliconcompiler
```


### 3. Run a Test Compilation

With your environment activated and SiliconCompiler installed, you can test your setup by running a simple compilation that uses the Docker scheduler. This command will automatically pull the necessary Docker image and run the flow inside a container.

Execute the following command in the same terminal:

```bash
python -m siliconcompiler.demos.asic_demo -scheduler docker
```

If the setup is successful, you will see compilation output in your terminal as SiliconCompiler executes the demonstration flow.


---

Source: https://docs.siliconcompiler.com/en/latest/user_guide/remote_processing.html

## Guide to Remote Compilation

SiliconCompiler supports a remote compilation model, allowing you to leverage cloud resources for access to pre-configured tool installations, elastic compute, and potentially NDA-protected [PDKs](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-PDK) or [IPs](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-IP).

Remote execution runs against a server you or your organization operates.
SiliconCompiler does not host a server for you -- see
For Developers: Custom Servers for how to stand one up.


### Step 1: Configure Your Remote Server

All remote server settings are managed through a `credentials` file located in your home directory (`$HOME/.sc/` on Linux/macOS or `C:\Users\<USERNAME>\.sc\` on Windows).
The file holds JSON, but has no file extension.

While you can create this file manually, the recommended method is to use the interactive `sc-remote` command.

> **Warning**
> This file stores your password or API key **in plain text**, so treat it as a
> secret.
>
> - `sc-remote -configure` creates it readable only by you. If you write or
>   copy the file yourself, restrict it too -- on Linux and macOS,
>   `chmod 600 $HOME/.sc/credentials`. On Windows, remove the inherited
>   permissions and grant access to your account alone, through the file's
>   *Properties > Security* dialog or `icacls`.
> - **Never commit it to version control**, and do not paste its contents into
>   an issue, a pull request or a build log. If you need the credentials on a
>   build machine, use the secret store your CI provides rather than a file in
>   the repository -- see [Running builds in CI](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/ci.html#ci-tutorial).


#### Method 1: Interactive Setup (Recommended)

Open your terminal and run the following command:

```bash
sc-remote -configure
```

You will be prompted to enter your server's details. Follow the prompts based on the type of server you are connecting to:

- **Authenticated Server:** Provide the server address, your username, and your password/API key when prompted.

```bash
Remote server address: https://your-secure-server.com
Remote username: your-username
Remote password: your-key
Remote configuration saved to: /home/user/.sc/credentials
```

- **Unauthenticated Server:** Enter the server address and press Enter to leave the username and password fields blank.

```bash
Remote server address: https://your-server.example.com
Remote username:
Remote password:
Remote configuration saved to: /home/user/.sc/credentials
```


#### Method 2: Manual Configuration

If you prefer, you can create the `credentials` file manually in the appropriate directory.
The file must contain the following JSON structure:

```
{
  "address": "your-server-address",
  "username": "your-username",
  "password": "your-password-or-key"
}
```

For an unauthenticated server, simply leave the username and password fields as empty strings ("").


### Step 2: Verify the Connection

After configuration, run `sc-remote` without any arguments to test the connection to your server.

```bash
sc-remote
```

A successful connection will typically display a status message or an empty list of your remote jobs, confirming that your configuration and credentials are correct.


### Step 3: Run a Remote Job

To send a compilation job to the configured remote server, set the [`[option,remote]`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-project-option-remote) parameter in your build script:

```python
project.option.set_remote(True)
```

Build scripts that expose a command line through [`CommandLineSchema.create_cmdline()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.cmdlineschema.CommandLineSchema.create_cmdline) -- including the bundled demos -- also accept a `-remote` flag:

```bash
python -m siliconcompiler.demos.asic_demo -remote
```

The job will be packaged, sent to the remote server for processing, and the results will be streamed back to your local machine.
Results are downloaded for each [flowgraph node](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-flowgraph-node) as it completes, so a finished remote job leaves the same build directory contents behind as a local run.


### Troubleshooting

- **Local Changes Not Reflected:** Any modifications you make to local, built-in tool scripts, PDKs, or libraries will not be used in a remote job. The remote server uses its own pre-configured environment.
- **Network and Filesystem Issues:** Jobs run in isolated environments on the server. Code that relies on specific network or local filesystem calls may not work as expected.
- **Reporting Issues:** If you encounter problems with the remote workflow, please open an issue on the [SiliconCompiler repository's issue page](https://github.com/siliconcompiler/siliconcompiler/issues).


### For Developers: Custom Servers

If you are interested in deploying your own custom server, we provide a minimal example development server that can be used as a starting point: [sc-server](https://docs.siliconcompiler.com/en/latest/reference_manual/apps.html#app-sc-server) using the [remote API](https://docs.siliconcompiler.com/en/latest/reference_manual/server_api.html#server-api).

Running a server needs the `server` [extra](https://docs.siliconcompiler.com/en/latest/user_guide/installation.html#install-extras), which a default install does not carry -- submitting jobs to one, as the rest of this page does, needs nothing beyond SiliconCompiler itself:

```bash
pip install --upgrade "siliconcompiler[server]"
```

A ready-to-run deployment of it is checked in at `setup/server/`: a Docker Compose stack that brings up `sc-server` backed by a real Slurm cluster -- `slurmctld`, `slurmdbd` with a MariaDB accounting store, `slurmrestd`, and one or more `slurmd` compute nodes -- with the EDA tools already in the image, so full flows run and not just the scheduler path.

```bash
cd setup/server
docker compose up -d --build
```

The server is then reachable on `http://localhost:8080`, so the credentials file from Step 1 is:

```json
{"address": "localhost", "port": 8080}
```

Add compute nodes with `docker compose up -d --scale scrunner=4`; they register themselves, so no configuration changes. `setup/server/README.md` covers the rest.


---

Source: https://docs.siliconcompiler.com/en/latest/user_guide/data_model.html

## The Schema: A Centralized Data Model

At the core of every SiliconCompiler project is the Schema, a centralized data structure that holds all information about the design and the compilation process.
Think of it as the single source of truth or the digital blueprint for your hardware compilation project.

The Schema is designed to capture everything needed to produce a repeatable build. This includes, but is not limited to:

- **Design Definition**: Hardware sources, top-level module, and clock specifications.
- **Compilation Strategy**: The sequence of tools to run (the "flow"), and settings for each tool.
- **Target Technology**: Information about the target process design kit ([PDK](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-PDK)).
- **Metrics & Results**: Data gathered from the compilation, such as cell area, timing, and power.

This data is stored in Schema [parameters](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-parameter), which are accessed through a simple and consistent set of API methods.

The diagram above illustrates how different types of data are organized within the Schema and accessed via methods.

The following sections detail how to interact with the Schema.


### Working with the Schema

You interact with the Schema's parameters through a Project object.
The recommended way to do so is through **typed accessors** -- named methods, grouped by area, that set and read one parameter each.

The following example creates a Project and manipulates [`[option,fileset]`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-project-option-fileset), which selects which [filesets](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-fileset) of the design to compile.

```python
>>> from siliconcompiler import Project

# Create a project, which contains a schema.
>>> project = Project()

# The 'fileset' option is initially empty.
>>> print(project.option.get_fileset())
[]

# Append values with the matching add_ accessor.
>>> project.option.add_fileset('rtl')
>>> project.option.add_fileset('sdc')
>>> print(project.option.get_fileset())
['rtl', 'sdc']
```

Typed accessors are ordinary Python methods, so they are discoverable by autocompletion, checked by your editor, and documented with their own argument types.
Each one is listed in the [Python API](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#schema-api) reference.


#### Keypaths: the layer underneath

Underneath, every parameter lives at a **keypath** -- an ordered list of strings giving its unique location in the Schema, written in this documentation as [`[option,fileset]`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-project-option-fileset).
The generic [`BaseSchema.get()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.BaseSchema.get), [`BaseSchema.set()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.BaseSchema.set), and [`BaseSchema.add()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.BaseSchema.add) methods address parameters by keypath directly:

```python
# The same parameter the accessors above operated on.
>>> print(project.get('option', 'fileset'))
['rtl', 'sdc']
```

There is no second copy of the data and no conversion between the two forms: `project.option.get_fileset()` and `project.get('option', 'fileset')` read the same stored value.
The typed accessor is a thin, named wrapper around the keypath call.

> **Admonition**
> #### Which should you write?
>
> **Prefer the typed accessor whenever one exists.** It is the supported,
> self-documenting interface, and it is what the
> [tutorials](https://docs.siliconcompiler.com/en/latest/user_guide/index.html#tutorials) and the `examples/` directory use.
>
> **Reach for a keypath when there is no accessor to use.** Two cases account
> for most of them:
>
> - **Reading results.** [Metrics](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-metric) and [records](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-record)
>   are keyed by name and recorded per [flowgraph node](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-flowgraph-node), so they are read
>   with an explicit keypath plus a step and index:
>
>   ```
>   >>> project.get('metric', 'cellarea', step='synthesis', index='0')
>   67.032
>   ```
> - **Parameters an accessor has not been written for.** The Schema is larger
>   than the accessor surface; the keypath API reaches every parameter in the
>   [Schema Reference](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#schema), including those contributed by tools and
>   PDKs.
>
> Keypaths are not deprecated or discouraged in these cases -- they are the
> general mechanism the accessors are built on. What you should avoid is using
> a keypath for a parameter that already has an accessor, because the accessor
> carries the type and the name checking that a bare string list cannot.


### Files and Dataroots

A file parameter does not hold a path on this machine. It holds a path relative
to a [dataroot](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-dataroot) -- a named source of files -- together with that
dataroot's name, and the path is resolved against the dataroot only when the
file is needed:

```python
>>> from siliconcompiler import Design
>>> design = Design("picorv32")

>>> design.set_dataroot("picorv32", "git+https://github.com/YosysHQ/picorv32.git",
...                     tag="c0acaebf0d50afc6e4d15ea9973b60f5f4d03c42")
>>> with design.active_dataroot("picorv32"), design.active_fileset("rtl"):
...     design.add_file("picorv32.v")

>>> print(design.get("fileset", "rtl", "file", "verilog", field="dataroot"))
['picorv32']
```

This is what lets a [manifest](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-manifest) be rebuilt on another machine: it records
where each file comes from, not where it happened to sit. A dataroot can be a
local directory, an installed Python package, a git repository, an archive
download and more, chosen by the scheme its path starts with. Every scheme,
what it takes and how it authenticates is listed in [Data Sources](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/resolvers.html#builtin-resolvers).


### The Manifest: Saving and Loading the Schema

The entire state of the Schema can be saved to a file called a [manifest](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-manifest). This file, typically in JSON format, serves two critical purposes:

1. **Reference**: It provides a complete, human-readable record of every setting used in a compilation.
2. **Reproducibility**: It allows you to reload the exact configuration of a previous run, ensuring that builds are repeatable and shareable.

If you ran the [asic demo](https://docs.siliconcompiler.com/en/latest/user_guide/installation.html#asic-demo), you can find the project manifest here:

```
build/<design>/job0/<design>.pkg.json
```

Every [flowgraph node](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-flowgraph-node) also writes its own manifest, capturing the schema
as that node received and left it.
See [Directory structures](https://docs.siliconcompiler.com/en/latest/user_guide/directories.html#directory-structures) for the full build tree.

The [`BaseSchema.write_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.BaseSchema.write_manifest), [`BaseSchema.read_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.BaseSchema.read_manifest), and [`BaseSchema.from_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.BaseSchema.from_manifest) methods handle serializing the Schema to and from disk.


#### Writing and Reading a Manifest

```python
>>> from siliconcompiler import Project
>>> from siliconcompiler.flows.asicflow import ASICFlow

# Create and configure a project.
>>> project = Project()
>>> project.option.set_design('my_design')
>>> project.set_flow(ASICFlow())

# Write the entire schema configuration to a file.
>>> project.write_manifest('manifest.json')

# You can later reload this configuration into a new project.
>>> new_project = Project()
>>> new_project.read_manifest('manifest.json')
>>> print(new_project.option.get_design())
my_design

# Or you can directly load it
>>> new_project = Project.from_manifest('manifest.json')
>>> print(new_project.option.get_design())
my_design
```

The manifest.json file written by the code above would contain a record of all schema parameters, including the design name we configured:

```json
{
  "design": {
    "example": [
      "cli: -design hello_world",
      "api: option.set('design', 'hello_world')"
    ],
    "help": "Name of the top level library",
    "lock": false,
    "node": {
      "default": {
        "default": {
          "signature": null,
          "value": null
        }
      }
    },
    "notes": null,
    "pernode": "never",
    "require": false,
    "scope": "global",
    "shorthelp": "Option: Design library name",
    "switch": [
      "-design <str>"
    ],
    "type": "str"
  }
}
```


### Further Reading

For a comprehensive list of all parameters and their definitions, refer to the [Schema Reference](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#schema).
For more details on the API methods, see the [Python API](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#schema-api) documentation.


---

Source: https://docs.siliconcompiler.com/en/latest/user_guide/execution_model.html

## Compilation Process

The complete SiliconCompiler compilation is handled by a single call to the [`Project.run()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.project.Project.run) function.
Within that function call, a static data [flowgraph](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-flowgraph), consisting of [nodes](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-flowgraph-node) and [edges](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-edge) is traversed and "executed."

The static flowgraph approach was chosen for a number reasons:

- Performance scalability ("cloud-scale")
- High abstraction level (not locked into one language and/or shared memory model)
- Deterministic execution
- Ease of implementation (synchronization is hard)


### The Flowgraph


#### Nodes and Edges

A SiliconCompiler flowgraph consists of a set of connected nodes and edges, where:

- A [node](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-flowgraph-node) is an executable [tool](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-tool) performing some ("[task](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-task)"), and
- An [edge](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-edge) is the connection between those tasks, specifying execution order.


#### Tasks

SiliconCompiler breaks down a "task" into an atomic combination of a step and an index, where:

1. A [step](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-step) is defined as a discrete function performed within compilation flow such as [synthesis](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-synthesis), [linting](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-lint), [placement](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-placement), [routing](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-routing), etc, and
2. An [index](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-index) is defined as a variant of a step operating on identical data.

An example of this might be two parallel synthesis runs with different settings after [elaboration](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-elaboration).
The two synthesis "tasks" might be called `syn/0` and `syn/1`, where:

See using index for optimization for more information on why using indices to build your flowgraph are helpful.


#### Execution

Flowgraph execution is done through the [`Project.run()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.project.Project.run) function which checks the flowgraph for correctness and then executes all tasks in the flowgraph from start to finish.


### Flowgraph Examples

The flowgraph, used in the [asic demo](https://docs.siliconcompiler.com/en/latest/user_guide/installation.html#asic-demo), is a built-in compilation flow, called [asicflow](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/flows.html#schema-siliconcompiler-flows-asicflow-asicflow). This compilation flow is a pre-defined flowgraph customized for an ASIC build flow, and is called through the [`Project.add_dep()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.project.Project.add_dep) function, which calls a [pre-defined PDK module](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/pdks.html#builtin-pdks) that [uses the asicflow flowgraph](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/flows.html#schema-siliconcompiler-flows-asicflow-asicflow).

You can design your own project compilation build flows by easily creating custom flowgraphs through:

- [`Flowgraph.node()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Flowgraph.node) / [`Flowgraph.edge()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Flowgraph.edge) methods

The user is free to construct a flowgraph by defining any reasonable combination of steps and indices based on available tools and PDKs.


#### A Two-Node Flowgraph

The example below shows a snippet which creates a simple two-step (import + synthesis) compilation pipeline.

Snippet from examples/heartbeat_flowgraph.py

```
flow = Flowgraph('synonlyflow')
flow.node('elaborate', elaborate.Elaborate())               # use surelog for import
flow.node('syn', syn_asic.ASICSynthesis())               # use yosys for synthesis
flow.edge('elaborate', 'syn')               # perform syn after import

```

At this point, you can visually examine your flowgraph by using [`Flowgraph.write_flowgraph()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Flowgraph.write_flowgraph). This function is very useful in debugging graph definitions.

```
flow.write_flowgraph("flowgraph.svg", landscape=True)
```


#### Using Index for Optimization

The previous example did not include any mention of [index](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-index), so the index defaults to `0`.

While not essential to basic execution, the '[index](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-index)' is fundamental to searching and optimizing tool and design options.

One example use case for the index feature would be to run a design through synthesis with a range of settings and then selecting the optimal settings based on power, performance, and area.
The snippet below shows how a massively parallel optimization flow can be programmed using the SiliconCompiler Python API.

Snippet from examples/flowgraph_doe.py that sets up parallel synthesis runs for optimization

```
flow.node('synmin', minimum.MinimumTask())

# create node for each syn strategy (first node called import and last node called synmin)
# and connect all synth nodes to both the first node and last node
for index in range(7):
    # Create synthesis node
    flow.node('syn', syn_asic.ASICSynthesis(), index=str(index))

    # Connect synthesis node to elaborate
    flow.edge('elaborate', 'syn', head_index=str(index))

    # Connect synthesis node to minimization
    flow.edge('syn', 'synmin', tail_index=str(index))

    # set synthesis metrics that you want to optimize for
    for metric in ('cellarea', 'peakpower', 'standbypower'):
        flow.set('syn', str(index), 'weight', metric, 1.0)


```

> **Seealso**
> [Parallel Job Execution](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/parallel.html#parallel-execution) runs this pattern as a
> worked example and compares it against the two other ways of parallelizing a
> sweep, and [Multi-Job Flows](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/multi_job_flows.html#multi-job-sweep) covers reading the
> resulting metrics back out to drive a decision.


---

Source: https://docs.siliconcompiler.com/en/latest/user_guide/directories.html

## Directory Structures

SiliconCompiler writes to two places: a **build directory** for the artifacts of
a compilation, and a **home directory** (`~/.sc`) for data and settings shared
across every project on the machine.

This page describes both, so you know where to look for a report, what is safe to
delete, and what to check into version control.


### The build directory

Everything a run produces goes under the build directory, which defaults to
`build/` relative to where you ran the script.
Below that, output is nested by [design](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-design) name and then by
[job](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-job) name, so several designs and several jobs can share one build
directory without colliding:

```text
build/                              <- option,builddir  (default: "build")
└── heartbeat/                      <- design name
    └── job0/                       <- option,jobname   (default: "job0")
        ├── heartbeat.pkg.json      <- the job manifest
        ├── job.log                 <- log for the most recent run
        ├── job.20260731-085354.log <- rotated logs from previous runs
        ├── sc_collected_files/     <- inputs copied in for reproducibility
        ├── elaborate/              <- one directory per step
        │   └── 0/                  <- one directory per index
        └── synthesis/
            └── 0/
```

The two paths worth remembering are the **job manifest**,
`build/<design>/<jobname>/<design>.pkg.json`, which is the complete
[schema](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-schema) as it stood at the end of the run, and **job.log**, which is the
full log of that run.
On each new run the previous `job.log` is renamed with the timestamp of its
last write rather than overwritten, and the five most recent are kept.

`sc_collected_files/` holds copies of input files that were marked for
collection, so the job directory contains everything needed to rebuild even if
the original sources move. It only appears when a run actually collects files.
A file or directory that more than one value names is copied once, and its other
names are links to that copy. A link inside a collected directory stays a link,
pointed at its target's copy; a target from outside the collection is copied once,
where a link to it is first met, and a link whose target does not exist is left
out with a warning.


#### Inside a node directory

Each [flowgraph node](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-flowgraph-node) -- one ([step](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-step), [index](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-index)) pair -- runs in
its own directory and leaves its results there:

```text
synthesis/0/
├── inputs/               <- files received from the preceding node(s)
│   ├── heartbeat.v
│   └── heartbeat.pkg.json
├── outputs/              <- files passed on to the following node(s)
│   ├── heartbeat.vg
│   └── heartbeat.pkg.json
├── reports/              <- structured tool reports the metrics are read from
├── synthesis.log         <- the tool's own output
├── synthesis.errors      <- lines from that log matched as errors
├── synthesis.warnings    <- lines from that log matched as warnings
├── sc_synthesis_0.log    <- SiliconCompiler's log for this node
├── sc_manifest.tcl       <- the manifest, exported for the tool to read
└── replay.sh             <- re-runs this node on its own
```

Two details of this layout are worth knowing, because they explain most of what
you will do with a build directory:

**There are two logs, and they answer different questions.**
`<step>.log` is what the tool printed -- the place to look when the tool itself
failed. `sc_<step>_<index>.log` is what SiliconCompiler did around it: which
files it resolved, which parameters it passed, how long the task took.
`<step>.errors` and `<step>.warnings` are the lines of the tool log that
matched the task's error and warning patterns, which is also how the
`errors` and `warnings` [metrics](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-metric) are counted.

**Every node carries its own manifest.**
`inputs/<design>.pkg.json` is the schema as the node received it, and
`outputs/<design>.pkg.json` is the schema as the node left it, with the
[metrics](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-metric) and [records](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-record) it produced.
This is what makes a single node reproducible: `replay.sh` re-runs it from its
own inputs, and [sc-issue](https://docs.siliconcompiler.com/en/latest/reference_manual/apps.html#app-sc-issue) packages it up as a standalone
test case:

```
sc-issue -cfg build/<design>/<jobname>/<step>/<index>/inputs/<design>.pkg.json
```

`replay.sh --help` lists its options. Some tools add modes of their own, such
as `--gui`, `--web` or `--shell`, which rerun the step in the tool's GUI,
web viewer or interactive prompt and leave it open when the step ends.

> **Note**
> The exported tool manifest is named `sc_manifest.<suffix>`, where the
> suffix depends on what the tool reads -- `.tcl` for OpenROAD and Yosys,
> `.json` for Python-driven tools such as KLayout. Not every task exports
> one.


#### Controlling the build directory

| Parameter | Default | Effect |
| --- | --- | --- |
| [`[option,builddir]`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-project-option-builddir) | `build` | Root of the build tree. Relative paths resolve against the directory the script was run from. Set it with `project.option.set_builddir(path)`. |
| [`[option,jobname]`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-project-option-jobname) | `job0` | Names the job directory. Use it to keep runs side by side for comparison. |
| [`[option,clean]`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-project-option-clean) | `False` | Runs from scratch. By default a re-run *resumes*: nodes that already completed are reused rather than re-executed. Setting `clean` discards that state and empties the job directory first, unless [`[option,from]`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-project-option-from) is set or `jobincr` moves the run elsewhere. |
| [`[option,jobincr]`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-project-option-jobincr) | `False` | Only takes effect together with `clean`. Instead of emptying the existing job directory, the run moves to the next unused job name (`job0` becomes `job1`), so the earlier job survives for comparison. On its own, `jobincr` does nothing. |

The build directory is entirely derived output. It is safe to delete, and it
should not be checked into version control.


### The SiliconCompiler home directory

`~/.sc` holds everything that is shared between projects rather than produced
by one:

```text
~/.sc/
├── cache/           <- everything kept between runs (see below)
├── settings.json    <- your persistent defaults
├── credentials      <- remote server address and login
└── tool_build/      <- scratch space for sc-install
```

On Windows the same directory is `C:\Users\<username>\.sc\`.
[sc-config paths](https://docs.siliconcompiler.com/en/latest/reference_manual/apps.html#app-sc-config-paths) prints where each of these is on
your machine, and which exist.


#### The cache

`~/.sc/cache` holds everything SiliconCompiler keeps between runs, in one
subdirectory per kind:

```text
~/.sc/cache/
├── dataroot/        <- downloaded data sources (PDKs, libraries, designs)
└── tools/           <- caches the tools keep for themselves
```

Cached data goes in those subdirectories, never in the directory itself, which
holds nothing but the sweep's own `.sc_cleanup` timestamp.
[`[option,cachedir]`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-project-option-cachedir) moves both areas together -- to shared storage on a
cluster, for instance, so that every user and every compute node resolves
packages from one place:

```python
project.option.set_cachedir("/shared/sc_cache")
```

Both areas are safe to delete; anything missing is downloaded or rebuilt on the
next run. Deleting either while a run is in progress is not.


##### Data sources

Any [dataroot](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-dataroot) that points at a git repository or a downloadable archive is
fetched once into `dataroot/` and reused by every project afterwards. Entries
are named `<name>-<reference>-<hash>`, where the reference is the requested
version and the hash distinguishes sources that resolve differently:

```text
~/.sc/cache/dataroot/
├── lambdapdk-v0.2.17-49afb2b188ee16ae/
├── lambdapdk-v0.2.17-49afb2b188ee16ae.lock
└── ...
```

The `.lock` files coordinate concurrent runs so that two processes do not
download the same package at once; they are not data and can be ignored. Their
modification time doubles as the entry's last-use time, stamped by every resolve.

Because nothing in a normal run removes the version an older project needed, this
area only grows. Every run therefore starts with a sweep of it: entries that
have not been resolved in 90 days are deleted, as is any `.lock` or
`.sc_lock` file whose entry is already gone, whatever its age -- except one
taken in the last hour, which is kept in case a resolve is holding it and has yet
to create its directory. The sweep runs at most once a week per cache directory,
records when it last ran in `.sc_cleanup`, and never interrupts a run. Both the age and the
interval are configurable, and the sweep can be switched off entirely -- see
[User Settings](https://docs.siliconcompiler.com/en/latest/development_guide/options.html#user-settings). To collect the cache on demand instead,
with a threshold of your own:

```bash
sc-config cache clean -days 30 -dryrun
```

Upgrading from a release before the cache was split, the old entries sit loose in
`~/.sc/cache` rather than in `dataroot/`. Nothing moves them: they are swept
on the same 90-day clock as everything else, and anything still wanted is
downloaded again into the new layout the next time it resolves. A cache shared
with a machine still on an older release therefore loses the entries that release
is using, and that release downloads them again -- the same one-time cost, paid
on the other machine.


##### Tool caches

`tools/<tool>/` is where a tool keeps whatever it carries from one run to the
next. Unlike a node's working directory, which is emptied at the start of every
run, this survives, and it is shared across every design built with that tool.

A tool that keeps a cache reads the directory from an environment variable, and
defaults it to somewhere under `~/.cache`. That is outside
[`[option,cachedir]`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-project-option-cachedir), so nothing SiliconCompiler manages sees it, and it is
absent from a task container, so a containerised run starts cold every time. The
drivers of such tools point that variable at `tools/<tool>` instead. Verilator
is the clearest case -- its generated makefile invokes ccache on every C++ build,
so `CCACHE_DIR` lands here -- and each tool gets its own subdirectory rather
than sharing one, because two tools rarely compile the same thing with the same
flags. Set the variable yourself, in the environment or on the task, and your
setting is left alone.

Sharing across designs is what a compiler cache wants, but not every cache can:
a cache whose contents are only valid for one task configuration has to be kept
apart from the others. A driver in that position names a subdirectory after the
task's digest instead of sharing `tools/<tool>/`
directly.

Nothing collects this area. A tool that keeps a cache is expected to cap it
itself -- ccache does, at 5GB by default -- so if you want it gone, delete it.


##### Naming things after a task

[`Task.get_digest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.get_digest) returns a hex digest of everything that configures a
task -- its command line, threads, scripts, environment, executable and version
requirement, and every keypath its driver declared with
[`Task.add_required_key()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.add_required_key). Two tasks configured the same way get the same
digest; two that differ anywhere, including in a single boolean, do not:

```python
class MyTask(Task):
    @property
    def cachedir(self):
        return os.path.join(super().cachedir, self.get_digest(length=16))
```

The digest is computed from the configuration as written. It reads no files,
resolves no [dataroot](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-dataroot), runs no executable and does not depend on
[`[option,hash]`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-project-option-hash), so it costs nothing and comes out the same on every
machine -- a cache directory named after it can be shared across a cluster. What
that leaves out is worth knowing before you rely on it: the contents of the input
files, and the version of the tool actually installed. A driver that needs either
composes it -- [`Task.get_exe_version()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.get_exe_version) for the second -- or requires the
keys that stand in for them, such as a dataroot's `tag`. The *directory* the
executable was found in is left out on purpose: it differs per machine, and a
digest that moved with it would partition the shared cache rather than share it.


#### Settings and credentials

`settings.json` holds defaults applied to every new [`Project`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.project.Project) -- your
preferred scheduler, log verbosity, and so on -- written by
[sc-config settings](https://docs.siliconcompiler.com/en/latest/reference_manual/apps.html#app-sc-config-settings) or
[`OptionSchema.write_defaults()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.option.OptionSchema.write_defaults). An administrator can also supply
machine-wide defaults from outside your home directory, at
`/etc/siliconcompiler/settings.json` on Linux and macOS or
`%PROGRAMDATA%\siliconcompiler\settings.json` on Windows.
[User Settings](https://docs.siliconcompiler.com/en/latest/development_guide/options.html#user-settings) covers the file format and the precedence
rules between the two.

`credentials` holds the address and login for a remote server, written by
`sc-remote -configure`. Note that it has no file extension, although its
contents are JSON. Point [`[option,credentials]`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-project-option-credentials) at a different file to
use more than one server. See [Remote Processing](https://docs.siliconcompiler.com/en/latest/user_guide/remote_processing.html#remote-processing).

`tool_build/` is where `sc-install` builds tools from source before
installing them, by default into `~/.local`. It is scratch space and can be
deleted.

> **Note**
> Except for `tool_build/`, nothing in `~/.sc` is required: SiliconCompiler
> creates what it needs on demand. Deleting the whole directory costs you your
> saved defaults and credentials, and means every package is downloaded again.


---

Source: https://docs.siliconcompiler.com/en/latest/user_guide/checklist.html

## Checklists: The Audit Model

A build that finishes is not the same as a build that is *signed off*. Somebody
still has to answer: are the design rules clean? Did timing close? Is there a
written specification? Were the warnings looked at, or just tolerated?

A [`Checklist`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Checklist) is where those questions live, and where their answers get
recorded. It turns [signoff](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-signoff) from a conversation into an object in the
[schema](https://docs.siliconcompiler.com/en/latest/user_guide/data_model.html#data-model) -- one that travels with the
[manifest](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-manifest), so a build can be audited long after the person who ran it has
moved on.


### What a checklist is

A [checklist](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-checklist) is a named collection of **criteria**. Each criterion is one
question, and carries the fields needed to answer it and to prove the answer
later:

| Field | Holds |
| --- | --- |
| `description` | The question, in English -- *"Is block DRC clean?"* |
| `criteria` | The machine-checkable form -- `drcs==0`, `setupslack>=0`. Compared against recorded [metrics](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-metric). |
| `task` | Which `(job, step, index)` the metrics come from -- a triple, because a checklist can be settled across several jobs |
| `report` | The report files that evidence the answer |
| `requirement` | Why the item exists -- the spec or standard it comes from |
| `rationale` | Why it matters, for the reader of the audit |
| `waiver` | A signed-off exception for a metric that does not meet its criterion |
| `ok` | The human sign-off, for items no metric can settle |

The split that matters is between the last two rows and the rest. Some questions
a tool can answer -- a [metric](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-metric) either meets a threshold or it does not. Others
("is there a written specification?") only a person can. A checklist holds both
kinds in one place rather than pretending everything is automatable.


### A shipped example

[OHTapeoutChecklist](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/checklists.html#schema-siliconcompiler-checklists-oh-tapeout-ohtapeoutchecklist)
is a subset of the [OH! library tapeout checklist](https://github.com/aolofsson/oh/blob/main/docs/tapeout_checklist.md), and
shows both kinds side by side:

```python
# Automated: settled by a metric
self.set('drc_clean', 'description', 'Is block DRC clean?')
self.set('drc_clean', 'criteria', 'drcs==0')

self.set('setup_time', 'description', 'Setup time met?')
self.set('setup_time', 'criteria', 'setupslack>=0')

# Manual: settled by a person
self.set('spec', 'description', 'Is there a written specification?')
```

Note `drcs` rather than `drvs`: the two are different metrics and the
distinction is deliberate. See [the FAQ](https://docs.siliconcompiler.com/en/latest/user_guide/faq.html#faq) on what each one counts.


### Using one

A checklist is a dependency, like a flow or a library. The shipped ones declare
*criteria* but not which nodes produce them, so binding each automated item to a
`(job, step, index)` is part of using one:

```python
from siliconcompiler.checklists.oh_tapeout import OHTapeoutChecklist

checklist = OHTapeoutChecklist()
project.add_dep(checklist)

project.run()

# Without this the item has no task to read metrics from, and check()
# passes it vacuously.
checklist.get_criteria("setup_time").add_task(("job0", "timing", "0"))

if not checklist.check():
    raise SystemExit("signoff failed")
```

> **Warning**
> An item with no `task` is **not** checked -- `check()` has nothing to read
> and moves on. A checklist attached but never bound therefore reports success
> while verifying nothing, which is the worst possible failure mode for a
> signoff gate. Bind every automated item, and confirm the result changes when
> you break something.

[`Checklist.check()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Checklist.check) walks each item, reads the metrics from the job
history for the tasks the item names, and compares them against the criteria. It
also asserts that the reports exist -- an item that passes on the numbers but has
no evidence behind it is not a pass. Three switches adjust how strict it is:

```python
checklist.check(items=["drc_clean", "setup_time"])  # only these
checklist.check(check_ok=True)                      # also require human sign-off
checklist.check(require_reports=False)              # numbers only, no evidence
```

Because it reads the **job history**, a checklist can span jobs: an item can be
settled by a signoff run while another is settled by the implementation run that
preceded it. See [Multi-Job Flows](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/multi_job_flows.html#multi-job-flows) for how those are
chained.


### Writing your own

Subclass [`Checklist`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Checklist) and declare the items:

```python
from siliconcompiler import Checklist

class MyTapeout(Checklist):
    def __init__(self):
        super().__init__("my_tapeout")

        item = self.make_criteria("no_setup_violations")
        item.set_description("Setup timing closed at the slow corner?")
        item.add_criteria("setupslack>=0")
        item.add_task(("signoff", "timing", "0"))   # (job, step, index)
```

The criteria strings are metric comparisons, so anything recorded as a
[metric](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-metric) can be gated on -- including metrics your own tool driver adds.

> **Seealso**
> [Working with Metrics](https://docs.siliconcompiler.com/en/latest/development_guide/metrics.html#dev-metrics) for what is recorded and how to read
> it back, and [Checklists](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/checklists.html#builtin-checklists) for the full reference of
> the shipped ones.


---

Source: https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/lint.html

## Lint Your RTL

Linting checks your [RTL](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-RTL) for syntax and style problems without compiling
it, and it is the quickest way to get a real result out of SiliconCompiler. No
[PDK](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-PDK), no cloud account, and -- unusually -- **no EDA tools to install**.
The default linter, [slang](https://sv-lang.com), ships as a Python package
that comes with SiliconCompiler itself, so this works immediately after
`pip install`.

A run takes about ten milliseconds.


### The script

Save this next to a Verilog file called `blinky.v`:

```python
from siliconcompiler import Design, Lint
from siliconcompiler.flows.lintflow import LintFlow

design = Design("blinky")
design.set_dataroot("root", __file__)
with design.active_dataroot("root"), design.active_fileset("rtl"):
    design.set_topmodule("blinky")
    design.add_file("blinky.v")

project = Lint(design)
project.add_fileset("rtl")
project.set_flow(LintFlow())

project.run()
project.summary()
```

The shape is the same as every other SiliconCompiler script -- describe the
design, pick a [flow](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-flow), run -- with two differences: the project type is
[`Lint`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Lint) rather than [`ASIC`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.ASIC), and no [target](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/targets.html#builtin-targets)
is loaded, because there is no technology to target.


### What it tells you

On clean sources the run says so and stops:

```text
| INFO     | job0 | lint | 0 | Number of errors: 0
| INFO     | job0 | lint | 0 | Number of warnings: 0
| INFO     | job0 | lint | 0 | Finished task in 0.01s
```

Give it something broken -- a mistyped signal name and an out-of-range bit
select -- and you get the diagnosis with the source line:

```text
| ERROR | blinky.v:13:24: error: use of undeclared identifier 'count'
| ERROR |             counter <= count + 1'b1;
| ERROR |                        ^~~~~
| ERROR | blinky.v:14:32: warning: cannot refer to element 8 of 'reg[7:0]' [-Windex-oob]
| ERROR |             led     <= counter[N];
| ERROR |                                ^
| INFO  | Number of errors: 2
```

Both counts are recorded as [metrics](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-metric) -- [`[metric,errors]`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-project-metric-errors)
and [`[metric,warnings]`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-project-metric-warnings) -- so they appear in
[`Project.summary()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.project.Project.summary) and can be read back afterwards. Read them from the
**history object** [`Project.run()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.project.Project.run) returns: job-scoped metrics are reset on
the live project when the job finishes, so the completed values live there.

```python
history = project.run()
history.get("metric", "errors", step="lint", index="0")
```

That is what makes linting worth scripting rather than running by hand: the
result is a number you can gate on.


### Choosing the linter

[LintFlow](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/flows.html#schema-siliconcompiler-flows-lintflow-lintflow) takes a `tool` argument:

```python
project.set_flow(LintFlow())                      # slang (default)
project.set_flow(LintFlow(tool="verilator"))      # verilator
project.set_flow(LintFlow(tool="all"))            # both, as separate nodes
```

`slang` needs nothing installed. `verilator` is an
[external tool](https://docs.siliconcompiler.com/en/latest/user_guide/installation.html#external-tools) and has to be available on your machine,
but it catches a different class of problem, which is what `tool="all"` is
for -- it builds one node per linter and runs them side by side.

The lint script above passes `-Weverything` to slang, so you are seeing
everything it has to say.


### In a real build script

`examples/heartbeat` exposes linting as one target among many, so the same
design can be linted, synthesized, simulated or hardened without editing
anything:

```python
def lint(N: Optional[str] = None):
    """Runs the linting flow on the Heartbeat design.

    Linting checks the Verilog source code for syntax errors and style
    issues without performing a full synthesis.

    Args:
        N (str, optional): The value for the Verilog parameter 'N'.
            Defaults to None, which uses the value set in the design schema.
    """
    # Create a project instance tailored for linting.
    project = Lint()

    # Instantiate the design configuration.
    hb = HeartbeatDesign()

    # Associate the design with the project.
    project.set_design(hb)
    # Add the necessary fileset for this flow.
    project.add_fileset("rtl")

    # Optionally override the 'N' parameter from the command line.
    if N is not None:
        hb.set_param("N", N, fileset="rtl")

    # Configure the project to use the linting flow.
    project.set_flow(LintFlow())

    # Execute the flow.
    project.run()
    # Display a summary of the results.
    project.summary()

```

```bash
cd examples/heartbeat
smake lint            # or: smake lint --N 16
```

See [Run a build script's targets without editing it](https://docs.siliconcompiler.com/en/latest/user_guide/howto.html#howto-smake) for how
that works, and [Example designs](https://docs.siliconcompiler.com/en/latest/user_guide/examples.html#examples) for the rest of what this one
can do.


### Next

- [Simulate your design](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/simulate.html#simulate-tutorial) -- the next cheapest check,
  and still no PDK.
- [Quickstart](https://docs.siliconcompiler.com/en/latest/user_guide/quickstart.html#quickstart-guide) -- the same design taken all the way to
  a layout.
- [How do I...?](https://docs.siliconcompiler.com/en/latest/user_guide/howto.html#howto) -- recipes for the things you will want next.


---

Source: https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/simulate.html

## Simulate and Verify

Between [linting](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/lint.html#lint-tutorial) and building a layout sits everything
that checks the design actually *works*. SiliconCompiler drives three kinds of
check, none of which needs a [PDK](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-PDK):

| Check | Project type and flow | Answers |
| --- | --- | --- |
| **Simulation** | [`Sim`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Sim) + [DVFlow](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/flows.html#schema-siliconcompiler-flows-dvflow-dvflow) | "Does it do the right thing on the stimulus I wrote?" |
| **cocotb** | [`Sim`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Sim) + [dvflow_cocotb](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/targets.html#target-siliconcompiler-targets-dvflow-cocotb) | The same, with the testbench written in Python |
| **Formal** | [`Sim`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Sim) + [PropertyCheckFlow](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/flows.html#schema-siliconcompiler-flows-formalflow-propertycheckflow) | "Is this property true for *every* input, not just the ones I tried?" |

All three are [`Sim`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Sim) projects: the project type says what kind of question
you are asking, and the flow says which tool answers it.


### Simulation

A [`Sim`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Sim) project needs one thing an [`ASIC`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.ASIC) project does not: a
[testbench](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-testbench). It goes in its own [fileset](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-fileset) alongside the [RTL](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-RTL), so the same
design object serves both.

```python
def sim(N: Optional[str] = None, tool: str = "verilator", tb_type: str = "v"):
    """Runs a simulation of the Heartbeat design.

    After the simulation completes, it attempts to open the generated
    waveform file (VCD) for viewing.

    Args:
        N (str, optional): The value for the Verilog parameter 'N'.
            Defaults to None, which uses the value set in the design schema.
        tool (str, optional): The simulation tool to use ('verilator' or
            'icarus'). Defaults to "verilator".
        tb_type (str, optional): The file extension of the testbench ('cc' or
            'v'). Defaults to "v".
    """
    # Create a project instance tailored for simulation.
    project = Sim()

    # Instantiate and configure the design.
    hb = HeartbeatDesign()
    project.set_design(hb)

    # Add the tool-specific testbench and the RTL design files.
    project.add_fileset(f"testbench.{tool}.{tb_type}")
    project.add_fileset("rtl")
    # Set the appropriate design verification flow.
    project.set_flow(DVFlow(tool=tool))

    # Optionally override the 'N' parameter for the testbench.
    if N is not None:
        hb.set_param("N", N, fileset=f"testbench.{tool}.{tb_type}")

    if tool == "verilator":
        # Add trace to verilator
        CompileTask.find_task(project).set_verilator_trace(True)
        if tb_type == "v":
            CompileTask.find_task(project).set_verilator_main(True)

    # Run the simulation.
    project.run()
    project.summary()

    vcd = None
    if tool == "icarus" or (tool == "verilator" and tb_type != "cc"):
        # Find the VCD (Value Change Dump) waveform file from the results.
        vcd = project.find_result(step='simulate', index='0',
                                  directory="reports",
                                  filename="heartbeat_tb.vcd")
    else:
        # Find the VCD (Value Change Dump) waveform file from the results.
        vcd = project.find_result(step='simulate', index='0',
                                  directory="reports",
                                  filename="heartbeat.vcd")
    # If a VCD file is found, open it with the default waveform viewer.
    if vcd:
        project.show(vcd)

```

Two things are worth pulling out:

- **The testbench is a fileset, not a special case.** `testbench.verilator.v`
  and `testbench.icarus.v` are ordinary [filesets](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-fileset), so switching simulators is
  switching which one you add.
- **The tool is chosen by the flow.** [DVFlow](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/flows.html#schema-siliconcompiler-flows-dvflow-dvflow) takes `tool=` --
  `icarus`, `verilator`, `xyce` and `xdm-xyce` are supported -- and
  `np=` to run several independent pipelines at once for constrained-random
  stimulus.

Both simulators are [external tools](https://docs.siliconcompiler.com/en/latest/user_guide/installation.html#external-tools). Icarus is the
smaller install; Verilator is faster on large designs and is what the
`.cc` testbench variants target.

Run it from the example:

```bash
cd examples/heartbeat
smake sim                        # verilator, Verilog testbench
smake sim --tool icarus
```

The waveform lands in the node's `reports` directory as a [VCD](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-VCD), and the target
above opens it for you.

> **Seealso**
> `smake sim_postpnr` in the same script simulates the **gate-level netlist**
> after place-and-route, against the Skywater130 cell models -- the check that
> the implemented design still matches the RTL. `smake power` then chains
> three jobs to turn that simulation's VCD into a vector-driven power number.


#### Looking at the waveform

A simulation that only prints pass or fail tells you little when it fails. The
viewer is [surfer](https://surfer-project.org), and it reads the VCD the
simulation left behind.

The one thing to know is that the trace is a **report**, not an output.
[`Project.show()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.project.Project.show) with no argument looks for a *result* -- a layout in a
node's `outputs` directory -- so it will not find a waveform on its own. Locate
the file and hand it over:

Finding the trace, from examples/heartbeat/make.py

```python
        vcd = project.find_result(step='simulate', index='0',
                                  directory="reports",
                                  filename="heartbeat_tb.vcd")

```

```python
project.show(vcd)          # opens the waveform in surfer
```

The same file can be opened later from the command line by path, without
re-simulating:

```bash
sc-show build/heartbeat/job0/simulate/0/reports/heartbeat_tb.vcd
```

Install the viewer with the rest of the tools:

```bash
sc-install surfer
```

> **Note**
> VCD is a verbose format, and a long gate-level simulation can produce a file
> large enough to be slow to load. `vcd2fst` converts one to the compact FST
> format, which surfer reads just as well:
>
> ```bash
> sc-install vcd2fst
> ```


### Python testbenches with cocotb

[cocotb](https://www.cocotb.org) writes the testbench in Python instead of
Verilog, driving the simulator from a coroutine. SiliconCompiler wires it up
through the [dvflow_cocotb](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/targets.html#target-siliconcompiler-targets-dvflow-cocotb) target rather than a hand-built flow:

```python
def sim_icarus(seed: int = None, trace: bool = True):
    """Runs a cocotb simulation of the Adder design.

    Args:
        seed (int, optional): Random seed for test reproducibility.
            If not set, cocotb will generate a random seed.
        trace (bool, optional): Enable waveform tracing. Defaults to True.
            When enabled, generates a VCD file for waveform viewing.
    """
    # Create a project instance
    project = Sim(AdderTb())

    # Add the cocotb testbench files
    project.add_fileset("testbench.cocotb")

    # Call cocotb target function to setup the project for a cocotb run
    dvflow_cocotb(
        project=project,
        trace=trace,
        timescale=("1ns", "1ps"),
        seed=seed
    )

    # Select the icarus + cocotb flow
    project.set_flow("icaruscocotbdvflow")

    # Run the simulation
    project.run()
    project.summary()

    # Find and display the results file
    results = project.find_result(
        step='simulate',
        index='0',
        directory="outputs",
        filename="results.xml"
    )
    if results:
        print(f"\nCocotb results file: {results}")

    # Find and display the waveform file
    vcd = project.find_result(
        step='simulate',
        index='0',
        directory="reports",
        filename="adder.vcd"
    )
    if vcd:
        print(f"Waveform file: {vcd}")

```

The helper registers both the Icarus and Verilator cocotb flows and selects
Icarus; `project.set_flow("verilatorcocotbdvflow")` switches to the other
without rebuilding anything.

`cocotb` itself installs from PyPI (`pip install siliconcompiler[cocotb]`),
so the only external dependency is the simulator underneath it.
[examples/adder_cocotb](https://docs.siliconcompiler.com/en/latest/user_guide/examples.html#example-adder-cocotb) is the complete design.


### Formal property checking

Simulation shows a property holds for the stimulus you wrote. Formal checking
asks whether it holds at all. [PropertyCheckFlow](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/flows.html#schema-siliconcompiler-flows-formalflow-propertycheckflow) drives
[SymbiYosys](https://github.com/YosysHQ/sby) over SVA assertions in three
modes:

| Mode | Asks |
| --- | --- |
| `BMC` | Is the assertion true for the first *N* cycles? (bounded model check) |
| `PROVE` | Is it true in every reachable state? (unbounded, by k-induction) |
| `COVER` | Is this condition reachable *at all*? |

Each mode becomes its own node, so asking several questions at once runs them in
parallel:

```python
from siliconcompiler.flows.formalflow import PropertyCheckFlow, PropertyCheckMode

project.set_flow(PropertyCheckFlow(
    modes=PropertyCheckMode.BMC | PropertyCheckMode.PROVE | PropertyCheckMode.COVER))
```

[examples/sva_sby](https://docs.siliconcompiler.com/en/latest/user_guide/examples.html#example-sva-sby) has one script per mode, and a FIFO
carrying named assertions that runs all three. The first three mirror the
official SymbiYosys quickstart, so they are directly comparable with its
`.sby` files.

Requires `sby` and `yosys`; no PDK.


### Next

- [Quickstart](https://docs.siliconcompiler.com/en/latest/user_guide/quickstart.html#quickstart-guide) -- take a checked design to a layout.
- [Example designs](https://docs.siliconcompiler.com/en/latest/user_guide/examples.html#examples) -- the complete scripts behind each section
  above.
- [Working with Metrics](https://docs.siliconcompiler.com/en/latest/development_guide/metrics.html#dev-metrics) -- reading results back out of a run.


---

Source: https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/own_design.html

## Bringing Your Own Design

The demo builds someone else's design. This page is the next question: you have
[RTL](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-RTL) of your own, and you want to compile it.

There are four things to tell SiliconCompiler, and nothing else is required to
start.


### 1. Describe the design

A [`Design`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Design) is a top module plus the [filesets](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-fileset) holding
its sources. Sources go in `rtl`; timing constraints go in `sdc`, separately,
because they change with the technology and the RTL does not:

```python
from siliconcompiler import Design

design = Design("mydesign")
design.set_dataroot("root", __file__)

with design.active_dataroot("root"), design.active_fileset("rtl"):
    design.set_topmodule("mydesign")
    design.add_file("mydesign.v")
    design.add_file("submodule.v")

with design.active_dataroot("root"), design.active_fileset("sdc"):
    design.add_file("mydesign.sdc")
```

[`Design.set_dataroot()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Design.set_dataroot) with `__file__` makes every path relative to the
script, so the design still builds when someone clones it somewhere else. That
is worth doing from the start -- see [Data Sources](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/resolvers.html#builtin-resolvers) for
the other kinds, including sources fetched from a git repository at a pinned
commit.

Parameters and defines belong to the fileset too:

```python
design.set_param("WIDTH", "32", fileset="rtl")
design.add_define("SYNTHESIS", fileset="rtl")
```


### 2. Check it before you build

```python
assert design.check_filepaths()
```

Ten seconds here saves a failed run later; unresolvable paths are the most
common first failure. Then lint it, which needs no tools at all and catches the
next tier of problem:

```python
from siliconcompiler import Lint
from siliconcompiler.flows.lintflow import LintFlow

project = Lint(design)
project.add_fileset("rtl")
project.set_flow(LintFlow())
project.run()
```

See [Lint your RTL](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/lint.html#lint-tutorial). Do not skip this: [synthesis](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-synthesis)
error messages are much worse than [lint](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-lint) error messages.


### 3. Pick a technology

A [target](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-target) bundles the [PDK](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-PDK), the [standard cell](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-standard-cell) libraries and the
tool setup. Start with an open one -- you can change it later without touching
the design:

```python
from siliconcompiler import ASIC
from siliconcompiler.targets import freepdk45_demo

project = ASIC(design)
project.add_fileset("rtl")
project.add_fileset("sdc")

freepdk45_demo(project)
```

| Target | Use when |
| --- | --- |
| [freepdk45_demo](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/targets.html#target-siliconcompiler-targets-freepdk45-demo) | You want fast results and are not taping out. A fictional 45nm process, so timing numbers are indicative, not real. |
| [skywater130_demo](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/targets.html#target-siliconcompiler-targets-skywater130-demo) | You want an open PDK that real silicon has been made in. Slower. |
| [asap7_demo](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/targets.html#target-siliconcompiler-targets-asap7-demo) | You want to see behaviour at an advanced node. Predictive, not manufacturable. |
| [gf180_demo](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/targets.html#target-siliconcompiler-targets-gf180-demo), [ihp130_demo](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/targets.html#target-siliconcompiler-targets-ihp130-demo) | Other open PDKs with real foundry paths. |

Constraints your design will probably need:

```python
project.constraint.area.set_dieoutline(500, 500, coremargin=10)
```

Without a die area the floorplanner picks one from a utilisation target, which
is fine until you have macros -- see
[Instantiating a hardened module](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/hardened.html#hardened-modules).
[Floorplanning](https://docs.siliconcompiler.com/en/latest/user_guide/howto.html#howto-floorplanning) covers the rest of what goes on a
project: macro halos and placements, which side a pin comes out on, and pad
rings.


### 4. Run it

```python
project.run()
project.summary()
```

The summary is the first thing to read, and [When a run fails](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/debug.html#debug-tutorial) is the second.


### Then what?

The interesting part starts once it builds. Common next steps, in the order
people usually need them:

| You want to | Go to |
| --- | --- |
| Use RTL from another repository | [Building Your Own SoC](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/picorv32_ram.html#picorv32-example) -- dataroots pinned to a commit |
| Compose your design from another design | [Building Your Own SoC](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/picorv32_ram.html#picorv32-example) -- `add_depfileset` |
| Use an SRAM or another hard macro | [Instantiating a hardened module](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/hardened.html#hardened-modules) |
| Try several settings and keep the best | [Parallel Job Execution](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/parallel.html#parallel-execution) -- index parallelism |
| Sweep a parameter and compare | [Multi-Job Flows](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/multi_job_flows.html#multi-job-sweep) |
| Compile from VHDL, Bluespec, Chisel or Migen | [Hardware design frontends](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/hw_frontends.html#hw-frontends) |
| Target an FPGA instead | [Build for an FPGA](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/fpga.html#fpga-tutorial) |
| Not install any EDA tools | [Docker](https://docs.siliconcompiler.com/en/latest/user_guide/docker.html#docker), or a [remote run](https://docs.siliconcompiler.com/en/latest/user_guide/remote_processing.html#remote-processing) |

> **Seealso**
> [Example designs](https://docs.siliconcompiler.com/en/latest/user_guide/examples.html#examples) -- a working script for nearly every row
> above, and [How do I...?](https://docs.siliconcompiler.com/en/latest/user_guide/howto.html#howto) for the one-off questions that come up
> along the way.


---

Source: https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/debug.html

## When a Run Fails

A failed build gives you a one-line error and a directory full of files. This
page is about turning that into a diagnosis.

The order below is deliberate: it is roughly the order in which failures happen,
and each stage is cheaper to check than the one after it.


### First: which stage failed?

Read the last few lines of the terminal. SiliconCompiler distinguishes three
kinds of failure, and they need different responses:

| What you see | What it means |
| --- | --- |
| `Cannot resolve path ...` | **Before anything ran.** A file in the schema does not exist. Nothing was compiled; no tool was started. |
| `Run failed: Tools requirements not met` | **Before the tool ran.** The node was set up but a requirement was missing -- usually a file, sometimes a tool. |
| `Run failed` after node output | **The tool ran and failed.** Its own log is where the answer is. |

The first two are configuration problems in your script. The third is a design
or tool problem, and is the only one where you need the build directory.


### Missing files

By far the most common failure, and the one most often reported as a bug:

```text
| ERROR | Cannot resolve path missing.v in required file keypath
|         [library,nope,fileset,rtl,file,verilog] for lint/0.
| ERROR | Run failed: Tools requirements not met
```

Read the keypath backwards: a **verilog** file, in the **rtl**
[fileset](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-fileset), of the library **nope**, was needed by node **lint/0** and could
not be found. The path is reported exactly as you wrote it, so if it looks
relative, it was resolved against a [dataroot](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-dataroot) that does not contain it.

Check the whole design before running, which is much faster than a failed run:

```python
assert design.check_filepaths()
```

Most examples expose this as a target -- `smake check`. See
[Add files to a fileset](https://docs.siliconcompiler.com/en/latest/user_guide/howto.html#howto) for how paths and
[dataroots](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-dataroot) relate.


### When the tool itself fails

Now the build directory matters. Every node has its own, and two logs that
answer different questions:

```text
build/<design>/<jobname>/<step>/<index>/
├── inputs/                 <- what the node received
├── outputs/                <- what it produced
├── reports/                <- structured reports the metrics come from
├── <step>.log              <- what the TOOL printed
└── sc_<step>_<index>.log   <- what SiliconCompiler did around it
```

`<step>.log` is the tool's own output -- read it first when a tool failed.
`sc_<step>_<index>.log` is SiliconCompiler's: which files it staged, the exact
command line it ran, what it read back out. Read that when the tool looks like it
was given the wrong thing.

`build/<design>/<jobname>/job.log` is the whole run, and the error message
prints its path for you.

[Directory structures](https://docs.siliconcompiler.com/en/latest/user_guide/directories.html#build-directory) documents the rest of the tree.


### Reproducing it faster

A failing node can usually be re-run on its own, without repeating what already
worked. A re-run **resumes** by default:

```python
project.option.add_from("synthesis")   # start here, reuse earlier results
project.option.add_to("synthesis")     # and stop here
```

That reuses the inputs the failing node received last time, so the loop is edit,
re-run one node, look. See
[Run only part of the flow](https://docs.siliconcompiler.com/en/latest/user_guide/howto.html#howto) for the details, including how to
drop individual nodes with [`[option,prune]`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-project-option-prune).

To start clean instead -- when you suspect stale state rather than a real
failure:

```python
project.option.set_clean(True)      # do not resume; rebuild from scratch
```


### Seeing more

Two different knobs, often confused:

```python
project.logger.setLevel("DEBUG")    # SiliconCompiler's own verbosity
project.option.set_quiet(False)     # let the tool's output through
```

The first changes what SiliconCompiler tells you about scheduling, file staging
and metric collection. The second controls whether the tool's own chatter reaches
your terminal -- it is in `<step>.log` either way. If a run looks stuck,
`quiet=False` is usually what you want.


### Checking configuration without running

```python
project.check_manifest()
```

The check runs against the configuration [`Project.run()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.project.Project.run) would execute, so
values a run infers for you -- the design fileset, the ASIC main library -- are
reported as warnings rather than errors, and your project is left unmodified. To
also confirm that the source files resolve, use `design.check_filepaths()` above.


### Asking for help

When the failure is in a tool rather than your script, `sc-issue` packages a
self-contained, runnable reproduction -- the manifest, the input files and the
tool setup for one node:

```bash
sc-issue -cfg build/<design>/<jobname>/<step>/<index>/inputs/<design>.pkg.json
```

It writes `sc_issue_<...>.tar.gz`, which anyone can replay with:

```bash
sc-issue -run sc_issue_<...>.tar.gz
```

By default it includes the libraries the node used. `-exclude_libraries` with
`-add_library <name>` narrows that, which matters if some of them are
confidential. See [sc-issue](https://docs.siliconcompiler.com/en/latest/reference_manual/apps.html#app-sc-issue) for the full switch list.

Attach that archive to a [Discussion](https://github.com/siliconcompiler/siliconcompiler/discussions) or an
[issue](https://github.com/siliconcompiler/siliconcompiler/issues). A
reproduction turns "it failed" into something someone can fix.


### Failures that are not errors

A run can succeed and still be wrong. The summary table is where that shows up:

- [`[metric,errors]`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-project-metric-errors) and [`[metric,warnings]`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-project-metric-warnings) -- non-zero on a
  "successful" run is worth reading.
- [`[metric,setupslack]`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-asic-metric-setupslack) / [`[metric,holdslack]`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-asic-metric-holdslack) -- negative means
  timing did not close, and no tool will stop you.
- [`[metric,drvs]`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-asic-metric-drvs) -- [routing](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-routing) and connectivity violations.
  [`[metric,drcs]`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-asic-metric-drcs) is the different, geometric one; see
  [the FAQ](https://docs.siliconcompiler.com/en/latest/user_guide/faq.html#faq).
- [`[metric,unconstrained]`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-asic-metric-unconstrained) -- endpoints with no timing constraint. A
  large number usually means a missing or wrong [SDC](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-SDC).

[Checklists](https://docs.siliconcompiler.com/en/latest/user_guide/checklist.html#checklists) exist to turn those into a pass/fail gate rather
than something you have to remember to look at.

> **Seealso**
> [Working with Metrics](https://docs.siliconcompiler.com/en/latest/development_guide/metrics.html#dev-metrics) for reading any of these back out
> of a run, and [How do I...?](https://docs.siliconcompiler.com/en/latest/user_guide/howto.html#howto) for the recipes referenced above.


---

Source: https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/picorv32_ram.html

## Building Your Own SoC

This tutorial builds an [ASIC](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-ASIC) containing a PicoRV32 RISC-V CPU core, and
then the same core wired to an [SRAM](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-SRAM) -- the first step toward a real
[system-on-chip](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-SoC).

It is the natural next step after the [Quickstart](https://docs.siliconcompiler.com/en/latest/user_guide/quickstart.html#quickstart-guide),
because it introduces the two things that quickstart's single-file design does
not: **sources fetched from another repository**, and **composing your design out
of someone else's**.

Everything here comes from
[examples/picorv32](https://github.com/siliconcompiler/siliconcompiler/tree/main/examples/picorv32),
which is three files:

```text
examples/picorv32/
├── make.py            <- the build script; everything below is in here
├── picorv32.sdc       <- clock constraint
└── picorv32_top.v     <- wrapper that connects the core to an SRAM
```

The CPU source is **not** among them, and does not need to be downloaded --
see below.


### Running It

From that directory:

```bash
smake syn                              # synthesis only, quickest check
smake asic                             # full RTL-to-GDS, bare core
smake asic --fileset rtl.memory        # full RTL-to-GDS, core + SRAM
```

`make.py` exposes each function as a target;
[smake](https://docs.siliconcompiler.com/en/latest/reference_manual/apps.html#app-smake) discovers them and turns their arguments into
command-line switches. `smake --help` lists what is available.

The default [PDK](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-PDK) is `freepdk45`; `asap7` and `gf180` also work
(`--pdk asap7`), because the design carries a matching constraint fileset for
each. The full flow takes appreciably longer than the Quickstart's heartbeat --
most of it in [routing](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-routing).


### Where the Sources Come From

The design does not vendor the CPU. It declares a [dataroot](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-dataroot) pointing at
the upstream repository, pinned to a commit, and SiliconCompiler fetches and
caches it on first use:

```python
# Here, we're fetching the picorv32 source code directly from its GitHub repository
# at a specific commit hash to ensure reproducibility.
self.set_dataroot('picorv32',
                  'git+https://github.com/YosysHQ/picorv32.git',
                  'c0acaebf0d50afc6e4d15ea9973b60f5f4d03c42')
# We also define a dataroot for local files associated with this example script.
self.set_dataroot('example', __file__)


```

This is the pattern to copy for any third-party RTL. Pinning the commit is what
makes the build reproducible; without it, "the same script" silently means
something different next month. The cache lives in
[~/.sc/cache](https://docs.siliconcompiler.com/en/latest/user_guide/directories.html#sc-home), so the fetch happens once per machine, not once
per run.


### Part 1: The Bare Core

The `rtl` [fileset](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-fileset) is the core on its own:

```python
with self.active_fileset("rtl"):
    # Set the active data source for the following files.
    with self.active_dataroot("picorv32"):
        # Define the top-level module for this configuration.
        self.set_topmodule("picorv32")
        # Add the main Verilog source file to the fileset.
        self.add_file("picorv32.v")


```

Building it is the same three steps as any other project -- load the design, add
the filesets, apply a target:

```python
def asic(fileset: str = "rtl", pdk: str = "freepdk45"):
    """
    Configures and runs the full default ASIC flow (synthesis, place-and-route, etc.).
    """
    # Create a standard ASIC project.
    project = ASIC()

    # Load the design configuration.
    project.set_design(PicoRV32Design())
    # Add the RTL fileset.
    project.add_fileset(fileset)
    # Add the corresponding SDC fileset for the selected PDK. This is crucial for timing.
    project.add_fileset(f"sdc.{pdk}")

    # Load the target technology settings for the chosen PDK.
    asic_target(project, pdk=pdk)

    # Run the default flow defined in the target (usually a full ASIC flow).
    project.run()
    # Display a summary of the final results.
    project.summary()
    # Save the project state (results, logs, etc.) to a file for later inspection.
    project.snapshot()

```

I/O signals are placed around the edges of the die area without a pin
constraint, which is why they appear evenly distributed rather than grouped.


### Part 2: Adding an SRAM

A CPU core is not much use without memory. A real SoC would also want a SPI
interface for external non-volatile memory, a UART, a debug interface and a
cache -- this adds the first of those pieces.

The SRAM does not have to be built or downloaded. `lambdalib` ships a
single-port RAM, and the `rtl.memory` fileset composes it with the core:

```python
with self.active_fileset("rtl.memory"):
    # Add the picorv32 core Verilog file.
    with self.active_dataroot("picorv32"):
        # The top module for this version is a wrapper.
        self.set_topmodule("picorv32_top")
        self.add_depfileset(self, "rtl")
    # Add local wrapper files.
    with self.active_dataroot("example"):
        self.add_file("picorv32_top.v")
        # This is a key feature: it declares that this fileset depends on the
        # 'rtl' fileset from the 'Spram' design. SiliconCompiler will automatically
        # pull in and compile the SRAM module.
        self.add_depfileset(Spram(), "rtl")


```

Two things are worth pulling out of that block, because together they are the
whole mechanism for building a design out of other designs:

- [`Design.add_depfileset()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Design.add_depfileset) **declares a dependency on another design's
  fileset.** `add_depfileset(self, "rtl")` pulls in this design's own bare-core
  fileset, and `add_depfileset(Spram(), "rtl")` pulls in the RAM. Their sources
  are resolved and compiled with yours -- you never name their files.
- The **top module changes** to `picorv32_top`, the local wrapper that
  instantiates the core and the RAM and connects them.

So `rtl.memory` is not a modified copy of `rtl`; it is `rtl` plus a
library plus a wrapper. Swapping between the two configurations is a fileset
argument, nothing more.

[`Project.write_depgraph()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.project.Project.write_depgraph) draws what a project resolved to, which is the
quickest way to confirm a design is composed the way you think it is. Call it on
a project you have added filesets to -- no run required:

```
project.write_depgraph("picorv32.png")
```

Reading down from the design: `rtl.memory` pulls in both `picorv32/rtl` and
`la_spram/rtl`, and the SRAM brings a dependency of its own that you never had
to name. The `sdc.freepdk45` branch is the constraint fileset added alongside
the RTL one -- change the PDK and that branch changes with it.

The graph above is drawn before `asic_target` is applied, so it is the design's
own shape. Call it *after* the target and the PDK, the [standard cell](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-standard-cell)
library and every [macro](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-macro) library the target registers join the picture -- the honest view of a
build, and a considerably wider one.

> **Note**
> This SRAM is soft -- it is RTL, synthesized along with everything else. That
> is the simplest thing that works, and it is what makes this example run on any
> of the three PDKs. A production SoC would use a **hardened** memory macro
> instead, with fixed timing and area; see
> [Instantiating a hardened module](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/hardened.html#hardened-modules) for how a
> pre-implemented block is packaged and placed.


### Results

Outputs land in `build/picorv32/job0/`. The final layout is under
`write.gds/0/outputs/`, and metrics are summarised at the end of the run by
[`Project.summary()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.project.Project.summary). To open the layout:

```bash
sc-show -design picorv32                        # the finished GDS
sc-show -design picorv32 -arg_step floorplan.init   # an intermediate stage
```

[sc-show](https://docs.siliconcompiler.com/en/latest/reference_manual/apps.html#app-sc-show) needs a viewer -- [KLayout](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/tools.html#tool-klayout) is
the usual choice. [Directory structures](https://docs.siliconcompiler.com/en/latest/user_guide/directories.html#build-directory) explains the rest
of the tree, and [Working with Metrics](https://docs.siliconcompiler.com/en/latest/development_guide/metrics.html#dev-metrics) covers what the
summary is showing you.


### Extending Your Design

You now have the two techniques that hierarchical design rests on: pulling
sources from another repository, and composing filesets from other designs. From
here:

- [Instantiating a hardened module](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/hardened.html#hardened-modules) -- replace the soft
  SRAM with a [hardened macro](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-hardened-macro).
- [Multi-Job Flows](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/multi_job_flows.html#multi-job-flows) -- run implementation and
  [signoff](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-signoff) as
  separate jobs, or sweep a parameter across many.
- [Parallel Job Execution](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/parallel.html#parallel-execution) -- run those jobs
  concurrently.


---

Source: https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/fpga.html

## Build for an FPGA

SiliconCompiler compiles to [FPGA](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-FPGA) [bitstreams](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-bitstream) as well as to [GDSII](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-GDSII), through the
same schema, the same [flowgraph](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-flowgraph) and the same run. What changes is the project
type, the thing you target, and the artifact you get back.

For a lot of readers this is the easier on-ramp: an FPGA flow needs no [PDK](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-PDK), no
foundry agreement and no [tapeout](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-tapeout) budget, and the open-source toolchain for
Lattice iCE40 parts is a package-manager install away.

|  | ASIC | FPGA |
| --- | --- | --- |
| Project type | [`ASIC`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.ASIC) | [`FPGA`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGA) |
| What you target | a [PDK](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/pdks.html#builtin-pdks) and standard cell libraries | an [`FPGADevice`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGADevice) -- one part |
| How you target it | `target(project)` | `project.set_fpga(...)` |
| Extra constraints | SDC timing constraints | SDC, plus a pin-assignment file (PCF/XDC) |
| Output | GDSII | a bitstream |


### Check your install first

The FPGA equivalent of the [ASIC demo](https://docs.siliconcompiler.com/en/latest/user_guide/installation.html#asic-demo) builds an 8-bit counter
onto a small open architecture called **z1000**:

```bash
python -m siliconcompiler.demos.fpga_demo
```

It runs Yosys for [synthesis](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-synthesis), [VPR](https://docs.verilogtorouting.org/en/latest/) for
[place-and-route](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-place-and-route) and OpenSTA for timing, so a clean run tells you that half of
your toolchain is working. z1000 is a demo architecture -- 2K [LUTs](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-LUT), no hard
macros -- and exists to be a self-test, not a part you would ship to.


### A real part: blinky on an iCE40

[examples/blinky](https://docs.siliconcompiler.com/en/latest/user_guide/examples.html#example-blinky) builds a [bitstream](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-bitstream) for a Lattice
iCE40 UP5K, the part on an [iCEBreaker](https://github.com/icebreaker-fpga/icebreaker) board:

```python
design = Design("blinky")
# Set up a 'dataroot' to easily reference local files.
design.set_dataroot("blinky", __file__)

# Configure the "rtl" (Register-Transfer Level) fileset.
with design.active_dataroot("blinky"), design.active_fileset("rtl"):
    design.set_topmodule("blinky")
    design.add_file("blinky.v")

# Configure the "pcf" (Physical Constraints File) fileset.
# This is a crucial file for FPGAs. It maps the ports in the Verilog
# design (e.g., 'clk', 'led') to the physical pins on the FPGA.
with design.active_dataroot("blinky"), design.active_fileset("pcf"):
    design.add_file("icebreaker.pcf")

# Project Setup
# Create an FPGA, which is tailored for FPGA-specific needs.
project = FPGA(design)

# Tell the project which filesets are required for this compilation.
project.add_fileset("rtl")
project.add_fileset("pcf")

# FPGA Target Configuration
# Apply this FPGA configuration to the project.
project.set_fpga(ICE40Up5k_sg48())

# Flow Loading
# Set the compilation flow. The FPGANextPNRFlow is a pre-built flow
# that uses open-source tools like Yosys for synthesis and nextpnr
# for place-and-route.
project.set_flow(fpgaflow.FPGANextPNRFlow())


```

Three things differ from an [ASIC](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-ASIC) script:

- **A second constraint fileset.** `pcf` is a [fileset](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-fileset) holding the pin-constraint file, which
  maps ports in your [Verilog](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-Verilog) onto physical pins on the package. Without it the
  tools have no idea where `led` goes.
- **A device instead of a target.** [`FPGA.set_fpga()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGA.set_fpga) takes an
  [`FPGADevice`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGADevice) -- here `ICE40Up5k_sg48`, shipped in
  `siliconcompiler.fpgas`. The device carries the architecture description,
  the primitives Yosys may map to and the timing models, which is what a [PDK](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-PDK) plus
  a cell library does on the ASIC side.
- **An FPGA flow.** [FPGANextPNRFlow](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/flows.html#schema-siliconcompiler-flows-fpgaflow-fpganextpnrflow) is Yosys plus
  [nextpnr](https://github.com/YosysHQ/nextpnr) plus `icepack`.

Run it:

```bash
cd examples/blinky
python blinky.py
```

The summary reports resource utilisation -- [LUTs](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-LUT), flip-flops, carry cells --
rather than cell area, because those are the numbers that decide whether a
design fits.


### Which flow

| Flow | Tools | For |
| --- | --- | --- |
| [FPGANextPNRFlow](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/flows.html#schema-siliconcompiler-flows-fpgaflow-fpganextpnrflow) | yosys, nextpnr, icepack | Lattice iCE40 and similar open-toolchain parts |
| [FPGAVPRFlow](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/flows.html#schema-siliconcompiler-flows-fpgaflow-fpgavprflow) | yosys, VPR | Research and custom architectures described in VPR's XML |
| [FPGAVPROpenSTAFlow](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/flows.html#schema-siliconcompiler-flows-fpgaflow-fpgavpropenstaflow) | the above, plus OpenSTA | The same, when you also want timing analysis |
| [FPGAXilinxFlow](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/flows.html#schema-siliconcompiler-flows-fpgaflow-fpgaxilinxflow) | Vivado | Xilinx parts; needs a Vivado licence |

`examples/heartbeat` carries a Xilinx target alongside its ASIC ones, so the
same design goes to an Artix-7 with `smake fpga`.


### Installing the tools

`sc-install` has an FPGA group:

```bash
sc-install -group fpga
```

That covers `sv2v`, `yosys`, `wildebeest`, `vpr` and `opensta` -- the
VPR path. **It does not include** `nextpnr` or `icepack`, which the iCE40
example above needs; install those from your package manager or the
[nextpnr](https://github.com/YosysHQ/nextpnr) and
[icestorm](https://github.com/YosysHQ/icestorm) projects.

See [External Tools](https://docs.siliconcompiler.com/en/latest/user_guide/installation.html#external-tools) for what is script-installable on your
platform, and [Docker](https://docs.siliconcompiler.com/en/latest/user_guide/docker.html#docker) to skip installing entirely. Vivado is a
vendor tool and has to be installed and licensed separately.


### Defining your own device

[`FPGADevice`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGADevice) is a library -- it derives from the same base as a standard
cell library -- so describing a new part is the job covered by
[Defining a Library](https://docs.siliconcompiler.com/en/latest/development_guide/libraries.html#dev-libraries), and packaging one to share is
[Packaging an External Library](https://docs.siliconcompiler.com/en/latest/development_guide/external_libraries.html#dev-external-libraries).

For a complete worked device, read `siliconcompiler/demos/fpga_demo.py`: `Z1000`
sets the [LUT](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-LUT) size, the register types Yosys may infer, the VPR architecture and
routing-graph files, and the [Liberty](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-Liberty) models OpenSTA reads.


### Next

- [Lint your RTL](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/lint.html#lint-tutorial) -- faster still, and needs nothing
  installed.
- [Example designs](https://docs.siliconcompiler.com/en/latest/user_guide/examples.html#examples) -- `blinky` and the rest, with what each
  one needs.
- [Compilation Process](https://docs.siliconcompiler.com/en/latest/user_guide/execution_model.html#execution-model) -- how a flow is put together, if
  you want to build your own.


---

Source: https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/hw_frontends.html

## Hardware Design Frontends

In addition to traditional hardware description languages like Verilog and SystemVerilog, SiliconCompiler also supports higher-level languages, for ease of hardware design prototyping.

Here are some tutorials of a few different types of high-level hardware design frontends:

- Python-based frontends (Migen)
- chisel frontend
- C HLS frontend (Bambu)
- bluespec frontend
- MLIR frontend, for machine learning models (SODA)


### Python frontends

Since SC itself is a Python library, it can be used as-is in an end-to-end build script with any Python-based HDL that can be scripted to export designs to Verilog.

For example, if you have SC installed already, you can quickly get started building designs written in the Migen HDL.
To install Migen, run `pip install migen`. Then, paste the following into a file called "heartbeat_migen.py".

examples/heartbeat_migen/heartbeat_migen.py

```
#!/usr/bin/env python3

import os.path

# Import the necessary components from the Migen library for hardware design.
# Migen allows you to describe hardware circuits using Python.
from migen import Module, Signal, Cat, Replicate
from migen.fhdl.verilog import convert

# Import the core classes from the siliconcompiler library.
from siliconcompiler import Design
from siliconcompiler import ASIC
# Import a pre-defined target for the FreePDK45 process.
from siliconcompiler.targets import freepdk45_demo


# Migen Hardware Description
# This class defines the 'Heartbeat' hardware module using Migen's syntax.
class Heartbeat(Module):
    """
    A simple digital circuit that generates a periodic single-cycle pulse.

    This module contains a counter that increments on every clock cycle.
    The output 'out' goes high for a single clock cycle when the counter
    reaches a specific value (1 in this case) and is low otherwise.

    Args:
        N (int): The bit-width of the internal counter.
    """
    def __init__(self, N: int = 8):
        # I/O Declaration
        # Declare a 1-bit output signal for the module.
        self.out = Signal()

        # Internal Register Declaration
        # Declare an N-bit register to be used as a counter.
        self.counter_reg = Signal(N)

        # COMBINATORIAL AND SEQUENTIAL LOGIC #

        # The 'self.sync' domain is used to describe synchronous logic
        # that updates on the positive edge of the 'sys' clock.

        # On each clock cycle, increment the counter.
        self.sync += self.counter_reg.eq(self.counter_reg + 1)

        # Describe the logic for the output signal.
        # 'Cat' concatenates signals, and 'Replicate' creates a bitstring
        # of repeated values. So, Cat(Replicate(0, N-1), 1) creates the
        # binary value '00...01'. The output 'out' will be high only
        # when the counter is exactly 1.
        self.sync += self.out.eq(self.counter_reg == Cat(Replicate(0, N - 1), 1))


def main():
    """
    Generates Verilog from a Migen module and runs it through a full
    ASIC compilation flow using SiliconCompiler.

    Requires: migen (pip), yosys, openroad, opensta, klayout; freepdk45 (via lambdapdk)
    """
    # Verilog Generation
    # Instantiate the Migen Heartbeat module.
    heartbeat = Heartbeat()
    # Convert the Migen module into a Verilog file.
    # The `convert` function translates the Python hardware description
    # into standard Verilog HDL. We name the output module 'heartbeat'
    # and write it to 'heartbeat.v'.
    convert(heartbeat, ios={heartbeat.out}, name='heartbeat').write('heartbeat.v')

    # SiliconCompiler Design Setup
    # Create a design object to hold the configuration.
    design = Design("heartbeat")

    # Set the root directory for this design's source files using its filepath.
    design.set_dataroot("heartbeat", __file__)

    # Configure the RTL (Verilog) source files. A 'fileset' is a collection
    # of files for a specific purpose.
    with design.active_fileset("rtl"):
        # Set the name of the top-level module.
        design.set_topmodule("heartbeat")
        # Add the Verilog file we just generated.
        design.add_file(os.path.abspath("heartbeat.v"))

    # Configure the SDC (Synopsys Design Constraints) file for timing.
    # This fileset is separate from the RTL.
    with design.active_dataroot("heartbeat"), design.active_fileset("sdc"):
        design.add_file("heartbeat.sdc")

    # SiliconCompiler Project Setup
    # Create an ASIC project from the design configuration.
    project = ASIC(design)

    # Tell the project which filesets are needed for the compilation flow.
    project.add_fileset(["rtl", "sdc"])

    # Load the pre-defined target for the FreePDK45 demo process.
    # This configures the project with the correct PDK, standard cell libraries,
    # and tool flow for this technology.
    freepdk45_demo(project)

    # Execution & Analysis
    # Execute the complete ASIC compilation flow (synthesis, place, route, etc.).
    project.run()

    # Print a summary of the results (timing, area, power, etc.).
    project.summary()

    # Display the final physical layout in a GDS viewer (like KLayout).
    project.show()


if __name__ == '__main__':
    main()

```

Run this file with `python3 heartbeat_migen.py` to compile your Migen design down to a GDS and automatically display it in KLayout.

In this example, the `Heartbeat` class describes a design as a Migen module, and the `main()` function implements the build flow.
The flow begins by using Migen's built-in functionality for exporting the design as a file named "heartbeat.v".
The rest of the flow uses SC's core API to take this Verilog file and feed it into a basic [asicflow](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/flows.html#schema-siliconcompiler-flows-asicflow-asicflow) build, as described in the [Quickstart guide](https://docs.siliconcompiler.com/en/latest/user_guide/quickstart.html#quickstart-guide). For more info on how Migen works, see the [Migen docs](https://m-labs.hk/migen/manual/).

Although we wrote this example using Migen in particular, the concepts apply to other Python-based HDLs, such as [MyHDL](https://www.myhdl.org/) or [Amaranth](https://github.com/amaranth-lang/amaranth) (note that Amaranth's Verilog backend requires Yosys installed locally).


### Chisel frontend

SiliconCompiler has a [Chisel](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/tools.html#tool-chisel) frontend that enables you to build Chisel designs for any supported SC target.
To get started using Chisel with SC, ensure that SC is installed following the directions from the [Installation](https://docs.siliconcompiler.com/en/latest/user_guide/installation.html#installation) section, and [install sbt](https://www.scala-sbt.org/download.html).
See the [External Tools](https://docs.siliconcompiler.com/en/latest/user_guide/installation.html#external-tools) section for helpful build scripts.

To build a Chisel design, the only thing you need to do differently from a configuration perspective is:
Add all required Scala files as sources.
Keep in mind that other frontend-specific features such as include or library directories are not yet supported for the Chisel frontend.

Otherwise, you can configure the build as normal.

For example, to build the GCD example from the [Chisel project template repo](https://github.com/chipsalliance/chisel-template), first copy the following code into a file called "GCD.scala".

examples/gcd/GCD.scala

```scala
import chisel3._

/**
  * Compute GCD using subtraction method.
  * Subtracts the smaller from the larger until register y is zero.
  * value in register x is then the GCD
  */
class GCD extends Module {
  val io = IO(new Bundle {
    val value1        = Input(UInt(16.W))
    val value2        = Input(UInt(16.W))
    val loadingValues = Input(Bool())
    val outputGCD     = Output(UInt(16.W))
    val outputValid   = Output(Bool())
  })

  val x  = Reg(UInt())
  val y  = Reg(UInt())

  when(x > y) { x := x - y }
    .otherwise { y := y - x }

  when(io.loadingValues) {
    x := io.value1
    y := io.value2
  }

  io.outputGCD := x
  io.outputValid := y === 0.U
}

```

This design can then be quickly compiled to a GDS using Python:

examples/gcd/gcd_chisel.py

```python
#!/usr/bin/env python3

# Import the core classes from the siliconcompiler library.
from siliconcompiler import ASIC, Design
# Import a pre-defined target for the FreePDK45 process.
from siliconcompiler.targets import freepdk45_demo
# Import a specialized flow designed to handle Chisel source files.
from siliconcompiler.flows.asicflow import ChiselASICFlow


def main():
    """
    Builds the 'gcd' (Greatest Common Divisor) design using the FreePDK45 PDK.

    This script demonstrates a Chisel-to-GDSII flow. It sets up an ASIC
    project with a Chisel source file (.scala), loads the FreePDK45 target,
    runs a specialized compilation flow to handle the Chisel to Verilog
    conversion, and finally displays a summary and the final layout.
    """
    # Design Setup
    # Create a design object to hold the configuration.
    design = Design("gcd")

    # Set up a 'dataroot' to easily reference local files.
    design.set_dataroot("gcd", __file__)

    # Configure the "rtl" fileset. Note that the source file is Chisel (.scala).
    # The ChiselASICFlow will automatically convert this to Verilog.
    with design.active_dataroot("gcd"), design.active_fileset("rtl"):
        # The topmodule is the name of the Chisel 'class' to be compiled.
        design.set_topmodule("GCD")
        design.add_file("GCD.scala")

    # Configure the SDC (timing constraints) file. Chisel names the clock port
    # of a Module 'clock', so this flow needs its own constraints rather than
    # the 'clk' used by the hand-written gcd.v.
    with design.active_dataroot("gcd"), design.active_fileset("sdc"):
        design.add_file("gcd_chisel.sdc")

    # Project Setup
    # Create an ASIC project from the design configuration.
    project = ASIC(design)

    # Tell the project which filesets are needed for the compilation flow.
    project.add_fileset(["rtl", "sdc"])

    # Load the pre-defined target for the FreePDK45 demo process.
    freepdk45_demo(project)

    # Set the project to use the ChiselASICFlow. This pre-built flow
    # automatically inserts a Chisel-to-Verilog conversion step at the
    # beginning, before running the standard synthesis and PnR tools.
    project.set_flow(ChiselASICFlow())

    # Execution & Analysis
    # Execute the complete compilation flow.
    project.run()

    # Print a summary of the results (timing, area, power, etc.).
    project.summary()

    # Display the final physical layout in a GDS viewer (like KLayout).
    project.show()


if __name__ == '__main__':
    main()

```

For more information on creating designs using Chisel, see the [Chisel docs](https://www.chisel-lang.org/docs).


### C HLS frontend

SiliconCompiler supports high-level synthesis of C code to any supported SC target, implemented using the [Bambu](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/tools.html#tool-bambu) HLS tool.
To get started compiling C code with SC, ensure that SC is installed following the directions from the [Installation](https://docs.siliconcompiler.com/en/latest/user_guide/installation.html#installation) section, and [build Bambu from source](https://panda.dei.polimi.it/?page_id=88).
See the [External Tools](https://docs.siliconcompiler.com/en/latest/user_guide/installation.html#external-tools) section for helpful build scripts.

To build a C design, the only thing you need to do differently from a configuration perspective is:
Add all required C files as inputs.

Otherwise, you can configure the build as normal.

For example, to implement a GCD function as a circuit, first copy the following into a file called "gcd.c".

examples/gcd/gcd.c

```c
#include <stdio.h>

short gcd(short a, short b) {
    if (b > a) {
        short tmp = a;
        a = b;
        b = tmp;
    }

    while (a != 0 && b != 0) {
        short r = a % b;
        a = b;
        b = r;
    }

    if (a == 0)
        return b;
    else
        return a;
}

int main() {
    printf("gcd(4, 4) = %d\n", gcd(4, 4));
    printf("gcd(27, 36) = %d\n", gcd(27, 36));
    printf("gcd(270, 192) = %d\n", gcd(270, 192));

    return 0;
}

```

This design can then be quickly compiled to a GDS using Python:

examples/gcd/gcd_hls.py

```python
#!/usr/bin/env python3
# Copyright 2020-2025 Silicon Compiler Authors. All Rights Reserved.

from siliconcompiler import ASIC, Design
from siliconcompiler.targets import freepdk45_demo
# Import a specialized flow designed to handle High-Level Synthesis.
from siliconcompiler.flows.asicflow import HLSASICFlow


def main():
    """
    Builds the 'gcd' design using the FreePDK45 PDK via a High-Level Synthesis (HLS) flow.

    This script demonstrates how to take a C source file (`gcd.c`) as the primary
    design input. It uses a specialized HLS flow to first synthesize the C code
    into Verilog RTL, and then runs that RTL through the standard GDSII compilation
    process.
    """
    # Design Setup
    # Create a design object to hold the configuration.
    design = Design("gcd")

    # Set up a 'dataroot' to easily reference local files.
    design.set_dataroot("gcd", __file__)

    # Configure the input fileset. While named "rtl", in an HLS flow,
    # the primary source is C/C++, not Verilog.
    with design.active_dataroot("gcd"), design.active_fileset("rtl"):
        design.set_topmodule("gcd")
        # Add the C source file as the design input.
        design.add_file("gcd.c")

    # Configure the SDC (timing constraints) file for the HLS-generated module.
    with design.active_dataroot("gcd"), design.active_fileset("sdc"):
        design.add_file("gcd_hls.sdc")

    # Project Setup
    # Create an ASIC project from the design configuration.
    project = ASIC(design)

    # Enable the necessary filesets for the compilation flow.
    project.add_fileset(["rtl", "sdc"])

    # Load the pre-defined target for the FreePDK45 demo process.
    freepdk45_demo(project)

    # Set the project to use the HLSASICFlow. This is a pre-built flow
    # that automatically inserts an HLS step (using a tool like Bambu) at the
    # beginning to convert the C code to Verilog.
    project.set_flow(HLSASICFlow())

    # Execution & Analysis
    # Execute the complete HLS-to-GDSII compilation flow.
    project.run()

    # Print a summary of the results (timing, area, power, etc.).
    project.summary()

    # Display the final physical layout in a GDS viewer.
    project.show()


if __name__ == '__main__':
    main()

```

For more information on the Bambu project used for implementing this frontend, see their [docs](https://panda.dei.polimi.it/?page_id=31).


### Bluespec frontend

SiliconCompiler has a Bluespec frontend that enables you to build [bluespec](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/tools.html#tool-bluespec) designs for any supported SC target.
To get started using Bluespec with SC, ensure that SC is installed following the directions from the [Installation](https://docs.siliconcompiler.com/en/latest/user_guide/installation.html#installation) section, and download bsc or install it from source following the directions [here](https://github.com/B-Lang-org/bsc#download).
See the [External Tools](https://docs.siliconcompiler.com/en/latest/user_guide/installation.html#external-tools) section for helpful build scripts.

To build a Bluespec design, the only thing you need to do differently from a configuration perspective is:
Add the Bluespec top-level package as an 'input', and add all directories containing imported modules as entries in [`[fileset,<fileset>,idir]`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-design-fileset-idir).

Otherwise, you can configure the build as normal.

For example, to build this fibonacci example adapted from the [bsc smoke test](https://github.com/B-Lang-org/bsc/blob/main/examples/smoke_test/FibOne.bsv), first copy the following code into a file called "FibOne.bsv".

examples/fibone/FibOne.bsv

```systemverilog
interface FibOne_IFC;
   method Action nextFib;
   method ActionValue #(int)  getFib;
endinterface

(* synthesize *)
module mkFibOne(FibOne_IFC);
   // register containing the current Fibonacci value
   Reg#(int) this_fib <- mkReg (0);
   Reg#(int) next_fib <- mkReg (1);

   method Action nextFib;
      this_fib <= next_fib;
      next_fib <= this_fib + next_fib;  // note that this uses stale this_fib
  endmethod

  method ActionValue#(int) getFib;
    return this_fib;
  endmethod

endmodule: mkFibOne


```

This design can then be quickly compiled to a GDS using Python:

examples/fibone/fibone.py

```python
#!/usr/bin/env python3

# Import the core classes from the siliconcompiler library.
from siliconcompiler import ASIC, Design
# Import a pre-defined target for the FreePDK45 process.
from siliconcompiler.targets import freepdk45_demo


def main():
    '''
    This script demonstrates a Bluespec SystemVerilog (BSV) to GDSII flow.
    It shows that a Bluespec design needs no custom flow: the target reads the
    source language off the design's files and puts the Bluespec compiler in
    front of the standard synthesis, place, and route steps.

    Requires: bsc (Bluespec), yosys, openroad, opensta, klayout; freepdk45 (via lambdapdk)
    '''

    # Design Setup
    # Create a design schema to hold the project's configuration.
    design = Design("fibone")
    # Set up a 'dataroot' to easily reference local files.
    design.set_dataroot("fibone", __file__)

    # Configure the "rtl" fileset.
    # Note that the source file is a '.bsv' file, not Verilog.
    with design.active_dataroot("fibone"), design.active_fileset("rtl"):
        # The topmodule 'mkFibOne' is the name of the compiled module
        # generated by the Bluespec compiler, not the file name.
        design.set_topmodule("mkFibOne")
        design.add_file("FibOne.bsv")

    # Project Setup
    # Create a standard ASIC project.
    project = ASIC(design)

    # Tell the project to use the "rtl" fileset we defined.
    project.add_fileset("rtl")

    # Target Loading
    # Load the target configuration for the FreePDK45 technology. This is the
    # key part of the example: the target picks the flow's front end from the
    # design's sources, so the .bsv file above selects a 'convert' step running
    # the Bluespec compiler (bsc) where a Verilog design would get 'elaborate'.
    # The resulting flow is named 'asicflow-bluespec'. Passing
    # language="bluespec" here would select the same front end explicitly.
    freepdk45_demo(project)

    # Execution & Analysis
    # Run the flow. SiliconCompiler will execute the 'convert' step first, then
    # proceed with synthesis, place, route, and GDS export.
    project.run()

    # Display a summary of the results (timing, area, etc.).
    project.summary()

    return project


if __name__ == '__main__':
    main()

```

For more information on creating designs using Bluespec, see the [Bluespec docs](https://github.com/B-Lang-org/bsc#documentation).


### MLIR frontend (SODA)

SiliconCompiler can take a machine learning model straight to hardware using
[SODA Synthesizer](https://github.com/pnnl/soda-opt), whose front end
works in [MLIR](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-MLIR).
A model converted to the TOSA dialect -- the form PyTorch, TensorFlow and
TFLite models are brought into -- is then lowered to linalg, a kernel is
outlined and optimized for high-level synthesis by `soda-opt`, and
Bambu turns that kernel into Verilog for the rest of the
flow.

The design's source fileset holds a `.mlir` file instead of Verilog, and the
topmodule is the *outlined kernel*: `soda-opt` names it after the function it
came from, so a model whose entry point is `forward` yields
`forward_kernel`.

```python
design = Design("mm")
design.set_dataroot("soda", __file__)
with design.active_dataroot("soda"), design.active_fileset("soda"):
    design.set_topmodule("forward_kernel")
    design.add_file("mm.mlir")

project = ASIC(design)
project.add_fileset(["soda", "sdc"])
freepdk45_demo(project)
project.set_flow(SODAASICFlow())
project.run()
```

Install the toolchain with `sc-install mlir soda`, in that order:
`soda-opt` links against MLIR's C++ libraries, so it can only be built against
the LLVM revision `mlir` installs.

[The SODA tutorial](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/soda.html#soda-tutorial) walks through the whole flow: the three
optimization strategies, each a flow of its own, and the knobs each one exposes.


---

Source: https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/soda.html

## From a model to silicon (SODA)

[SODA Synthesizer](https://github.com/pnnl/soda-opt) compiles a
machine learning model into accelerator [RTL](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-RTL). Its front end, `soda-opt`,
works in [MLIR](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-MLIR): a model exported to the TOSA dialect is lowered to
linalg, the compute worth accelerating is outlined into a kernel, that kernel is
optimized for [high-level synthesis](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-high-level-synthesis), and an HLS tool turns it into
Verilog.

SiliconCompiler drives that front end and then keeps going. Everything from the
generated Verilog onward -- [synthesis](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-synthesis), [place-and-route](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-place-and-route),
[signoff](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-signoff) -- is the ordinary [ASIC flow](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/flows.html#builtin-flows), so a model
reaches [GDSII](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-GDSII) in a single job, with one manifest recording what every
stage did.

> **Admonition**
> ## Who this is for / prerequisites
>
> You should be comfortable with the [quickstart build](https://docs.siliconcompiler.com/en/latest/user_guide/quickstart.html#quickstart-guide)
> and with the idea of a design whose sources are not Verilog (see
> [Hardware design frontends](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/hw_frontends.html#hw-frontends)).
> You do **not** need to know MLIR to follow along; the one thing worth
> knowing is that a `.mlir` file is a program in a *dialect*, and that the
> flow's job is to rewrite it into progressively lower-level dialects until it
> is something an HLS tool can read.
>
> The full flow needs `mlir`, `soda`, `bambu`, `yosys`, `openroad`,
> `opensta` and `klayout`, plus FreePDK45 from `lambdapdk`.


### Installing the toolchain

Two installs, and the order matters:

```bash
sc-install mlir soda
```

`mlir` builds llvm-project -- `mlir-opt`, `mlir-translate`, `llvm-link`,
`opt` and `clang` -- at the revision `soda-opt` is developed against.

`soda` then builds `soda-opt` and `soda-translate` against that install.
The order matters and is not a convenience: `soda-opt` is an out-of-tree MLIR
project that links against MLIR's C++ libraries, so it can only be built against
that exact LLVM revision. A distribution `mlir-tools` package will not do, and
the `soda` script stops with an explanation rather than guessing. Naming both
on one command line is enough: they are installed left to right, and a failure in
`mlir` stops before `soda` is attempted.

The whole group, including the backend, is one command:

```bash
sc-install -group asic-soda
```

> **Important**
> **The HLS step needs a Bambu built against clang 16.** LLVM 19 emits opaque
> pointers (`ptr`) unconditionally -- typed pointers were removed in LLVM 17
> -- and an older Bambu front end rejects the IR outright:
>
> ```text
> error: expected type
> define void @forward_kernel(ptr %0, ptr %1, ptr %2) {
>                             ^
> ```
>
> SiliconCompiler's `install-bambu.sh` gives Bambu clang-16 on **ubuntu24 and
> ubuntu26**, but clang-11 on ubuntu22 and clang-8 on ubuntu20. So those two are
> where the flow runs end to end; on the older pair the MLIR front end works and
> high-level synthesis does not. Nothing preflights it, so an unusable Bambu
> surfaces at the last node rather than at the start -- `bambu --help` lists
> the front ends it was built with, and `I386_CLANG16` is the one to look for.
>
> Pointing Bambu at the clang this toolchain installs is not an option, which is
> the obvious thing to try: Bambu compiles a set of *plugins* against each
> supported clang's internals, so the versions it accepts are built in rather
> than configured, and there is no `--with-clang=<path>`. Its `configure`
> knows clang 4-13 and 16 -- on the pinned release and on upstream `main`
> alike -- so clang 19 cannot be used until Bambu itself ports its plugins to
> it.


### The example

`examples/soda` holds `mm`, `mm-no_weights` model: a stateless
batched matrix multiply, which is what `torch.matmul` over a `[1, 4, 8]` and
a `[1, 8, 4]` tensor exports to.

examples/soda/mm.mlir

```text
// Batched matrix multiply, in the TOSA dialect.
//
// This is soda-benchmarks "mm-no_weights" model
// (examples/pytorch-to-gds/mm-no_weights/torchscript.py), a stateless
// torch.matmul over a [1, 4, 8] and a [1, 8, 4] tensor, exported through
// torch-mlir with output_type="tosa". Regenerate it with `smake model`, which
// runs the same export -- it is checked in so that the flow can be built
// without a PyTorch and torch-mlir install.
//
// The entry function must be named `forward`: soda-opt outlines the kernel it
// finds into `<function>_kernel`, and that outlined kernel -- `forward_kernel`
// -- is what Bambu synthesizes and what the design's topmodule has to be.
module attributes {torch.debug_module_name = "MM"} {
  func.func @forward(%arg0: tensor<1x4x8xf32>, %arg1: tensor<1x8x4xf32>) -> tensor<1x4x4xf32> {
    %0 = tosa.matmul %arg0, %arg1 : (tensor<1x4x8xf32>, tensor<1x8x4xf32>) -> tensor<1x4x4xf32>
    return %0 : tensor<1x4x4xf32>
  }
}

```

It is checked in so that the flow can be built without a PyTorch install.
`smake model` regenerates it by re-running the export, which is the one target
that needs `pip install -r requirements.txt` in the example directory first;
nothing else here does.

Two things about this file decide everything downstream.

**The entry function is called** `forward`. `soda-opt` outlines the kernel it
finds into `<function>_kernel`, so the synthesizable kernel here is
`forward_kernel`.

**The topmodule is therefore** `forward_kernel`, **not** `mm`. Bambu is
pointed at the design's topmodule, and everything after it -- synthesis, the
[SDC](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-SDC), the final GDS -- names that kernel. Getting this wrong points the
HLS tool at a function that does not exist; the `soda` task notices and says
so, but it is easier to get right the first time.


### Building it

The design's sources are MLIR rather than Verilog. Everything else about it is an
ordinary [design](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/own_design.html#own-design-tutorial):

examples/soda/make.py

```python
class SODADesign(Design):
    """The ``mm`` design: a TOSA model plus the constraints its kernel is built to.

    The topmodule is ``forward_kernel`` rather than ``mm`` because soda-opt
    outlines the kernel it finds into ``<function>_kernel``, and that outlined
    kernel is what Bambu synthesizes and what everything downstream sees.
    """

    def __init__(self):
        super().__init__()
        self.set_name("mm")

        self.set_dataroot("soda", __file__)

        with self.active_dataroot("soda"):
            # The model, in TOSA. `smake model` regenerates it. The fileset is
            # named for what it holds rather than "rtl"; nothing keys off the
            # name, and the front end looks for a .mlir file across all of them.
            with self.active_fileset("soda"):
                self.set_topmodule("forward_kernel")
                self.add_file("mm.mlir")

            # Read three times over a build: by Bambu as its high-level
            # synthesis target, then by synthesis, then by place-and-route.
            with self.active_fileset("sdc"):
                self.add_file("mm.sdc")

```

`mm.sdc` constrains the clock port Bambu gives the RTL it generates, which is
called `clock`:

examples/soda/mm.sdc

```tcl
# Bambu names the clock port of the RTL it generates "clock", so the constraint
# has to be attached to that port. The period here is what the HLS scheduler
# targets, and the same file then constrains synthesis and place-and-route.
create_clock [get_ports clock] -name core_clock -period 5

set_input_delay 1.0 -clock core_clock [all_inputs]
set_output_delay 1.0 -clock core_clock [all_outputs]

```

That one file is read three times over a build: by Bambu as the period its
scheduler has to hit, then by synthesis, then by place-and-route. Changing it
changes the hardware, not just the report.

Selecting the flow is the whole of the rest -- a model reaches [GDSII](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-GDSII) in
one job, and the only thing that says "SODA" is which flow was chosen:

```python
def asic(strategy: str = "optimized", jobname: Optional[str] = None) -> ASIC:
    """Takes the model all the way to GDSII.

    Args:
        strategy (str): The soda-opt strategy to use.
        jobname (str, optional): The job name. Defaults to the strategy.

    Returns:
        ASIC: The completed project.
    """
    project = _project()
    project.set_flow(SODAASICFlow(strategy=strategy))
    _configure(project)

    project.option.set_jobname(jobname or f"asic-{strategy}")

    project.run()
    project.summary()
    project.snapshot()
    return project

```

Run it, and every other stage, as an [smake](https://docs.siliconcompiler.com/en/latest/user_guide/howto.html#howto-smake) target:

```bash
cd examples/soda
smake elaborate     # MLIR to Verilog: soda-opt plus Bambu, nothing else
smake syn           # ...and on through synthesis and timing
smake asic          # ...and on to GDSII
```


### What the flow does

`SODAASICFlow` is the ordinary ASIC flow with the SODA front end in front of
it. The front end on its own is one of the flows in
`sodaflow`, and it is worth knowing what each of its
nodes is for, because that is where a build goes wrong:

| Node | Tool | What it does |
| --- | --- | --- |
| `tosa2linalg` | `mlir-opt` | Lowers the TOSA operations to their linalg equivalents, still on tensors. |
| `bufferize` | `mlir-opt` | Puts that linalg on buffers and turns the function's result into an out-parameter. Hardware has no notion of returning a tensor. |
| `soda` | `soda-opt` | Outlines the kernel, optimizes it for HLS, lowers it to the LLVM dialect. This is the node the three strategies differ in. |
| `translate` | `mlir-translate` | Emits LLVM IR, then strips the `llvm.stacksave` / `llvm.stackrestore` intrinsics MLIR brackets stack buffers with, which an HLS backend cannot read. |
| `runtime` | `clang` | Compiles a C support module to LLVM IR -- by default the bundled `memref_copy.c`. It has no design input, so it is a second entry node and runs alongside the rest. |
| `link` | `llvm-link` | Merges that module in, but only if the kernel calls it. Bufferized code lowers `memref.copy` to a `memrefCopy` call that upstream expects from MLIR's runner library; there is no runtime to link against in hardware, so the definition goes into the module. |
| `convert` | `bambu` | High-level synthesis: LLVM IR to Verilog. |

Everything downstream of `convert` is the flow any Verilog design uses.


### The three strategies

The `soda` node is where SODA earns its name, and it offers three ways to
lower the outlined kernel:

**`baseline`**

  No HLS-oriented optimization: linalg straight to the LLVM dialect. This is
  the reference -- what the HLS tool makes of code nobody prepared for it.

**`optimized`**

  Runs `soda-opt`'s Bambu pipeline first: the loop nest is tiled, given local
  buffers, unrolled and scalar-replaced. This is the default, and the
  difference between it and the baseline is the result the SODA papers report.

**`transformed`**

  Applies a schedule written in MLIR's transform dialect instead of the fixed
  pipeline, then lowers. This is how a design expresses a strategy the
  pipeline's knobs cannot. It needs a schedule to be worth running, so unlike
  the other two it is not exercised by the example -- write the schedule first,
  then hand it to the task.

Each strategy is a flow of its own, so picking one is picking a flow:

```python
from siliconcompiler.flows.sodaflow import SODABaselineElaborationFlow

# The front end on its own: MLIR in, Verilog out.
project.set_flow(SODABaselineElaborationFlow())
```

Any flow that elaborates a design takes one as its `frontend`, which is the
whole of how the SODA path reaches synthesis and GDSII -- there is no SODA
backend, and no language string to spell:

```python
project.set_flow(SynthesisFlow(frontend=SODABaselineElaborationFlow()))
project.set_flow(ASICFlow(frontend=SODABaselineElaborationFlow()))
```

`SODAASICFlow` is that last line with the strategy named instead, which is
what the example uses:

```python
project.set_flow(SODAASICFlow(strategy="baseline"))
```

`make.py` in the example runs the comparison the strategies exist for:

```bash
smake compare
```

which synthesizes the baseline and the optimized kernel and prints Bambu's own
estimate beside what synthesis actually produced -- how well the HLS tool
predicted the hardware, and how much the optimization bought.


### Turning the knobs

Every stage of the optimization pipeline is a task setter, so a design can be
swept over them without touching the flow. Reach the task with `find_task`
once the flow is in the project:

```python
from siliconcompiler.tools.soda.opt import OptimizedTask

project.set_flow(SODAASICFlow())

soda = OptimizedTask.find_task(project)
soda.set_soda_fullunrolls(3)      # unroll one more level of the loop nest
soda.set_soda_tilesize(2)         # tile every affine loop
soda.add_soda_permutation([1, 2, 0])
soda.set_soda_buffertrick(False)  # no local buffers for the loop nest
```

> **Important**
> A flow *copies* the task it is handed, so configuring a task object before
> passing it to `Flowgraph.node()` has no effect. `find_task` after
> `set_flow` is the way to reach the one the flow will actually run.

`set_soda_fullunrolls` is the one that moves the result most: each application
unrolls one more level, trading cells for cycles. `smake unrolled 3` in the
example synthesizes with a different depth so the trade is visible.

The transform-dialect strategy takes its schedule the same way. The schedule is
your own MLIR file, holding a `transform.named_sequence @__transform_main` that
rewrites the outlined kernel; it is required, so the flow stops at validation
without one rather than lowering the kernel unrewritten:

```python
from siliconcompiler.tools.soda.opt import TransformedTask

project.set_flow(SODAASICFlow(strategy="transformed"))
TransformedTask.find_task(project).set_soda_schedule("my_schedule.mlir")
```

The support module the kernel is linked against is a knob too -- any C file whose
LLVM IR should end up inside the kernel goes here, and the module it produces is
named after it:

```python
from siliconcompiler.tools.mlir.compile import RuntimeTask
from siliconcompiler.tools.mlir.link import LinkTask

RuntimeTask.find_task(project).set_mlir_source("helpers.c")
# ...which the link step picks up as "the upstream module that is not the
# kernel", so it needs no name of its own. What it does need is the symbol
# that decides whether merging is worth it:
LinkTask.find_task(project).set_mlir_requiredsymbol("myHelper")
```

and the HLS step has its own:

```python
from siliconcompiler.tools.bambu.convert import ConvertTask as BambuConvertTask

bambu = BambuConvertTask.find_task(project)
bambu.set_bambu_memorychannels(2)
bambu.set_bambu_experimentalsetup("BAMBU-BALANCED-MP")
# Anything without a setter of its own still reaches the command line:
bambu.add_commandline_option("--max-sim-cycles=2000000")
```

The target supplies the rest. FreePDK45's Nangate45 library already carries
`--device=nangate45` for Bambu.


### Where to look when it fails

The front end fails in a small number of recognizable ways:

*The* `soda` *node emits nothing to outline.* The module reached it without a
kernel to find -- usually because `bufferize` did not produce linalg on
buffers. Read `bufferize/0/outputs/<top>.mlir`; if it still mentions `tosa.`
or `tensor<`, the lowering is what to fix.

*The kernel has the wrong name.* The `soda` node warns when the kernel it
outlined is not the design's topmodule. Rename the topmodule to match, or point
`set_soda_anchorfunc` at the function you meant.

*Bambu rejects the LLVM IR.* Look at `link/0/outputs/<top>.ll`. An unresolved
`memrefCopy` means the `runtime` node did not run or the `link` node
decided it was not needed; `translate`'s intrinsic strip covers the other
common case.

*A pass name is not recognized.* `soda-opt` and `mlir-opt` have to come from
the same llvm-project revision. `sc-install mlir` then `sc-install soda`, in
that order, is what keeps them in step.

*Bambu reports* `error: expected type` *on a* `ptr` *argument.* Its front-end
compiler is older than clang 16 and cannot read opaque pointers. See the install
note above; this is a property of the Bambu build, not of the design.

For the pass-by-pass view, turn on the IR dump -- verbose, but it is the only
practical way to see which pass broke a lowering:

```python
OptimizedTask.find_task(project).set_soda_printirafterall(True)
```


---

Source: https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/padring.html

## Implementing an IO pad ring

Every build in the other tutorials stops at a rectangle of standard cells. A part
you can put on a board needs more than that: it needs pads to bond to, supplies
that reach them, and a ring of cells around the edge tying the two together.

This tutorial builds one. The design is `examples/padring` -- a RISC-V
processor with an [SRAM](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-SRAM) inside a complete sky130 pad ring -- and it runs
to [GDSII](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-GDSII):

```bash
cd examples/padring
./padring.py
```

> **Note**
> This needs a local toolchain (Yosys, OpenROAD, OpenSTA and KLayout) and takes
> around ten minutes. The pad ring is generated by
> [lambdalib](https://github.com/siliconcompiler/lambdalib), which installs
> alongside `lambdapdk`, so there is nothing extra to fetch.


### What a ring is made of

Four things have to line up, and they live in different places:

| Piece | Where it lives |
| --- | --- |
| The pad cells | RTL. A dependency on lambdalib's generator, plus a `CELLMAP` saying which cell sits where on each side. |
| The interface | RTL. A top level whose ports *are* the pads. |
| Placement | A TCL script, attached to the floorplanning task. |
| Power | Two more TCL scripts: the grid, and the global connections that tie the core's supplies to the ring's. |


### The interface

The top level is the module that becomes the die, and its ports are the pads:

The die's pins

```verilog
module picorv32_top (
    // Supplies. Core and IO are separate domains.
    inout vdd,
    inout vss,
    inout vddio,
    inout vssio,

    // Clock and reset in.
    input clk,
    input resetn,

    // Processor status out.
    output trap,

    // Memory bus, brought out so the processor can be watched on a bench.
    output        mem_valid,
    output        mem_la_read,
    output        mem_la_write,
    output [ 3:0] mem_la_wstrb,
    output [29:0] mem_addr
);

```

Two conventions are worth copying. The ports are named for what they carry, not
for where they sit in the ring -- nobody debugging a board wants to work out
which bit of `no_pad` is the clock. And each one declares the direction it is
really used in: the cells in the ring are all bidirectional, but a pin on the
finished part is not, and only the supplies are genuinely `inout`.

Underneath, the logic never touches a pad cell. It drives four buses per side --
`dout` out, `din` back in, `oen` and `ie` for direction, and a
technology-specific configuration bus -- which is what lets the same processor be
wrapped in another technology's pads without editing it.


### Describing the ring

`CELLMAP` lists one side, cell by cell, in the order they abut. Each entry is
80 bits packing the cell type, the pin it carries, and its power section:

Four supplies then ten signal pads, per side

```verilog
    localparam [80*NCELLS-1:0] CELLMAP = {
        {16'h0000, 16'h0000, LA_VSS, 16'h0000, PIN_NONE},
        {16'h0000, 16'h0000, LA_VDD, 16'h0000, PIN_NONE},
        {16'h0000, 16'h0000, LA_VDDIO, 16'h0000, PIN_NONE},
        {16'h0000, 16'h0000, LA_VSSIO, 16'h0000, PIN_NONE},
        {16'h0000, 16'h0000, LA_BIDIR, 16'h0000, 16'd0},
        {16'h0000, 16'h0000, LA_BIDIR, 16'h0000, 16'd1},
        {16'h0000, 16'h0000, LA_BIDIR, 16'h0000, 16'd2},
        {16'h0000, 16'h0000, LA_BIDIR, 16'h0000, 16'd3},
        {16'h0000, 16'h0000, LA_BIDIR, 16'h0000, 16'd4},
        {16'h0000, 16'h0000, LA_BIDIR, 16'h0000, 16'd5},
        {16'h0000, 16'h0000, LA_BIDIR, 16'h0000, 16'd6},
        {16'h0000, 16'h0000, LA_BIDIR, 16'h0000, 16'd7},
        {16'h0000, 16'h0000, LA_BIDIR, 16'h0000, 16'd8},
        {16'h0000, 16'h0000, LA_BIDIR, 16'h0000, 16'd9}
    };

```

All four sides reuse this map here. A real part rarely has such tidy symmetry --
different sides carry different pin counts, and each gets its own map.


### Placing it

The RTL settled which cells exist. A TCL script settles where they go, and the
order of operations matters because each step depends on the last: make the IO
rows, place the pads into them, place the corners, fill the gaps, connect the
ring by abutment, then add the bond pads.

Pads go into rows in CELLMAP order

```tcl
# North and south run left to right; east and west are built bottom to top,
# so their declaration order is reversed relative to the row.
place_pads -row IO_NORTH {*}[padring_side_insts north]
place_pads -row IO_SOUTH {*}[padring_side_insts south]
place_pads -row IO_WEST {*}[lreverse [padring_side_insts west]]
place_pads -row IO_EAST {*}[lreverse [padring_side_insts east]]


```

`connect_by_abutment` is the step people miss. The supply rails and the
configuration signals pass between neighbouring cells through touching pins
rather than through routed wire, so it has to come *after* the fill has closed
the gaps -- otherwise the ring is a ring of islands.

> **Seealso**
> Every command in that script belongs to OpenROAD, not to SiliconCompiler, and
> each takes more arguments than this example uses. OpenROAD's
> [pad](https://openroad.readthedocs.io/en/latest/main/src/pad/README.html) module documents `make_io_sites`, `place_pads`,
> `place_corners`, `place_io_fill`, `connect_by_abutment` and
> `place_bondpad`; its [pdn](https://openroad.readthedocs.io/en/latest/main/src/pdn/README.html) module documents the power grid
> commands in the next section.


### Wiring it to the flow

None of those scripts do anything until a task is told to read them, and that
happens in two steps. First the design carries each script in a fileset of its
own -- `"padring.sky130"` and the two beside it are names this design invents,
not names SiliconCompiler looks for:

Three filesets, one per script

```python
        # Physical construction, kept in separate filesets so that a
        # different technology can supply its own without touching the RTL.
        with self.active_dataroot("padring"), self.active_fileset("padring.sky130"):
            self.add_file("openroad/padring.tcl")

        with self.active_dataroot("padring"), self.active_fileset("pdn.sky130"):
            self.add_file("openroad/pdn.tcl")

        with self.active_dataroot("padring"), self.active_fileset("globalconns.sky130"):
            self.add_file("openroad/global_connect.tcl")

```

Then the project hands those filesets to the tasks that read them. These are
task variables rather than schema keys, because each configures one step:

Attaching the physical filesets

```python
    InitFloorplanTask.find_task(project).add_openroad_padringfileset("padring.sky130")

    PowerGridTask.find_task(project).add_openroad_powergridfileset("padring", "pdn.sky130")

    for task in APRTask.find_task(project):
        task.add_openroad_globalconnectfileset("padring", "globalconns.sky130")

```

> **Important**
> The second block is the end of the setup, not the whole of it. Each line
> names a fileset that the first block created; on a design without them the
> three hooks point at nothing, and the tasks run as if no ring had been asked
> for.

> **Note**
> The pad ring hook takes only a fileset name, while the power grid and global
> connect hooks also take the library that owns the fileset. That is because a
> pad ring is always read from the design being built, while a power grid or a
> set of global connections often comes from a library instead: when neither is
> set explicitly, both tasks collect them from the ASIC libraries in the
> build. Set
> one here, as this design does, and that fallback no longer runs -- so a
> library's grid has to be named alongside the design's rather than inherited.

The power grid then needs one addition an ordinary design does not: the core's
rings are tied out to the supply pads with `-connect_to_pads`, so the core is
fed through the ring rather than through pins on the die edge.


### How big does the die have to be?

The ring sets a floor: fourteen cells plus two corners need about 1520 µm a side.
A die sized by that is **pad limited** -- set by how many pins must fit around the
edge rather than by the logic inside.

It also has to be set explicitly. `init_floorplan` refuses to size a die with a
ring in it from the usual density and aspect ratio, because the ring is placed at
absolute coordinates and a die chosen after the fact would not line up with it:

The die the ring is drawn against

```python
    project.constraint.area.set_dieoutline(1900, 1900, coremargin=250)

```

The memory fits inside that. sky130's SRAM macro is 683 µm wide and needs a
placement channel around it, which it has once the 250 µm margin holds the core
off the pads, so this die lands at 1900 µm.


### What to look at

Open the result with `project.show()`, or the GDS directly, and check the ring
before anything else:

The finished die. Ten signal pads and four supply pads on each side, corners
turning the ring, IO fill closing the gaps between cells, and bond pads over
the top. Inside, the SRAM macro is the wide block across the lower core and
the processor is the dense region above it.

- **Four populated sides.** The floorplan log reports what it placed --
  `Placed 14 pads in IO_NORTH` and so on. A ring that is missing pads on one
  side usually means the selection in the placement script stopped matching the
  instance names the RTL generates.
- **Continuous supplies.** The fill cells should leave no gaps, and the rails
  should run unbroken through the corners.
- **Bond pads** landing on the plate each pad cell carries, not merely
  somewhere over the cell -- a bond pad off the plate sits on the cell's
  keep-out and the power grid check reports it as a short.

> **Warning**
> This example stops short of a tapeout in one respect worth naming: the supply
> pads carry ESD clamp pins (`DRN_HVC`, `SRC_BDY_HVC`) which are left
> unconnected, and the power grid step says so. Where those clamps belong
> depends on the chip's ESD strategy and on foundry guidance, so the example
> does not guess. A real part has to resolve them.


### Next

- [Example designs](https://docs.siliconcompiler.com/en/latest/user_guide/examples.html#examples) -- the full source for this build.
- [How do I...?](https://docs.siliconcompiler.com/en/latest/user_guide/howto.html#howto) has the same steps in condensed form.
- [Instantiating a hardened module in a design](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/hardened.html#hardened-modules) covers
  macros inside the core, which is the other half of a floorplan like this one.


---

Source: https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/hardened.html

## Instantiating a hardened module in a design

Hardened modules allow predictable timing, efficient [placement](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-placement), and scalable hierarchical [ASIC](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-ASIC) design.

This tutorial demonstrates how to use Silicon Compiler to harden a [Verilog](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-Verilog) module as a reusable [macro](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-macro), and then instantiate it multiple times in another module by:

1. Setup design
2. [Synthesizing](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-synthesis), [placing](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-placement), and [routing](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-routing) **mod_and** using Silicon Compiler
3. Packaging the resulting layout and timing models from **mod_and** as a [hard macro](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-hard-macro)
4. Running the ASIC flow on module **top**

The module hardened here (**mod_and**) has no parameters. This tutorial does each
step by hand so the mechanism is explicit.

> **Seealso**
> If your module is **parameterized** and instantiated with several different
> parameter values, a hardened macro (which has no parameters) cannot bind to
> those instantiations directly. The [uniquify tutorial](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/uniquify.html#uniquify-modules)
> shows how [`Uniquified`](https://docs.siliconcompiler.com/en/latest/reference_manual/uniquify_api.html#siliconcompiler.tools.slang.utils.macro.Uniquified) automates this whole flow -- discovering the
> parameter values in use, generating a parameter-free hardenable variant for
> each parameterization plus one dispatching wrapper per module, and building
> and wiring them into the parent for you.

All these steps are contained in the [python script](https://github.com/siliconcompiler/siliconcompiler/blob/main/examples/macro_reuse/make.py).

To run this script from its containing folder:

```bash
smake build_top
```

or, on a machine with nothing installed but Docker, run the whole script inside
the image (see [Two ways to use the image](https://docs.siliconcompiler.com/en/latest/user_guide/docker.html#docker-two-ways) -- this is the
second one, not the Docker scheduler):

```bash
docker run --rm -v "$(pwd):/sc_work" \
    ghcr.io/siliconcompiler/sc_runner:latest \
    python3 make.py
```

The image output will appear in: `./build/top/job0/write.gds/0/outputs/top.png`


### Environment Setup

Import the modules to be used:

```python
from siliconcompiler import Design, ASIC, StdCellLibrary
from siliconcompiler.targets import skywater130_demo

```


### Files used


#### Child Module (and.v)

and.v

```verilog
module mod_and (
    input  wire       clk,
    input  wire [7:0] a,
    input  wire [7:0] b,
    output reg  [7:0] y
);

    always @(posedge clk) begin
        y <= a & b;
    end

endmodule

```


#### Parent Module (top.v)

top.v

```verilog
module top (
    input  wire       clk,
    input  wire [7:0] a1,
    input  wire [7:0] b1,
    input  wire [7:0] a2,
    input  wire [7:0] b2,
    output wire [7:0] y
);

    wire [7:0] d1;
    wire [7:0] d2;

    mod_and D1 (
        .clk(clk),
        .a  (a1),
        .b  (b1),
        .y  (d1)
    );
    mod_and D2 (
        .clk(clk),
        .a  (a2),
        .b  (b2),
        .y  (d2)
    );
    mod_and Y (
        .clk(clk),
        .a  (d1),
        .b  (d2),
        .y  (y)
    );
endmodule

```


### Step 1: Setup design

The following code will instantiate the module: **mod_and** and **top**:


#### Child Module (and.v)

Design setup for mod_and

```python
class And(Design):
    """
    Defines the child module (an AND gate).
    Inheriting from Design allows us to encapsulate file paths and module names.
    """
    def __init__(self):
        super().__init__("and")
        # Set the root directory for relative paths to this file's location
        self.set_dataroot("local", __file__)
        self.set_topmodule("mod_and", fileset="rtl")
        self.add_file("and.v", fileset="rtl")

```


#### Parent Module (top.v)

Design setup for top

```python
class Top(Design):
    """
    Defines the parent module (Top) which contains instances of the And gate.
    """
    def __init__(self):
        super().__init__("top")
        self.set_dataroot("local", __file__)
        self.set_topmodule("top", fileset="rtl")
        self.add_file("top.v", fileset="rtl")

        # Logically link 'And' so the linter/elaborator knows definitions exist.
        # Note: In the build_top() function, we will override this for physical implementation.
        self.add_depfileset(And(), depfileset="rtl", fileset="rtl")

```

Calling [`DependencySchema.write_depgraph()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.dependencyschema.DependencySchema.write_depgraph) on **top** draws what it now
depends on -- useful for checking that a module you expected to be linked in
actually is:


### Step 2: Synthesize, Place & Route module **mod_and**

The following code will build module **mod_and** with the default [ASIC](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/flows.html#schema-siliconcompiler-flows-asicflow-asicflow) flow.
This generates the physical layout required for the macro.

```python
def build_and() -> StdCellLibrary:
    """
    Hardens module 'And' and packages it as a library.

    Returns:
        StdCellLibrary: An object containing paths to the generated LEF, GDS, and LIB files.
    """

    project = ASIC(And())
    project.add_fileset("rtl")
    skywater130_demo(project)

    # Run the standard ASIC flow (Syn -> Floorplan -> Place -> Route -> Export)
    project.run()
    project.summary()

    # Create a reproducible snapshot of the build
    project.snapshot()


```


### Step 3: Packaging the resulting layout and timing models from **mod_and** as a hard macro

Once the flow is complete, we must package the results into a StdCellLibrary.
This object tells the tools where to find the physical views ([LEF](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-LEF)/[GDS](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-GDSII)) and timing views ([LIB](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-Liberty)) required by the parent design.
We gather the results from the previous build step and register them into the library object

```python
    # Packaging the Macro
    # Create a new library object to represent this hardened block
    library = StdCellLibrary("module_and")

    # Copy PDK name from the build project
    library.add_asic_pdk(project.get("asic", "pdk"))

    # Register Physical Views (GDS and Abstract)
    with library.active_fileset("models.physical"):
        # LEF: Abstract view for placement and routing in the parent
        library.add_file(project.find_result("lef", step="write.views"))
        # GDS: Actual layout for final merge
        library.add_file(project.find_result("gds", step="write.gds"))
        # Include necessary setup files for APR tools (like OpenROAD)
        library.add_asic_aprfileset()

    # Register Timing Views (Liberty files) for all available corners
    # This ensures the parent flow can perform timing analysis on the macro
    for corner in ("slow", "typical", "fast"):
        with library.active_fileset(f"models.timing.{corner}"):
            library.add_file(project.find_result(f"{corner}.lib", step="write.views"))
            library.add_asic_libcornerfileset(corner, "nldm")

    return library

```


### Step 4: Running the ASIC flow on module **top**

Finally, we configure the flow for the top module.
Critical steps here include:

1. **Blackboxing (Alias)**: We use add_alias to prevent the tool from synthesizing the RTL of And. We want to use the pre-hardened version, not re-synthesize it.
2. **Library Injection**: We use add_asiclib to provide the LEF and LIB files we packaged in Step 3.

```python
def build_top(size: int = 250, margin: int = 10):
    """
    Builds the top-level module using the pre-built 'And' library.
    """

    project = ASIC(Top())
    project.add_fileset('rtl')

    # Hierarchical Configuration
    # 1. 'add_alias': Tells the tool "When you see module 'And', do not compile its RTL."
    #    This effectively turns 'And' into a blackbox during synthesis.
    project.add_alias(And(), "rtl", None, None)

    # 2. 'add_asiclib': Injects the pre-built library (LEF/LIB) we created in build_and().
    #    The APR tool will use the LEF for placement and the LIB for timing.
    project.add_asiclib(build_and())

    # Load target technology
    skywater130_demo(project)

    # Constraints
    # Setting explicit die area is critical for macros.
    # If the core is too small, the placer may fail to fit the child macros.
    project.constraint.area.set_dieoutline(size, size, coremargin=margin)

    project.run()
    project.summary()
    project.snapshot()

```

> **Note**
> Setting the core and die area explicitly is crucial for macro placement.
> If the area is too small, the floorplan may fail to insert the macros.

```python
    project.constraint.area.set_dieoutline(size, size, coremargin=margin)

```


### Conclusion

This tutorial demonstrates how to perform a basic modular hierarchical [ASIC](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/flows.html#schema-siliconcompiler-flows-asicflow-asicflow) design flow in Silicon Compiler by:

- Hardening a leaf module **mod_and**
- Exporting the layout and timing views from **mod_and** as a custom library `module_and`
- Instantiating `module_and` in the parent module **top**

This approach enables scalable chip design with reusable hardened blocks.


---

Source: https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/uniquify.html

## Hardening parameterized modules (uniquify)

> **Note**
> **Beta feature.** Uniquify ([`Uniquified`](https://docs.siliconcompiler.com/en/latest/reference_manual/uniquify_api.html#siliconcompiler.tools.slang.utils.macro.Uniquified)) is new; its API and
> generated output may change in a future release.

The [hardened-module tutorial](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/hardened.html#hardened-modules) hardened a single,
*unparameterized* module and instantiated it in a parent -- packaging the
[macro](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-macro), [blackboxing](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-blackbox) the [RTL](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-RTL) and injecting the
library all by hand. This tutorial tackles
the case that flow cannot: a **parameterized** module instantiated with several
different parameter values.

> **Admonition**
> ## How this differs from the hardened-module tutorial
>
> The [hardened-module tutorial](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/hardened.html#hardened-modules) teaches the underlying
> *mechanism* -- harden a module, blackbox it, inject the macro -- by hand for
> one fixed module. If you have not read it, start there.
>
> This tutorial is about the problem that mechanism alone cannot solve. A
> [hardened macro](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-hardened-macro) is a fixed [netlist](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-netlist) with **no parameters**, so a post-synthesis
> block named `heartbeat` no longer has an `N` for a parent's
> `heartbeat #(.N(8))` to bind to -- and the parent uses `N` = 8, 24 *and*
> 48. [`Uniquified`](https://docs.siliconcompiler.com/en/latest/reference_manual/uniquify_api.html#siliconcompiler.tools.slang.utils.macro.Uniquified) resolves this automatically: it discovers which
> parameter values are actually used, generates a hardenable variant for each
> plus a wrapper that restores the original interface, and drives the whole
> harden-and-inject flow for every variant at once.

Given a design and the names of the parameterized modules to harden,
[`Uniquified`](https://docs.siliconcompiler.com/en/latest/reference_manual/uniquify_api.html#siliconcompiler.tools.slang.utils.macro.Uniquified):

1. **enumerates** every concrete parameter combination the modules are actually
  instantiated with (by elaborating the design with [slang](https://github.com/MikePopoloski/slang)),
2. **generates**, for each combination, a parameter-free *variant* to harden
  (e.g. `heartbeat__N8`) plus a parameterized *wrapper* that keeps the
  original module's name and interface and dispatches to the matching variant,
3. **registers** filesets for those sources on the design, then lets you
  **build** each variant into a macro and **wire up** the wrappers and macros
  into a parent [`ASIC`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.ASIC) project.

This mirrors how `lambdalib` maps an abstract cell onto hardened
implementations, but generated automatically from how the modules are used.

> **Note**
> Unparameterized modules are handled too. A module with no overridable
> parameters is already hardenable, so no wrapper is generated for it -- it is
> hardened directly and blackboxed at wireup, i.e. [`Uniquified`](https://docs.siliconcompiler.com/en/latest/reference_manual/uniquify_api.html#siliconcompiler.tools.slang.utils.macro.Uniquified) does
> exactly what the [hardened-module tutorial](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/hardened.html#hardened-modules) does by
> hand. A single [`Uniquified`](https://docs.siliconcompiler.com/en/latest/reference_manual/uniquify_api.html#siliconcompiler.tools.slang.utils.macro.Uniquified) can therefore harden a mix of
> parameterized and unparameterized modules in one shot.

All of the code below is contained in the
[example script](https://github.com/siliconcompiler/siliconcompiler/blob/main/examples/uniquify/uniquify.py).
To inspect what uniquify generates (no EDA tools required):

```bash
smake main
```

and to run the full flow (requires yosys and OpenROAD):

```bash
smake harden
```


### The design

The parent instantiates a parameterized `heartbeat` counter with several
distinct widths (`N`), plus a `prescaler`. Note that `N=24` is used twice
-- uniquify hardens it only once.

heartbeat_top.v

```verilog
// Parent design. It depends on the parameterized `heartbeat` and `prescaler`
// modules (each defined in its own file / SiliconCompiler Design) and
// instantiates them with several distinct parameter values.
module heartbeat_top (
    input        clk,
    input        nreset,
    output       out_fast,
    output       out_slow,
    output       out_slow2,
    output       out_slowest,
    output [3:0] cnt_a,
    output [7:0] cnt_b
);
    // Four heartbeat instances, three distinct parameterizations (N=24 merges).
    heartbeat #(
        .N(8)
    ) u_fast (
        .clk(clk),
        .nreset(nreset),
        .out(out_fast)
    );
    heartbeat #(
        .N(24)
    ) u_slow (
        .clk(clk),
        .nreset(nreset),
        .out(out_slow)
    );
    heartbeat #(
        .N(24)
    ) u_slow2 (
        .clk(clk),
        .nreset(nreset),
        .out(out_slow2)
    );
    heartbeat #(
        .N(48)
    ) u_slowest (
        .clk(clk),
        .nreset(nreset),
        .out(out_slowest)
    );

    // Two prescaler parameterizations.
    prescaler #(
        .W(4)
    ) u_ps4 (
        .clk(clk),
        .nreset(nreset),
        .count(cnt_a)
    );
    prescaler #(
        .W(8)
    ) u_ps8 (
        .clk(clk),
        .nreset(nreset),
        .count(cnt_b)
    );
endmodule

```

heartbeat.v

```verilog
// A parameterized module, instantiated with several distinct N values by the
// parent. Hardening it requires knowing which concrete N values are actually
// used -- that is what the uniquify enumeration answers.
module heartbeat #(
    parameter N = 8
) (
    input      clk,
    input      nreset,
    output reg out
);
    reg [N-1:0] counter_reg;
    always @(posedge clk or negedge nreset) begin
        if (!nreset) begin
            counter_reg <= {(N) {1'b0}};
            out <= 1'b0;
        end else begin
            counter_reg <= counter_reg + 1'b1;
            out <= (counter_reg == {(N) {1'b1}});
        end
    end
endmodule

```


### Step 1: Define the modules and the parent

Each parameterized module to be hardened must be its own reusable
[`Design`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Design) (uniquify aliases the module's RTL to a generated wrapper, so it
needs a design to alias). The parent depends on their RTL so it elaborates.

The parameterized modules

```python
class Heartbeat(Design):
    """Parameterized `heartbeat` module (its own reusable design)."""
    def __init__(self):
        super().__init__("heartbeat")
        self.set_dataroot(_DATAROOT, __file__)
        with self.active_fileset("rtl"), self.active_dataroot(_DATAROOT):
            self.set_topmodule("heartbeat")
            self.add_file("heartbeat.v")


class Prescaler(Design):
    """Parameterized `prescaler` module (its own reusable design)."""
    def __init__(self):
        super().__init__("prescaler")
        self.set_dataroot(_DATAROOT, __file__)
        with self.active_fileset("rtl"), self.active_dataroot(_DATAROOT):
            self.set_topmodule("prescaler")
            self.add_file("prescaler.v")



```

The parent design

```python
class HeartbeatTop(Design):
    """Parent design instantiating the parameterized submodules."""
    def __init__(self):
        super().__init__("heartbeat_top")
        self.set_dataroot(_DATAROOT, __file__)
        with self.active_fileset("rtl"), self.active_dataroot(_DATAROOT):
            self.set_topmodule("heartbeat_top")
            # The parent depends on the submodule RTL so it elaborates.
            self.add_file("heartbeat_top.v")
            self.add_depfileset(Heartbeat(), depfileset="rtl", fileset="rtl")
            self.add_depfileset(Prescaler(), depfileset="rtl", fileset="rtl")

```


### Step 2: Construct the `Uniquified` helper

Pass the parent design (or a [`Project`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.project.Project)) and the module names to
uniquify. Construction enumerates the parameter combinations and generates the
wrappers/variants **in memory** -- it writes nothing to disk and runs no tools --
and registers the new filesets on the design.

Setting up uniquification

```python
def uniquify():
    """Set up uniquification of the target modules on a fresh parent design.

    Uniquify both parameterized submodules at once (each variant name is prefixed
    with its module). Returns the :class:`Uniquified` handle: the wrapper/variant
    filesets are registered on the design, but nothing is hardened yet.
    """
    return Uniquified(HeartbeatTop(), ["heartbeat", "prescaler"])

```

The filesets registered on the design are:

- `rtl.<module>.wrapper` -- the parameterized wrapper (keeps the module's name
  and interface), one per module.
- `rtl.hardened.<variant>` -- one parameter-free variant per combination, the
  top that gets hardened into a macro.
- `rtl.wrapper` -- an aggregate that pulls every per-module wrapper at once.


### Step 3: Inspect what was generated

The helper exposes its results as plain state. The `main` function prints the
variants and fileset names, then writes the sources so you can read a wrapper:

Inspecting the results

```python
def main():
    uq = uniquify()

    for module, variants in uq.variants.items():
        print(f"'{module}' -> {len(variants)} variant(s): {variants}")
    print()
    print("wrapper filesets:  ", uq.wrapper_filesets)
    print("hardened filesets: ", uq.hardened_filesets)

    # Materialize the generated sources (construction is disk-side-effect free),
    # then show one wrapper: it keeps the module name + parameters and dispatches
    # to the hardened variants.
    uq.write()
    with open(os.path.join(uq.outdir, "heartbeat.wrapper.v")) as fobj:
        print("\n" + "=" * 64 + "\nGenerated wrapper for 'heartbeat':\n")
        print(fobj.read())

```

For this design that reports three `heartbeat` variants (`N` = 8, 24, 48 --
the duplicate `N=24` merged) and two `prescaler` variants:

```text
'heartbeat' -> 3 variant(s): ['heartbeat__N24', 'heartbeat__N48', 'heartbeat__N8']
'prescaler' -> 2 variant(s): ['prescaler__W4', 'prescaler__W8']
```

The generated wrapper keeps the `heartbeat` name and its `N` parameter, and
uses a `generate` block to select the matching hardened variant. If a design
ever requests a parameter combination that was not hardened,
[elaboration](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-elaboration) fails
loudly via `$error` rather than silently building the wrong thing:

heartbeat.wrapper.v (generated)

```verilog
module heartbeat #(
    parameter N = 8
) (
    input      clk,
    input      nreset,
    output out
);
    generate
        if ((N == 24)) begin : g_heartbeat__N24
            heartbeat__N24 u_impl (.clk(clk), .nreset(nreset), .out(out));
        end
        else if ((N == 48)) begin : g_heartbeat__N48
            heartbeat__N48 u_impl (.clk(clk), .nreset(nreset), .out(out));
        end
        else if ((N == 8)) begin : g_heartbeat__N8
            heartbeat__N8 u_impl (.clk(clk), .nreset(nreset), .out(out));
        end
        else begin : g_invalid
            $error("no hardened variant of heartbeat exists for the requested parameters");
        end
    endgenerate
endmodule
```


### Step 4: Harden the variants

[`Uniquified.build()`](https://docs.siliconcompiler.com/en/latest/reference_manual/uniquify_api.html#siliconcompiler.tools.slang.utils.macro.Uniquified.build) hardens the selected variants (all of them by default)
into [`StdCellLibrary`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.StdCellLibrary) macros. Pass a `target` -- a SiliconCompiler
target callback `fn(project)` that configures the PDK, flow and constraints on
each variant's ASIC run -- exactly as you would for a normal build:

The target used for each variant (and the parent)

```python
def _configure_freepdk45(project):
    """Configure a variant/parent ASIC run for FreePDK45."""
    from siliconcompiler.targets import freepdk45_demo
    from siliconcompiler.tools.openroad._apr import OpenROADPSMParameter

    freepdk45_demo(project)
    project.constraint.area.set_density(5.0)
    # The demo PDK has no power grid; skip IR-drop analysis.
    for task in OpenROADPSMParameter.find_task(project):
        task.set_openroad_psmenable(False)

```

Hardening every variant

```python
    uq.build(target=_configure_freepdk45, parallel=True)

```

Each variant is built under its own job (`jobname=<variant>`) beneath the
helper's `libdir`, and the resulting macro is persisted so a later run reuses
it. `build` returns a `{variant: StdCellLibrary}` mapping. Pass
`parallel=True` to harden the variants concurrently, or `macros="heartbeat"`
/ `macros="heartbeat__N*"` to rebuild a subset.


### Step 5: Wire up the parent

Finally, build the parent. This is where the mechanism from the
[hardened-module tutorial](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/hardened.html#hardened-modules) -- alias the module's RTL,
inject the macro with `add_asiclib` -- is applied, but you do not write it out
by hand: [`Uniquified.wireup()`](https://docs.siliconcompiler.com/en/latest/reference_manual/uniquify_api.html#siliconcompiler.tools.slang.utils.macro.Uniquified.wireup) does it for every variant at once. It aliases
each module's RTL to its generated *wrapper* (so synthesis elaborates the
dispatch instead of the original parameterized RTL, the one twist beyond the
hardened-module flow) and injects all the hardened macros:

Building the parent with the wrappers and macros

```python
def harden():
    """Full flow: harden every variant and build the parent with the macros.

    Requires EDA tools (yosys/OpenROAD).
    """
    uq = uniquify()
    uq.build(target=_configure_freepdk45, parallel=True)

    project = ASIC(uq.design)
    project.add_fileset("rtl")
    _configure_freepdk45(project)
    uq.wireup(project)

    project.run()
    project.summary()

```

> **Note**
> `wireup` requires every used variant to have a built (or loaded) macro, and
> raises otherwise. The generated wrapper has a branch for each *enumerated*
> variant, so an unbuilt-but-used variant still matches its own branch (it does
> not reach the `$error` default) -- what fails is the missing hardened
> implementation. The `$error` branch only guards parameter combinations that
> were never enumerated at all. Call [`Uniquified.build()`](https://docs.siliconcompiler.com/en/latest/reference_manual/uniquify_api.html#siliconcompiler.tools.slang.utils.macro.Uniquified.build) first, or
> [`Uniquified.load_macros()`](https://docs.siliconcompiler.com/en/latest/reference_manual/uniquify_api.html#siliconcompiler.tools.slang.utils.macro.Uniquified.load_macros) to reuse macros from a previous run.


### Conclusion

Starting from a parent that instantiates a parameterized module with several
different parameter values, uniquify:

- discovered the concrete parameterizations in use,
- generated a hardenable variant for each and a parameterized wrapper to
  dispatch to them,
- hardened the variants into reusable macros, and
- wired the wrappers and macros into the parent build.

See the [Uniquify API](https://docs.siliconcompiler.com/en/latest/reference_manual/uniquify_api.html#uniquify-api) for the full class reference.


---

Source: https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/pex_calibration.html

## Calibrating the parasitic estimate (PEX)

Before it routes a design, OpenROAD *estimates* every net's parasitics from a
small per-layer resistance/capacitance model -- the [PDK](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-PDK) `rclayer`
values fed to `set_layer_rc`. That estimate drives every timing-repair
decision in [place-and-route](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-place-and-route), yet it is only a model, and a PDK ships
with it hand-tuned (or missing). This tutorial shows how to build that model,
and a correction on top of it, **directly from the PDK's OpenRCX
:term:`signoff` deck** using the `pex_calibrate` utility, so the
[routing](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-routing) layers no longer need hand tuning.
(Vias and any layer the bench cannot reproduce still come from whatever the PDK
already prescribes -- see the note below.)

> **Admonition**
> ## Who this is for / prerequisites
>
> This is an advanced, PDK-owner-facing tutorial. It assumes you are
> comfortable with parasitic extraction and signoff (OpenRCX decks,
> [SPEF](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-SPEF)), per-layer R/C models and `set_layer_rc`, PDK process
> [corners](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-corner), and the
> difference between global-route and detailed-route wirelength. You also need:
>
> - a target whose PDK ships an OpenRCX deck
>   (`pdk.add_pexmodelfileset("openroad", ...)` with an `openrcx` file --
>   see [Defining a Process Design Kit (PDK)](https://docs.siliconcompiler.com/en/latest/development_guide/pdks.html#dev-pdks)),
> - a working OpenROAD [ASIC](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-ASIC) flow for that target (the survey routes real
>   designs end to end), and
> - OpenROAD **26Q3-23 or newer**. Both extraction tasks select the deck with
>   `set_extraction_rules_file` and the calibration walks parasitics through
>   the multi-corner [STA](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-STA) scene API; the tasks declare this floor, so an older
>   install is rejected up front rather than failing mid-run.
>
> If you only want to *use* a PDK that is already calibrated, you do not need
> this tutorial: the corrections are applied automatically once a PDK owner
> commits them.

The tool works in two phases:

1. **Initial model** -- `bench_wires` builds synthetic wire patterns from the
  tech, extracts them with the OpenRCX deck, and walks the per-segment
  parasitics into a per-layer resistance/capacitance model. One model is
  produced for every corner the PDK ships a deck for. These seed
  `pdk.add_openroad_rclayer(...)`.
2. **Correction factors** -- a small survey of designs is routed; on each routed
  database the *real* per-layer capacitance is measured (again by extracting
  with the deck and walking segments), pooled across designs, and divided by
  the initial per-layer capacitance to give one `cap_factor` per layer. These
  seed `pdk.add_openroad_rccorrection(...)`.

> **Note**
> The correction is a *pooled ratio* of capacitance **per unit wire length**,
> summed over all nets of all survey designs. Because it is per-unit-length, it
> is far more a property of the **process** than of any one design: a bigger or
> busier design contributes more wire to the same ratio rather than shifting it.
> It is not literally survey-independent -- layers a design barely routes on
> contribute little, so lightly-used upper layers stay noisy -- so add designs
> until the factors on the layers you care about stop moving.


### Quick start

Run the calibration on FreePDK45 using the bundled demo survey (`gcd`,
`picorv32`, `aes` and `jpeg`):

```bash
python -m siliconcompiler.tools.openroad.utils.pex_calibrate freepdk45_demo -o pex
```

The demo designs are not vendored into the package; their RTL is fetched from
pinned git sources (the scgallery repo, and upstream for `picorv32`) and
cached under `~/.sc` on first use - so the first run needs network access,
later runs do not. There is no dependency on the scgallery *package*.

The tool prints the lines to paste into a PDK setup:

```text
# Initial PEX estimate model for corner 'typical' (from bench_wires); res in ohm/um, cap in F/um
pdk.add_openroad_rclayer("typical", "routing", "metal2", 3.5714, 1.19382e-16)
pdk.add_openroad_rclayer("typical", "routing", "metal3", 3.5714, 1.55445e-16)
...
# Calibrated PEX corrections for corner 'typical'
pdk.add_openroad_rccorrection("typical", "metal2", cap_factor=0.6960)
pdk.add_openroad_rccorrection("typical", "metal3", cap_factor=0.6412)
...
```

and writes two CSV data files under `-o` (here `./pex/`):

- `freepdk45.rclayer.csv` -- the initial per-layer model (one row per
  corner/layer).
- `freepdk45.rccorr.csv` -- the correction factors (one row per corner/layer).

The target argument is resolved to a target setup function, and the PDK name is
derived from it automatically -- you do not name the PDK or the corners. A bare
name is looked up under `siliconcompiler.targets` (`freepdk45_demo` ->
`siliconcompiler.targets.freepdk45_demo`); a `module:function` or
`module.function` path also works for a custom target.

> **Note**
> The segment walk characterizes routing layers only, so anything the bench
> cannot reproduce -- **vias**, and any layer absent from the routing tech LEF
> (for example a thick top metal such as gf180's `MetalTop`) -- is **carried
> over from the PDK's existing** `rclayer` **verbatim** and marked in both the
> printed output and the `source` column of `<pdk>.rclayer.csv`:
>
> ```
> pdk.add_openroad_rclayer("typ", "via", "Via1", 5.3)  # preserved from PDK (not characterized by OpenRCX)
> ```
>
> So a layer the tool cannot measure is never dropped or zeroed; it keeps
> whatever the PDK already prescribed.


### Reusing the results (no rerun)

The two CSV files *are* the calibration. Running the tool again with the files
already present just reprints the lines -- it does **not** rerun the flows:

```bash
# instant: reads pex/*.csv and reprints the PDK lines
python -m siliconcompiler.tools.openroad.utils.pex_calibrate freepdk45_demo -o pex

# or, explicitly print-only (errors if the files are missing)
python -m siliconcompiler.tools.openroad.utils.pex_calibrate freepdk45_demo -o pex --print
```

Each phase reuses its own file independently, so if only the initial model was
produced, a later run completes just the survey. To recompute from scratch:

```bash
python -m siliconcompiler.tools.openroad.utils.pex_calibrate freepdk45_demo -o pex --rerun
```

> **Warning**
> The cache is keyed on the **PDK name only** -- it does not know which designs
> produced it. So after **changing the survey** (adding a design, editing one)
> you must pass `--rerun`, or delete `<pdk>.rccorr.csv`; otherwise the tool
> reuses the previous survey's factors and the numbers will look identical for
> the wrong reason. This matters most for the "add designs until the factors stop
> moving" workflow below. The tool prints a note whenever it reuses the file.


### Applying the calibration

Copy both blocks of emitted lines into your PDK setup (the PDK owner commits
them as policy). The `add_openroad_rclayer` lines are the estimate model; the
`add_openroad_rccorrection` lines scale its capacitance toward signoff:

```python
pdk.add_openroad_rclayer("typical", "routing", "metal2", 3.5714, 1.19382e-16)
pdk.add_openroad_rccorrection("typical", "metal2", cap_factor=0.6960)
```

> **Important**
> The two blocks are **one calibration** -- paste both, and replace the PDK's
> existing `rclayer` for the benched layers rather than adding to it. A
> `cap_factor` is the ratio of measured capacitance to *the bench value
> printed beside it*, so applying it on top of a different (for example
> hand-tuned) `rclayer` scales the wrong baseline and can be worse than no
> correction at all. Conversely, pasting the new `rclayer` without the
> corrections leaves the estimate at the uncorrected bench value. Re-run the
> tool whenever you change either block. Lines marked `# preserved from PDK`
> are your existing values echoed back unchanged, so the emitted block is a
> complete picture of the PDK's `rclayer` -- if you would rather re-seed from
> scratch, `pdk.unset_openroad_rclayer()` clears it first.

Every place-and-route node then estimates parasitics through this corrected
model. A layer with no correction entry is left unchanged, so an empty
correction is identical to running without one; a correction naming a layer with
no `rclayer` entry is ignored, and OpenROAD warns about it so a misspelled
layer name is not silent. To run a node against the raw, uncalibrated estimate
without editing the PDK, call `set_openroad_applypexcorrection(False)` on the
place-and-route task. During the derivation survey the
PDK carries no correction, so the `calibrate` node measures the *uncorrected*
estimate the factor is derived from. The bench models every corner the deck
ships, but the survey only calibrates the corners wired into a timing
[scenario](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-scenario);
the calibration step warns about any modeled corner it does not cover, so a
corner that will keep the uncalibrated estimate is not a silent surprise.


### Quantifying the improvement

The two CSVs *are* the calibration; the `--score` flag additionally
**measures** what they buy. It re-routes the survey twice -- once uncorrected,
once with the derived correction applied to the whole flow -- and reports the
per-net estimate error against the golden extraction, before and after:

```bash
python -m siliconcompiler.tools.openroad.utils.pex_calibrate freepdk45_demo --score
```

```text
PEX estimate error vs golden -- |est - golden| / golden over signal/clock nets:
corner       metric     before     after    change
--------------------------------------------------
typical      median      31.2%     12.4%    -18.8%
typical      p90         58.0%     24.1%    -33.9%
typical      mean        34.5%     15.0%    -19.5%
```

Each row is the per-net relative gap between OpenROAD's pre-route estimate and
the OpenRCX golden extraction, so a smaller *after* number means the calibrated
estimate tracks signoff more closely. The exact numbers depend on the survey
designs and the PDK (the illustrative values above are not a guarantee).

Two caveats on reading this table. It is an **in-sample** measurement: the same
designs that produced the factors are being scored, so it reports how well the
per-layer model fits the survey, not how it generalises -- hold a design out of
`--design` and score it separately if you want that. And the *remaining* error
is not attributed by the tool; the wirelength difference described below is the
expected dominant contributor, but the table does not decompose it.

This is an opt-in diagnostic: it roughly doubles the survey work (an extra routed
pass per design), so it is for *validating* a calibration, not for every run.


### Calibrating your own PDK

Point the tool at your target and (optionally) your own survey designs. Corners
are discovered automatically: an initial model is produced for **every** corner
the PDK ships an OpenRCX deck for, and a correction factor for every corner your
target wires into a timing scenario (routing and timing need a scenario).

From the command line, each `--design` is a directory holding `<name>.v`
(and optionally `<name>.sdc`):

```bash
python -m siliconcompiler.tools.openroad.utils.pex_calibrate my_pkg.targets:my_target \
    --design designs/aes --design designs/jpeg -o pex
```

From Python you pass [`Design`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Design) objects, which lets you build the survey
designs however you like (multiple sources, include dirs, remote dataroots)
rather than relying on the `<name>.v` layout `--design` assumes. The survey
consumes the `rtl` fileset, plus `sdc` when the design has one:

```python
from siliconcompiler import Design
from siliconcompiler.tools.openroad.utils import pex_calibrate

designs = [
    pex_calibrate.design_from_dir("designs/aes"),
    pex_calibrate.design_from_dir("designs/jpeg"),
]
# calibrate() prints the paste-able PDK lines at the end and also returns
# them as data for further processing.
model, factors = pex_calibrate.calibrate("my_pkg.targets:my_target",
                                         designs=designs, outdir="pex")
```

Guidance for the survey:

- Add designs until the factors stop moving -- passing `--rerun` each time, or
  the cached factors come straight back (see the warning above). A handful of
  medium designs is usually enough. The upper metal layers need designs that
  actually route on them, or their factors stay noisy; the `nseg` column of
  `<pdk>.rccorr.csv` is the per-layer sample count to judge that by.
- Your PDK must ship an OpenRCX deck
  (`pdk.add_pexmodelfileset("openroad", ...)` with an `openrcx` file) -- it
  is the golden reference for both phases. A deck is needed for every corner a
  timing scenario names: a scenario pointing at a corner with no deck fails
  setup rather than being quietly dropped from the calibration.


### What gets calibrated (and what does not)

The estimate error has two independent parts:

1. **Per-layer capacitance model** -- capacitance per unit wire length on each
  layer. This is essentially a property of the process, and it is what the
  calibration corrects. The resistance already reproduces the deck, so only
  `cap_factor` is prescribed; the resistance ratio is written to the CSV as a
  ~1.0 sanity check and is never applied.
2. **Wirelength** -- the estimate uses the *global-route* wirelength, which
  differs from the final *detailed-route* wirelength. This gap is
  design-density-dependent (a sparse design and a dense one differ even in
  sign), so it is **not** something a single per-layer factor can fix, and the
  tool deliberately does not try. Chasing it would produce a different factor
  for every design -- which is not a calibration.

So the calibration makes the per-layer capacitance model match signoff; the
residual per-net total-capacitance gap is expected to be dominated by the
wirelength difference and is out of scope.

> **Note**
> The correction is derived from, and scored against, the *global-route*
> estimate (`estimate_parasitics -global_routing` on the routed database).
> Earlier place-and-route nodes -- global placement, repair, detailed placement
> -- estimate from placement instead (`-placement`), which uses a Steiner
> wirelength model. Both consume the same corrected `set_layer_rc` values, so
> both benefit from a better per-unit-length capacitance; only the wirelength
> half of the error differs between them, and that half is out of scope either
> way.

> **Note**
> The survey routes **untimed** by default -- a design's `sdc` fileset is used
> only when it ships one, and no clock is required. Adding a clock (clock-tree
> synthesis, timing-driven placement, timing repair) does add wiring, but
> `cap_factor` is a *per-unit-length* quantity, so the extra wiring does not
> move it. Measured across this survey, constraining the designs shifts the
> pooled factor by well under 1% on the layers that carry essentially all the
> routing; the only larger movement is on the top one or two layers, which are
> too lightly used to calibrate reliably either way. Timing the survey is
> therefore not worth the extra runtime.

> **Note**
> The demo survey (`gcd`, `picorv32`, `aes`, `jpeg` on FreePDK45) is a
> small illustrative sample, so the upper-layer factors are still somewhat noisy.
> On this PDK the `cap_factor` comes out below 1.0: the `bench_wires`
> pattern set runs at tighter effective coupling than real routing does, so it
> over-predicts capacitance per unit length and the survey de-rates it. That
> direction is an observation about the pattern set, not a guarantee -- read the
> sign of your own factors rather than assuming it. The demo exists to exercise
> the flow end to end; a production calibration wants a representative sample of
> your own designs.


### How it works

- `GeneratePEXEstimateFlow` (`siliconcompiler.flows.openroad_pex`):
  `bench` (`bench_wires` -> pattern DEF) -> `extract` (re-read the DEF in a
  fresh process, extract with the deck, walk segments -> per-layer R/C). It runs
  on a dummy `openroad_bench` design so the bench job stays out of a real
  design's build directory, and it needs no design of its own -- only the tech
  [LEF](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-LEF) and the OpenRCX deck.
- `PEXCalibrateFlow` (`siliconcompiler.flows.openroad_pex`): the core ASIC
  flow ([synthesis](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-synthesis) through routing) with a `calibrate` node in place of
  the view/[GDS](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-GDSII) write. The `calibrate` node records the pre-route estimate per net,
  then extracts the golden reference (`extract_parasitics -max_res 0
  -no_merge_via_res`) and walks the per-segment parasitics into per-layer
  capacitance and length.

Walking single-layer segments is what makes the per-layer capacitance
measurable directly (`C = ΣC / Σlength` per layer) -- a merged/reduced SPEF has
already thrown that per-segment layer detail away, which is why both flows
re-extract rather than reading a signoff SPEF.

> **Seealso**
> `examples/pex_calibration/calibrate.py` -- a runnable thin wrapper around
> `siliconcompiler.tools.openroad.utils.pex_calibrate.calibrate` for the
> FreePDK45 demo.


---

Source: https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/multi_job_flows.html

## Multi-Job Flows and Automation

[Compilation process](https://docs.siliconcompiler.com/en/latest/user_guide/execution_model.html#execution-model) describes setting up one job. This
tutorial covers what happens when one `run()` is not enough: chaining a second
flow onto the results of the first, sweeping a parameter across many jobs, and
building a design hierarchically.

All three rest on the same mechanism -- **job history** -- so it is worth
understanding that first.


### Job History

Every [`Project.run()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.project.Project.run) copies the finished project state into a history
record keyed by [`[option,jobname]`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-project-option-jobname), and [`Project.history()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.project.Project.history) reads it
back:

```python
project.option.set_jobname("baseline")
project.run()

# Change something, or the second run just reproduces the first.
project.option.set_optmode(3)             # optimize harder
project.option.set_jobname("tuned")
project.run()

before = project.history("baseline").get("metric", "cellarea",
                                         step="synthesis", index="0")
after = project.history("tuned").get("metric", "cellarea",
                                     step="synthesis", index="0")
```

Three properties of the record are worth knowing, because they decide how you
structure a script:

- **Keyed by jobname.** Give each run a distinct name or you cannot tell the
  results apart. Reusing one replaces the earlier record and logs
  `Overwriting job <name>`.
- **Recorded even when the run fails.** The history is written in a `finally`
  block, so a job that errored is still queryable -- which is what makes it
  usable for automation that has to cope with failures.
- **A full project, not just metrics.** `history()` returns a
  [`Project`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.project.Project), so anything readable on a live project is readable on a
  past one.


### Pattern 1: Chaining Flows

Run one flow, then feed its outputs into another as inputs. The canonical case is
implementation followed by signoff, because they are different flows over the
same design.

[`Project.find_result()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.project.Project.find_result) locates an output by extension and step, which is
what lets the second job pick up where the first left off:

```python

# After the first run, we find the paths to the output GDSII and netlist files...
# ...and add them to a new 'layout' fileset. These files will be the
# *inputs* for our next signoff step.
with design.active_fileset("layout"):
    design.set_topmodule("gcd")
    design.add_file(project.find_result('gds', step='write.gds'))
    design.add_file(project.find_result('vg', step='write.views'))

# Add the new 'layout' fileset to the project for the next run.
# `clobber=True` ensures it overwrites the fileset if it already exists.
project.add_fileset("layout", clobber=True)

# Explicitly switch the project's flow to `SignoffFlow`, a pre-built flow
# designed for running DRC and LVS checks on a layout.
project.set_flow(SignoffFlow())

# Set a unique name for this job run.
project.option.set_jobname("signoff")

# Execute the signoff flow.
project.run()


```

Note the three moving parts: a **new fileset** holding the previous job's
outputs, `clobber=True` so it replaces rather than appends on a re-run, and a
**new jobname** so the signoff results do not overwrite the implementation
record.

Full example:
[examples/gcd/gcd_skywater.py](https://github.com/siliconcompiler/siliconcompiler/blob/main/examples/gcd/gcd_skywater.py).


### Pattern 2: Sweeping a Parameter

Run the same flow many times with one thing changed, then compare.

Carry each variant as its own [fileset](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-fileset) and give each run its own jobname:

```python
for n in datawidths:
    # Add the corresponding RTL fileset to the project for this run.
    # 'clobber=True' ensures we replace the fileset from the previous iteration.
    proj.add_fileset(f"rtl.{n}", clobber=True)
    # Set a unique jobname for each run. This helps in organizing the results
    # and retrieving metrics from the correct run later.
    proj.option.set_jobname(f"N{n}")

    # Execute the synthesis flow.
    proj.run()

    # After the run, retrieve the 'cellarea' metric from the 'synthesis' step.
    # We use the jobname to access the history of the specific run we just completed.
    area.append(proj.history(f"N{n}").get('metric', 'cellarea', step='synthesis', index='0'))


```

The loop body is the whole pattern: swap the fileset, name the job, run, read the
metric back out of history.

Full example:
[examples/oh_experiments/adder_sweep.py](https://github.com/siliconcompiler/siliconcompiler/blob/main/examples/oh_experiments/adder_sweep.py).
[check_area.py](https://github.com/siliconcompiler/siliconcompiler/blob/main/examples/oh_experiments/check_area.py)
in the same directory is the variant that builds a **fresh project per run**
instead of reusing one -- worth preferring when the runs differ in more than one
setting, since it removes any chance of state leaking between them.

> **Seealso**
> Sweeps are also the natural place to add parallelism: the jobs are
> independent, so they can run at the same time.
> [Parallel Job Execution](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/parallel.html#parallel-execution) covers how.


### Pattern 3: Hierarchical Builds

Build a block in one job, then consume its results in another. This is the
multi-job structure behind hardened macros: the child is implemented, packaged as
a library, and injected into the parent, which never sees its RTL.

```python
library = build_and()          # job 1: implement the child, package the views

project = ASIC(Top())
project.add_alias(And(), "rtl", None, None)   # blackbox the child's RTL
project.add_asiclib(library)                  # inject its LEF/LIB
project.run()                                 # job 2: implement the parent
```

[Instantiating a hardened module](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/hardened.html#hardened-modules) works this through end
to end, and [Hardening parameterized modules](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/uniquify.html#uniquify-modules) automates
it across every parameterization of a module.


### Putting It Together

The three patterns compose into flows that no single flowgraph can express,
because the decisions between jobs are ordinary Python:

Read it as an alternation. SiliconCompiler runs a job (grey); your script reads
the result and decides what to run next (yellow); repeat. A synthesis job fans
out into one implementation job per configuration, your code compares them, and
either proceeds to signoff or adjusts and re-runs.

The flowgraph handles what is static -- the steps inside a job, and the edges
between them. Your script handles what depends on a result, because that is not
something a static graph can express.

> **Seealso**
> - [Parallel Job Execution](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/parallel.html#parallel-execution) -- running the jobs above
>   concurrently.
> - [Working with Metrics](https://docs.siliconcompiler.com/en/latest/development_guide/metrics.html#dev-metrics) -- what is available to compare.
> - [Directory structures](https://docs.siliconcompiler.com/en/latest/user_guide/directories.html#build-directory) -- where each job's outputs
>   land.


---

Source: https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/parallel.html

## Parallel Job Execution

Single-threaded performance has saturated, so making hardware compilation fast
means making effective use of parallel hardware. Two things work in our favour:
the compute-to-data ratio of the expensive compilation steps is high, and several
of those steps partition into embarrassingly parallel problems.

This tutorial runs one workload three ways -- synthesizing the same adder at four
datawidths -- and shows where the parallelism comes from in each. The code is a
single script:

- [examples/parallel/parallel.py](https://github.com/siliconcompiler/siliconcompiler/blob/main/examples/parallel/parallel.py)
- [examples/parallel/adder.v](https://github.com/siliconcompiler/siliconcompiler/blob/main/examples/parallel/adder.v)

```bash
./parallel.py serial
./parallel.py indexed
./parallel.py processes
```

Each prints its own wall-clock time. `serial` and `processes` run identical
work and differ only in how it is scheduled, so those two compare directly.
`indexed` is not a like-for-like third measurement -- it deliberately
synthesizes four variants per datawidth, for the reason given in that section.


### The Workload

One [`Design`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Design) carries an `rtl.<n>` [fileset](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-fileset) per datawidth, each
setting the Verilog parameter `N`:

```python
"""Build one design carrying an "rtl.<n>" fileset per datawidth."""
design = Design("adder")
design.set_dataroot("parallel", __file__)

for n in DATAWIDTHS:
    with design.active_dataroot("parallel"), design.active_fileset(f"rtl.{n}"):
        design.set_topmodule("adder")
        design.add_file("adder.v")
        design.set_param("N", str(n))


```

Nothing about this is specific to parallelism -- it is the same sweep-by-fileset
pattern used in [Multi-Job Flows](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/multi_job_flows.html#multi-job-flows).


### Approach 1: Serial

The baseline: each datawidth runs to completion before the next one starts, and
within a job only one [flowgraph node](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-flowgraph-node) runs at a time.

```python
design = make_design()

for n in DATAWIDTHS:
    project = make_project(design, n)
    # Pin the scheduler to a single node so nothing overlaps. This is the
    # baseline, not a recommendation.
    project.option.scheduler.set_maxnodes(1)
    project.run()



```

[`[option,scheduler,maxnodes]`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-project-option-scheduler-maxnodes) is pinned to `1` here only to make the
baseline honest. Left alone it defaults to the number of available cores, so
**SiliconCompiler already overlaps independent nodes without you asking** -- the
serial case is the one you have to opt into.


### Approach 2: Index Parallelism -- Inside a Job

[Indices](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-index) are variants of a [step](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-step) operating on identical
input data. They have no edges between them, so the scheduler is free to run them
concurrently, and a `minimum` node picks the best result.

Flows expose this through `_np` arguments -- `syn_np` here, and
`floorplan_np`, `place_np`, `cts_np`, `route_np` on
[asicflow](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/flows.html#schema-siliconcompiler-flows-asicflow-asicflow):

```python
design = make_design()

for n in DATAWIDTHS:
    # Four synthesis indices per job. The jobs still run one after another,
    # but each one now uses several cores instead of one -- and produces four
    # variants rather than one, which is why this run is not a like-for-like
    # timing comparison against the other two.
    project = make_project(design, n, syn_np=4)
    project.run()



```

This is the approach to reach for when you want to *explore* -- several tool
configurations against the same input, with the winner selected automatically.
[Using Index for Optimization](https://docs.siliconcompiler.com/en/latest/user_guide/execution_model.html#using-index-for-opt) builds a synthesis
sweep out of the same primitives.

> **Warning**
> Give the flow its own `name`. A [target](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/targets.html#builtin-targets) has usually
> already registered a flow under the default name, and constructing another
> with that name resolves back to *its* copy:
>
> ```
> project.set_flow(SynthesisFlow(syn_np=4))                 # silently syn_np=1
> project.set_flow(SynthesisFlow(name="sweep", syn_np=4))   # four indices
> ```
>
> The failure mode is quiet: the run succeeds, just without the extra indices.
> Check with `project.get("flowgraph", project.option.get_flow(),
> field="schema").get_nodes()`.


### Approach 3: Process Parallelism -- Across Jobs

Index parallelism cannot help when the runs differ in their *inputs*: four
datawidths are four different elaborations, so they are four different flows.
Because they share nothing, they can run as independent processes.

```python
# Each datawidth is an independent flow with no data shared between them,
# so they can run as separate processes.
#
# Two constraints shape this, and both come from run() starting processes of
# its own inside each worker:
#
# ProcessPoolExecutor, not multiprocessing.Pool -- Pool's workers are
# daemonic, and a daemonic process may not have children, so run() dies with
# "daemonic processes are not allowed to have children".
#
# get_process_context(), not the interpreter default -- SiliconCompiler pins
# the same context for its own workers, and the default changed to forkserver
# on Linux in Python 3.14.
with ProcessPoolExecutor(len(DATAWIDTHS), mp_context=get_process_context()) as pool:
    for n, area in pool.map(_run_one, DATAWIDTHS):
        print(f"N={n:<3} cellarea={area}")



```

The worker returns a metric rather than the project, because what crosses a
process boundary has to be picklable:

```python
"""Worker body: a complete, independent run in its own process."""
project = make_project(make_design(), n)
project.run()
return n, project.history(f"N{n}").get(
    "metric", "cellarea", step="synthesis", index="0")



```

> **Warning**
> **Do not use** `multiprocessing.Pool` **for this.** Its workers are
> daemonic, and a daemonic process may not have children. [`Project.run()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.project.Project.run)
> forks a worker per [flowgraph node](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-flowgraph-node), so inside a `Pool` it fails with
> `daemonic processes are not allowed to have children` before any tool
> starts. [`ProcessPoolExecutor`](https://docs.python.org/3/library/concurrent.futures.html#concurrent.futures.ProcessPoolExecutor) does not make its
> workers daemonic, which is why it is used above. Plain
> [`multiprocessing.Process`](https://docs.python.org/3/library/multiprocessing.html#multiprocessing.Process) also works.

> **Note**
> **Guard your script.** SiliconCompiler forks its own node workers on Linux,
> but a script that itself starts processes must be import-safe: on macOS and
> Windows the child re-imports the file, and without
> `if __name__ == "__main__":` it recurses instead of running.


### Choosing Between Them

| Approach | Use when | Bounded by |
| --- | --- | --- |
| **Index** | Runs share an input and differ in tool settings; you want the best result picked for you. | [`[option,scheduler,maxnodes]`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-project-option-scheduler-maxnodes), and the width the flow was built with (`_np`). |
| **Process** | Runs differ in their inputs -- different designs, parameters, or targets -- and you want all the results. | Your pool size, and memory: each process holds a full toolchain. |
| **Both** | A sweep where each point also explores settings. | Multiply the two; it is easy to oversubscribe. |

The two compose, and that is where oversubscription starts: a pool of 4 processes
each running a flow with `syn_np=4` can ask for 16 concurrent tool invocations,
each of which may itself be multi-threaded. Bound it with
[`[option,scheduler,maxnodes]`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-project-option-scheduler-maxnodes) and
[`[option,scheduler,maxthreads]`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-project-option-scheduler-maxthreads) -- see
[Control how much of the machine a run uses](https://docs.siliconcompiler.com/en/latest/user_guide/howto.html#howto).

> **Seealso**
> - [Compilation process](https://docs.siliconcompiler.com/en/latest/user_guide/execution_model.html#execution-model) -- steps, indices, and how the
>   flowgraph is executed.
> - [Multi-Job Flows](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/multi_job_flows.html#multi-job-flows) -- chaining and sweeping jobs, and
>   reading results back out of history.
> - [Remote processing](https://docs.siliconcompiler.com/en/latest/user_guide/remote_processing.html#remote-processing) -- moving the same flows onto a
>   cluster, where the ceiling is much higher than one workstation.


---

Source: https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/cluster.html

## Running on a Cluster

A flowgraph is a set of independent tasks with declared dependencies, which is
exactly the shape a job scheduler wants. Handing the nodes to a cluster instead
of running them on your laptop is one option:

```python
project.option.scheduler.set_name("slurm")
```

Everything else -- the design, the flow, the target -- is unchanged. The same
script runs locally, on a cluster, or in containers.


### What the schedulers are

| Value | Runs each node |
| --- | --- |
| *(unset)* | As a process on the machine you launched from. The default. |
| `slurm` | As a Slurm job. Needs a reachable `slurmctld`. |
| `docker` | In its own container -- see [Docker](https://docs.siliconcompiler.com/en/latest/user_guide/docker.html#docker-two-ways) |

> **Note**
> `lsf` and `sge` are accepted by the schema but **have no implementation**
> -- only `slurm` and `docker` are dispatched. Setting either is not
> silently ignored: the run fails at start-up, before any node executes, with
>
> ```
> Unsupported scheduler 'lsf' for node <step>/<index>
> ```
>
> The same applies when it is set on a single node
> (`set_name("lsf", step="route")`) rather than on the whole run. If you
> need one of them, say so on
> [Discussions](https://github.com/siliconcompiler/siliconcompiler/discussions);
> the dispatch layer is small and the Slurm one is the template.

> **Important**
> **The build directory must be on shared storage.** Nodes pass results to each
> other through `build/`, so every host that might run a node has to see the
> same filesystem at the same path. This is the single most common reason a
> working local build fails on a cluster.
>
> ```python
> project.option.set_builddir("/shared/scratch/me/build")
> ```


### Asking for resources

Per-node resource requests translate to the scheduler's own switches:

```python
project.option.scheduler.set_cores(16)
project.option.scheduler.set_memory(64000)      # MB
project.option.scheduler.set_queue("bigmem")    # partition
```

All three take `step=`/`index=`, which is usually what you want -- routing
needs a different machine than linting does:

```python
project.option.scheduler.set_cores(32, step="route")
project.option.scheduler.set_memory(128000, step="route")
```

Anything the accessors do not cover goes through
[`add_options()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.option.SchedulerSchema.add_options), which passes switches to the scheduler
verbatim.


### Bounding the fan-out

On a cluster the limit stops being your core count and starts being what you are
allowed to occupy:

```python
project.option.scheduler.set_maxnodes(50)    # concurrent nodes
project.option.scheduler.set_maxthreads(8)   # threads per tool
```

These compose with the flow's own width. A sweep of 10 jobs, each with
`syn_np=4`, is 40 concurrent tool invocations before either of these applies --
see [Parallel Job Execution](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/parallel.html#parallel-execution), which is worth reading
first if you are about to point this at a shared machine.


### Being told when it finishes

A cluster run is one you walk away from:

```python
project.option.scheduler.add_msgcontact("me@example.com")
project.option.scheduler.add_msgevent("end")     # also: "begin", "timeout", "fail"
```

[Job status emails](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/emails.html#emails) covers what arrives.


### Delaying the start

[`set_defer()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.option.SchedulerSchema.set_defer) takes a time and passes it to Slurm as
`--begin`, so the job is queued but does not start until then -- useful for
holding a long build until a shared machine is quiet.

> **Note**
> This does **not** detach the run. SiliconCompiler still waits for the job to
> finish, so the process stays alive for the delay *and* the build. There is
> currently no fire-and-forget submission; use your shell or the scheduler
> directly if you need one.


### Setting up Slurm

If you do not already have a cluster, [Slurm setup](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/slurmsetup.html#slurmsetup) walks
through configuring a single machine as a one-host cluster, which is the right
way to test that a script works under a scheduler before asking for real
resources. Add hosts afterwards.

> **Seealso**
> [Remote processing](https://docs.siliconcompiler.com/en/latest/user_guide/remote_processing.html#remote-processing) is the other way to run
> elsewhere -- a SiliconCompiler server rather than a batch scheduler, and no
> shared filesystem on your side (the server may still need one behind it). [Docker](https://docs.siliconcompiler.com/en/latest/user_guide/docker.html#docker) runs the tools locally
> without installing them.


---

Source: https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/ci.html

## Running Builds in CI

A SiliconCompiler build is an ordinary Python script, so any CI system that runs
Python runs it. The interesting part is not getting it to run once -- it is
getting it to run in minutes rather than an hour, and to fail for the right
reasons.


### Start with what costs nothing

Not every check needs EDA tools. The cheapest gates catch most breakage and run
in seconds on a stock runner:

```yaml
- run: pip install siliconcompiler
- run: python -c "from mydesign import design; assert design().check_filepaths()"
- run: python lint.py
```

[Linting](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/lint.html#lint-tutorial) needs no tools at all -- the default linter ships
as a Python package. [Formal checks](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/simulate.html#simulate-tutorial) and simulation need
a simulator but no [PDK](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-PDK). Run these on every push, and save the full flow
for something less frequent.


### The two things that make it practical

**Do not install tools per job.** Use the
[Docker image](https://docs.siliconcompiler.com/en/latest/user_guide/docker.html#docker), which has them already:

```yaml
jobs:
  build:
    runs-on: ubuntu-latest
    container: ghcr.io/siliconcompiler/sc_runner:latest
    steps:
      - uses: actions/checkout@v4
      - run: python make.py
```

Pinning `:latest` is a trap, though: the image drifts from the release you
meant, and you end up debugging a tool version nobody chose. **Ask
SiliconCompiler which image to use.** It publishes a reusable workflow that
resolves the exact digest for a tool set, which you call rather than reimplement:

```yaml
jobs:
  image:
    uses: siliconcompiler/siliconcompiler/.github/workflows/docker_image.yml@v0.38.2
    with:
      sc_version: v0.38.2       # 'latest' resolves to the newest release
      tool: runner              # SiliconCompiler + the tools; see below

  build:
    needs: image
    runs-on: ubuntu-latest
    container: ${{ needs.image.outputs.sc_tool }}
    steps:
      - uses: actions/checkout@v4
      - run: python make.py
```

Pin both: the `@` ref decides which workflow definition runs, and
`sc_version` decides which image it resolves. A tag is the readable choice; a
commit SHA is the strict one, since a tag can be moved. `latest` and `@main`
are convenient and reproducible only until someone releases.

`sc_tool` comes back fully qualified -- `ghcr.io/siliconcompiler/sc_runner:v0.38.2`
for `runner`, or a digest-pinned `sc_tools:af23682...` for `tools` -- so the
job moves forward only when you change `sc_version`. Behind
[docker_image.yml](https://github.com/siliconcompiler/siliconcompiler/blob/main/.github/workflows/docker_image.yml)
is `siliconcompiler.utils.toolimages`, which derives the image from the tool versions
pinned in `_tools.json`, so the container and the tool pins cannot disagree.

Two images are published and they are **not** interchangeable:

| Image | Contains |
| --- | --- |
| `tool: runner` | `sc_runner` -- the EDA tools **plus** SiliconCompiler, at the release the image was built for. Run a build script with nothing to install. |
| `tool: tools` | `sc_tools` -- the EDA tools and **not** the SiliconCompiler package. For jobs that install it themselves: testing a checkout, or pinning a version other than the image's. |

Getting this backwards is the easy mistake: `sc_tools` followed by
`python make.py` fails on `ImportError: siliconcompiler`.

Or build your own with [sc-install](https://docs.siliconcompiler.com/en/latest/reference_manual/apps.html#app-sc-install) and reuse it. Either
way the install happens once, not once per job.

**Cache the data.** [PDKs](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-PDK), libraries and git-fetched sources are
downloaded into [the cache](https://docs.siliconcompiler.com/en/latest/user_guide/directories.html#sc-home) on first use. Point it somewhere your
CI can restore:

```yaml
- uses: actions/cache@v4
  with:
    path: ~/.sc/cache
    key: sc-cache-${{ hashFiles('**/make.py') }}
- run: python make.py
```

`~/.sc/cache` is the default location, so caching that path is enough. It also
carries the tool caches, so a Verilator build restores its ccache along with the
PDK. To put it somewhere else, set it in the script -- there is no environment
variable for it:

```python
project.option.set_cachedir("/mnt/ci-cache")
```

Without this every job re-downloads the PDK, which usually costs more than the
build.


### Failing for the right reason

[`Project.run()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.project.Project.run) raises on a failed run, so a build that cannot complete
fails the job by itself. What it will *not* do is fail because the result got
worse -- that is yours to assert. Read the metrics from the history object
`run()` returns, not from the live project, which is reset when the job ends:

```python
history = project.run()
project.summary()

slack = history.get("metric", "setupslack", step="route", index="0")
assert slack >= 0, f"timing did not close: {slack}"
```

For anything beyond a couple of assertions, [checklists](https://docs.siliconcompiler.com/en/latest/user_guide/checklist.html#checklists) are
the structured form -- a named set of criteria checked against recorded metrics,
which is a better artifact than a wall of asserts and produces the same
pass/fail.

> **Tip**
> Record the numbers, not just the verdict. Publishing
> `build/<design>/<jobname>/<design>.pkg.json` as an artifact means a
> regression can be diffed against the last good run rather than re-argued.
> [Directory structures](https://docs.siliconcompiler.com/en/latest/user_guide/directories.html#build-directory) says what else is worth
> keeping.


### Keeping it fast

- **Split the flow.** [`[option,from]`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-project-option-from) / [`[option,to]`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-project-option-to) run
  synthesis on every push and the full flow nightly.
- **Bound the parallelism.** CI runners are small; a flow built with `_np`
  widths that suit a workstation will thrash. See
  [`[option,scheduler,maxnodes]`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-project-option-scheduler-maxnodes) and
  [Parallel Job Execution](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/parallel.html#parallel-execution).
- **Give each configuration its own jobname** so results do not overwrite each
  other -- [Multi-Job Flows](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/multi_job_flows.html#multi-job-flows).


### A worked reference

SiliconCompiler's own CI does all of the above: it runs inside a prebuilt tools
container, restores the data cache between jobs, and splits fast checks from the
nightly EDA runs. The workflows under [.github/workflows](https://github.com/siliconcompiler/siliconcompiler/tree/main/.github/workflows)
are the reference implementation, and are worth copying from rather than
starting fresh.

> **Seealso**
> [When a Run Fails](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/debug.html#debug-tutorial) -- what to collect from a CI failure
> so it can be diagnosed without re-running it, and `sc-issue` for packaging
> a reproduction out of a build directory.


---

Source: https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/custom_flow.html

## Authoring a Custom Flow

The built-in flows cover the usual paths -- [lint](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-lint), [synthesis](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-synthesis),
[RTL](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-RTL)-to-[GDSII](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-GDSII), [signoff](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-signoff). Sooner or later you want something they do not do: an extra check
between two steps, a tool the standard flow does not run, or a pipeline
assembled out of pieces of several flows.

A [flow](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-flow) is just a graph of tasks, and building one is a handful of lines.
This page walks one end to end; [Building a Flowgraph](https://docs.siliconcompiler.com/en/latest/development_guide/flows.html#dev-flows) is the
API reference to keep open beside it.


### When you actually need one

Reach for a custom flow last, not first. Three cheaper things handle most cases:

| You want to | Do this instead |
| --- | --- |
| Run only part of a standard flow | [`[option,from]`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-project-option-from) / [`[option,to]`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-project-option-to) -- [Run only part of the flow](https://docs.siliconcompiler.com/en/latest/user_guide/howto.html#howto) |
| Try several settings for one step | the flow's `_np` argument -- [Parallel Job Execution](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/parallel.html#parallel-execution) |
| Inject a Tcl script around a tool | [`add_prescript()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.add_prescript) / [`add_postscript()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.add_postscript) -- [Using Commercial Tools](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/commercial_tools.html#commercial-tools) |
| **Change which tools run, or in what order** | **a custom flow** |


### Nodes and edges

Two calls build a graph. [`Flowgraph.node()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Flowgraph.node) names a [step](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-step) and gives
it a task to run; [`Flowgraph.edge()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Flowgraph.edge) says one must finish before another
starts:

```python
from siliconcompiler import Flowgraph

flow = Flowgraph("myflow")
flow.node("import", ImportFilesTask())
flow.node("synthesis", SynthesisTask())
flow.edge("import", "synthesis")

project.set_flow(flow)
```

Each node is a [task](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-task) -- a tool driver class, not a tool name. That is what
lets a flow be checked before anything runs: the task knows what it needs and
what it produces.

Nodes with no edge between them carry no ordering constraint, so the scheduler
*may* run them together. Whether it does depends on
[`[option,scheduler,maxnodes]`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-project-option-scheduler-maxnodes), the resources available, and how wide the
rest of the flow is -- leaving an edge out permits concurrency rather than
guaranteeing it.


### A worked example

`examples/heartbeat` builds a timing-signoff flow that no built-in flow
provides: stage a parasitics file into a node's inputs, then run timing against
it.

```python
# Stage the parasitics into the timing node's inputs; sc_timing.tcl reads
# the per-corner SPEF from the step inputs (there is no SPEF fileset type).
signoff_flow.node("stage", ImportFilesTask())
signoff_flow.node("signoff", TimingTask())
signoff_flow.edge("stage", "signoff")
signoff.set_flow(signoff_flow)

```

Two nodes, one edge, and it replaces the flow the target installed. Note what is
*not* here: the target is still loaded, so the PDK, the libraries and the delay
models all come from it. A custom flow changes what runs, not what it runs
against.

The rest of that function is worth reading for how a custom flow fits into a
larger build -- it is the third job in a chain, taking a netlist from the
implementation run and a VCD from a simulation run. See
[Multi-Job Flows](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/multi_job_flows.html#multi-job-flows) for that pattern.


### Configuring a task in the flow

Once a task is in a flow, [`find_task()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.find_task) reaches it to set its options:

```python
ImportFilesTask.find_task(signoff).add_import_file(spef)
```

This is the general shape for tuning any node: find the task on the project, then
call its accessors. It works for built-in flows too --
`SynthesisTask.find_task(project).set_threads(4)`.


### Reusing pieces

Flows compose. [`Flowgraph.graph()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Flowgraph.graph) splices an existing flow in as a
subgraph, which is how the built-in flows are built out of each other -- the
[ASIC](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-ASIC) flow is a [floorplanning](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-floorplan) flow, a
[placement](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-placement) flow, a [routing](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-routing) flow and more, joined together:

```python
flow = Flowgraph("check_then_build")
flow.graph(LintFlow(), name="lint")
flow.graph(SynthesisFlow(), name="syn")
```

Prefer this to rebuilding a standard pipeline node by node -- you inherit its
updates for free.


### Checking what you built

A flowgraph is data, so look at it before you spend an hour running it:

```python
flow.write_flowgraph("myflow.svg")
```

> **Warning**
> Give a new flow its own **name**. A [target](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/targets.html#builtin-targets) has usually
> already registered a flow under the default one, and constructing another with
> that name resolves back to *its* copy -- so your changes silently do not
> appear. The failure is quiet: the run succeeds, just not the run you wrote.

[`Project.run()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.project.Project.run) checks the graph for correctness before executing anything:
unreachable nodes, missing inputs, and tasks whose requirements are not met all
fail before a tool starts.


### Writing the task itself

If no existing task wraps the tool you need, that is the next layer down:
[Building a Tool](https://docs.siliconcompiler.com/en/latest/development_guide/tools.html#dev-tools) covers writing a driver -- the setup, the
command line, and reading metrics back out of the tool's reports. The four
methods a task can implement are [`setup()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.setup), [`pre_process()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.pre_process),
[`runtime_options()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.runtime_options) and [`post_process()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.post_process).

> **Seealso**
> [Building a Flowgraph](https://docs.siliconcompiler.com/en/latest/development_guide/flows.html#dev-flows) for the full API,
> [Compilation Process](https://docs.siliconcompiler.com/en/latest/user_guide/execution_model.html#execution-model) for how a graph is executed, and
> [flows](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/flows.html#builtin-flows) for the built-in ones -- worth reading as
> worked examples before writing your own.


---

Source: https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/commercial_tools.html

## Using Commercial Tools

SiliconCompiler drives commercial EDA tools as well as open-source ones -- the
[flowgraph](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-flowgraph) does not care which tool a [task](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-task) wraps. What differs is how you get the
driver.

> **Important**
> **Read this first, because the capability tables do not say it.**
> [Vivado](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/tools.html#tool-vivado) is the only commercial tool whose driver ships in
> this repository. Drivers for the Synopsys, Cadence and Siemens tools exist and
> are in use, but cannot be distributed publicly: a tool driver encodes command
> lines, script structure and flow knowledge that vendor agreements cover.
>
> So "supported" means the integration exists, not that `pip install`
> gives it to you. If you need one of those, ask on
> [Discussions](https://github.com/siliconcompiler/siliconcompiler/discussions) --
> that is the honest route, and it is a conversation about access rather than
> something the docs can settle.

Everything else you can drive yourself, using the same mechanisms the built-in
drivers use.


### Vivado, end to end

`examples/heartbeat` targets a Xilinx Artix-7 alongside its [ASIC](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-ASIC) flows:

```python
def fpga(N: Optional[str] = None):
    """Runs the FPGA implementation flow for the Heartbeat design.

    This flow targets a Xilinx Artix-7 FPGA (xc7a100tcsg324) and generates
    a bitstream that can be programmed onto the device.

    Args:
        N (str, optional): The value for the Verilog parameter 'N'.
            Defaults to None, which uses the value set in the design schema.
    """
    # Create a project instance for an FPGA flow.
    project = FPGA()

    # Instantiate and configure the design.
    hb = HeartbeatDesign()
    project.set_design(hb)

    # Add the RTL and FPGA constraint filesets.
    project.add_fileset("rtl")
    project.add_fileset("fpga.xc7a100tcsg324")
    # Specify the Xilinx implementation flow.
    project.set_flow(FPGAXilinxFlow())

    # Configure the specific FPGA part details.
    fpga = FPGADevice("xc7")
    fpga.set_partname("xc7a100tcsg324")
    project.set_fpga(fpga)

    # Optionally override the 'N' parameter.
    if N is not None:
        hb.set_param("N", N, fileset="rtl")

    # Run the FPGA flow (synthesis, place, route, bitstream generation).
    project.run()
    project.summary()

```

```bash
cd examples/heartbeat
smake fpga
```

[FPGAXilinxFlow](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/flows.html#schema-siliconcompiler-flows-fpgaflow-fpgaxilinxflow) is
the standard Vivado pipeline. SiliconCompiler runs `vivado` in batch mode, so
it has to be on your `PATH` and your licence has to work -- test that outside
SiliconCompiler first, because a licence failure surfaces as a tool error in
`<step>.log` rather than as anything more helpful.


### Injecting Tcl around a tool

The most common commercial-tool request is not a new driver at all: it is *"I
need to run my own Tcl at a specific point"* -- a vendor-specific constraint, an
in-house checking script, an extra report.

Every task takes a pre- and post-script, so you do not have to fork the driver:

```python
from siliconcompiler.tools.vivado.syn_fpga import SynthesisTask

task = SynthesisTask.find_task(project)
task.add_prescript("scripts/my_setup.tcl")     # before the tool's own script
task.add_postscript("scripts/my_reports.tcl")  # after it
```

The scripts are sourced by the tool in its own interpreter, with the tool's state
already loaded -- so a post-script sees the elaborated or placed design and can
report on it. Both are per-node, so `step=`/`index=` narrows them to one
point in the flow:

```python
task.add_postscript("scripts/check.tcl", step="synthesis")
```

That is the answer to "how do I get my Tcl between synthesis and
implementation": attach it to the step it belongs after.


### Writing a driver

For a tool with no driver at all, a [task](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-task) class is the unit of work.
[Building a Tool](https://docs.siliconcompiler.com/en/latest/development_guide/tools.html#dev-tools) is the reference; the shape is four optional
methods:

| Method | Does |
| --- | --- |
| [`setup()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.setup) | Declares what the task needs and produces -- inputs, outputs, required files, the tool and version |
| [`pre_process()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.pre_process) | Runs before the tool: stage files, generate a script |
| [`runtime_options()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.runtime_options) | Builds the command line |
| [`post_process()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.post_process) | Reads the tool's reports and records [metrics](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-metric) |

[`post_process()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.post_process) is the one people underestimate. A driver that runs a tool but
records no metrics gives you a build you cannot gate on -- no
[checklist](https://docs.siliconcompiler.com/en/latest/user_guide/checklist.html#checklists) can check it, and the summary table has nothing to
show. Read an existing driver before writing yours; the OpenROAD and Yosys ones
are the most complete.


### Keeping it private

A driver for a licensed tool usually cannot go in this repository, and it does
not need to. Package it as your own `pip`-installable module and register it
through entry points --
[Packaging an External Library](https://docs.siliconcompiler.com/en/latest/development_guide/external_libraries.html#dev-external-libraries) covers the layout,
the `pyproject.toml`, a proprietary licence identifier, and the
environment-variable [dataroot](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-dataroot) pattern for reference data that must not
enter a wheel.

[Where does my module go?](https://docs.siliconcompiler.com/en/latest/development_guide/contribution.html#module-placement) is the one-page version of
that decision.

> **Seealso**
> [Authoring a Custom Flow](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/custom_flow.html#custom-flow-tutorial) for wiring a new task
> into a pipeline, and [When a Run Fails](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/debug.html#debug-tutorial) for reading a
> tool's log when it does not do what you expected.


---

Source: https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/dashboard_tutorial.html

## Dashboard Tutorial

To start, ensure you install the dashboard dependencies by running:

```bash
pip install siliconcompiler[dashboard]
```

At this point, you should have the dashboard in your environment.

Then, run the command:

```bash
python3 -m siliconcompiler.apps.utils.dashboard -cfg <path to manifest>
```

You can specify the port by adding a port flag:

```bash
python3 -m siliconcompiler.apps.utils.dashboard -cfg <path to manifest> -port <port number>
```

And/or you can include extra projects by adding a `-graph_cfg` flag:

```bash
python3 -m siliconcompiler.apps.utils.dashboard -cfg <path to manifest> -graph_cfg <manifest name> <path to manifest> -graph_cfg <manifest name> <path to manifest>
```


### Header

In the header, you can select any of the projects that are part of the history of the project loaded in and any of the other projects loaded in through the `-graph_cfg` flag (see arrow below).


### Metrics Tab

You will load into the metrics tab similar to the one below upon running [dashboard](https://docs.siliconcompiler.com/en/latest/reference_manual/apps.html#app-dashboard).


#### Metrics Section

The metrics section displays an overview of each value for each metric tracked for each node.
Click "Transpose" to switch the axes (arrow A in image below).

You may use the "Select Parameter" expander to specify certain nodes and/or metrics (arrow C and D in image below).
Click "Apply" to make those changes (arrow B in image below).


#### Node Information Section

Below is the node information section.
It consists of three subsections - node metrics, node details, and node files.

You can select a node using the "Select Node" expander as seen with arrow's A and B below.
Click "Apply" to make the change.

Alternatively, you can double click on the flowgraph node.
Nodes that are selected will bolden.


##### Node Metrics Subsection

The node metrics subsection consists of all of not `None` values recorded for each of the metrics recorded for the selected node.


##### Node Details Subsection

The node details subsection consists of all of the characteristics about this node that are not reflected in the metrics section.


##### Node Files Subsection

The node files subsection consists of all of the files for a given node that are in the build directory.

Selecting a node will display a list of the metrics that the file informs below the file tree.


### File Viewer Tab

The selected node you clicked in the Node Files Subsection will appear here.
You may download the file by clicking the download button as shown below.

If no file is selected, the error message below will be displayed telling you to select a file first.


### Manifest Tab

The next tab you can select is the manifest tab.
This displays the manifest after it has been filtered through to make it more readable.

To view the manifest, click the arrow on the dictionary (arrow A). The search bars will return partial matches for either
the keys (arrow B in image below) or the values (arrow C in image below).
You may download the JSON as you view it at any point (arrow D in image below).
You can view the raw manifest by clicking the checkbox to the right of the search bar (arrow E in image below).


### Display Preview Tab

This displays the preview image of the project if there is one in the directory (example given below). If not, this tab will not be included.


### Graphs Tab

This tab is meant to make comparisons between nodes for a given metric across many projects.

At the top of the panel, select which runs/jobs to include for all the graphs (arrow A in image below). T

Move the slider to add more graphs or remove old ones (arrow B in image below).

For each graph, you must select one metric (show in image below).

You may select any amount of nodes (show in image below).

Sometimes nodes may not have values for a metric, in which case they will not be included in the graph.
In the image below, import0 is not in the legend.

Sometimes nodes that are in the legend are not visible on the graph.
What has happened is that they have the exact same values as some other node.
Consider deselecting other nodes in this case.
In the image below, cts0 is barely visible on the graph.


---

Source: https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/emails.html

## Job Status Emails

SiliconCompiler supports sending job status updates to your email.
To get started you will need to get the [SMTP](https://en.wikipedia.org/wiki/Simple_Mail_Transfer_Protocol) login information.
Then run [sc-config email set](https://docs.siliconcompiler.com/en/latest/reference_manual/apps.html#app-sc-config-email), which asks for each setting without echoing the password, and check them by sending yourself one message:

```bash
sc-config email set
sc-config email test you@xyz.com
```

The settings are kept in `$HOME/.sc/email.json`, readable only by you, which looks like this:

```json
{
    "server": "smtp.gmail.com",
    "port": 465,
    "ssl": true,
    "username": "user@gmail.com",
    "password": "app password",
    "from": "Updates <user@gmail.com>"
}
```

During the job execution you can control where the emails will be sent to by setting [`[option,scheduler,msgcontact]`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-project-option-scheduler-msgcontact), this can be controlled
per node basis.
Additionally, [`[option,scheduler,msgevent]`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-project-option-scheduler-msgevent) needs to set to indicate the types of messages to receive.
By default, this is disabled.
This key can be set to the following values:

- `begin`: this will send a message to indicate a specific node has begun.
- `end`: this will send a message to indicate a specific node has finished.
- `fail`: this will send a message to indicate a specific node has failed.
- `timeout`: this will send a message to indicate a specific node has timed out.
- `summary`: this will send a message with a summary of the run metrics.
- `all`: convenience value to include all of the above.

```python
...
# Send messages for all nodes to you@xyz.com
project.option.scheduler.add_msgcontact('you@xyz.com')

# Send messages for route step to you@xyz.com and pd-routing@xyz.com
project.option.scheduler.add_msgcontact(['you@xyz.com', 'pd-routing@xyz.com'], step='route')

# Send messages at the end of each node, in the event of a failure, and the final summary.
project.option.scheduler.add_msgevent(['end', 'fail', 'summary'])
...
```

Each email for node execution will contain the status of the run, metrics and records collected to this point, and any logs that are available.
The summary email will contain a metrics table and the output image if one is available.


---

Source: https://docs.siliconcompiler.com/en/latest/user_guide/examples.html

## Example Designs

Every directory below is a working, tested design in the
[examples](https://github.com/siliconcompiler/siliconcompiler/tree/main/examples)
folder of the repository. They run in CI, so they compile against the current
release rather than the one they were written for.

This page is generated from those directories, so a new example appears here
automatically and the folder listing and this page cannot drift out of sync.


### Running one

`examples/` is not shipped inside the installed package, so clone the
repository (or open the source link on any entry below) and run the script named
as the entry point:

```bash
git clone https://github.com/siliconcompiler/siliconcompiler.git
cd siliconcompiler/examples/gcd
python gcd.py
```

Where the entry point is `make.py`, it holds several targets rather than one
script body, and [smake](https://docs.siliconcompiler.com/en/latest/user_guide/howto.html#howto-smake) runs them by name:

```bash
cd siliconcompiler/examples/heartbeat
smake --help          # what this example can do
smake lint            # run one of them
```

**Read "Requires" before starting a run.** Most examples need EDA tools
installed locally -- see [External Tools](https://docs.siliconcompiler.com/en/latest/user_guide/installation.html#external-tools), or use
[Docker](https://docs.siliconcompiler.com/en/latest/user_guide/docker.html#docker) to run them without installing anything. The ones marked
*no PDK* are the cheapest place to start.


### Where to start

| If you want to | Start with |
| --- | --- |
| Run something in seconds, with no [PDK](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-PDK) | adder_cocotb (simulation), sva_sby (formal), blinky (FPGA) |
| See a plain RTL-to-GDSII build | gcd, then aes for something larger |
| Compile from something other than Verilog | fibone (Bluespec), ghdl_fsynopsys (VHDL), heartbeat_migen (Migen), mlir_hls (LLVM IR) |
| Build a design out of other designs | picorv32, macro_reuse, uniquify |
| Sweep, parallelise, or analyse a build | parallel, oh_experiments, pex_calibration |
| See every project type in one place | heartbeat |


### All examples


#### `adder_cocotb`

Example demonstrating cocotb integration with SiliconCompiler.

This example shows how to use the `dvflow_cocotb` helper to run Python-based
cocotb testbenches against a design, using either the Icarus Verilog or
Verilator simulation flow.

Requires

cocotb (pip), plus icarus or verilator -- no PDK needed

Source

[examples/adder_cocotb](https://github.com/siliconcompiler/siliconcompiler/tree/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/examples/adder_cocotb) (entry point `make.py`)


#### `adder_lec`

Checks the synthesized 'adder' netlist against the RTL it came from.

This script sets up an ASIC project for a small adder, synthesizes it into a
Nangate45 netlist, and checks that netlist against the RTL with
Kepler-formal.

Requires

yosys, kepler-formal; freepdk45 (via lambdapdk)

Source

[examples/adder_lec](https://github.com/siliconcompiler/siliconcompiler/tree/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/examples/adder_lec) (entry point `lec.py`)


#### `aes`

This script demonstrates a standard RTL-to-GDSII compilation flow

for an AES (Advanced Encryption Standard) core. It takes Verilog source
code and timing constraints as input and produces a final GDSII layout file.

Requires

yosys, openroad, opensta, klayout; freepdk45 (via lambdapdk)

Source

[examples/aes](https://github.com/siliconcompiler/siliconcompiler/tree/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/examples/aes) (entry point `aes.py`)


#### `blinky`

This script demonstrates a standard RTL-to-bitstream flow for an FPGA.

It takes a Verilog design for a simple "blinky" circuit, compiles it
for a specific iCE40 FPGA part, and generates a bitstream file that

can be programmed onto the hardware.

Requires

yosys, nextpnr, icepack -- no PDK; targets a Lattice iCE40 UP5K

Source

[examples/blinky](https://github.com/siliconcompiler/siliconcompiler/tree/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/examples/blinky) (entry point `blinky.py`)


#### `fibone`

This script demonstrates a Bluespec SystemVerilog (BSV) to GDSII flow.

It shows that a Bluespec design needs no custom flow: the target reads the
source language off the design's files and puts the Bluespec compiler in
front of the standard synthesis, place, and route steps.

Requires

bsc (Bluespec), yosys, openroad, opensta, klayout; freepdk45 (via lambdapdk)

Source

[examples/fibone](https://github.com/siliconcompiler/siliconcompiler/tree/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/examples/fibone) (entry point `fibone.py`)


#### `gcd`

Builds the 'gcd' (Greatest Common Divisor) design using the FreePDK45 PDK.

This script sets up a basic ASIC project, configures the design
with its RTL and SDC files, loads the FreePDK45 demo target,
runs the compilation flow, and displays a summary and the final layout.

The other scripts in this directory build the same design against gf180,
ihp130 and skywater130.

Requires

yosys, openroad, opensta, klayout; freepdk45 (via lambdapdk)

Source

[examples/gcd](https://github.com/siliconcompiler/siliconcompiler/tree/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/examples/gcd) (entry point `gcd.py`)


#### `ghdl_fsynopsys`

This script demonstrates a VHDL to GDSII flow.

It shows how SiliconCompiler uses a specialized flow to automatically
convert VHDL source code into Verilog before running the standard
synthesis, place, and route steps.

Requires

ghdl, yosys, openroad, opensta, klayout; freepdk45 (via lambdapdk)

Source

[examples/ghdl_fsynopsys](https://github.com/siliconcompiler/siliconcompiler/tree/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/examples/ghdl_fsynopsys) (entry point `build.py`)


#### `heartbeat`

One small design, taken through nearly everything SiliconCompiler does.

`heartbeat` is the design the [Quickstart](https://docs.siliconcompiler.com/en/latest/user_guide/quickstart.html#quickstart-guide) builds. This
script drives it through every project type in the tool, each exposed as an
[smake](https://docs.siliconcompiler.com/en/latest/user_guide/howto.html#howto-smake) target:

```
smake lint          # Lint:  slang, bundled -- no tools to install
smake syn           # ASIC:  synthesis only
smake asic          # ASIC:  RTL to GDSII
smake fpga          # FPGA:  bitstream for a Xilinx Artix-7
smake sim           # Sim:   RTL simulation, opens the waveform
smake sim_postpnr   # Sim:   gate-level, against Skywater130 cell models
smake power         # three chained jobs: VCD-driven power signoff
smake screenshot    # render the finished layout
smake check         # verify every referenced file resolves
```

It is therefore the best single place to see how the project types differ, and
what `smake` is for.

Requires

nothing for lint; verilator or icarus (sim); yosys, openroad, opensta, klayout (syn/asic); vivado (fpga); freepdk45 and skywater130 (via lambdapdk)

Source

[examples/heartbeat](https://github.com/siliconcompiler/siliconcompiler/tree/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/examples/heartbeat) (entry point `make.py`)


#### `heartbeat_migen`

Generates Verilog from a Migen module and runs it through a full

ASIC compilation flow using SiliconCompiler.

Requires

migen (pip), yosys, openroad, opensta, klayout; freepdk45 (via lambdapdk)

Source

[examples/heartbeat_migen](https://github.com/siliconcompiler/siliconcompiler/tree/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/examples/heartbeat_migen) (entry point `heartbeat_migen.py`)


#### `interposer`

A simple example demonstrating how to build a silicon interposer flow.

An interposer is a silicon die that acts as a bridge, providing
connections between other dies (chiplets) and a package substrate. This
design flow focuses on the physical routing of these connections (Redistribution
Layers or RDL) rather than logic synthesis.

Requires

openroad, klayout; interposer (via lambdapdk)

Source

[examples/interposer](https://github.com/siliconcompiler/siliconcompiler/tree/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/examples/interposer) (entry point `interposer.py`)


#### `macro_reuse`

Design Reuse of a Hardened Macro.

This script demonstrates a hierarchical ASIC design flow using SiliconCompiler.
It performs the following steps:
1. Defines a child module 'And'.
2. Hardens 'And' into a macro (Synthesize -> Place -> Route -> GDS/LEF/LIB).
3. Packages the results of 'And' into a reusable StdCellLibrary object.
4. Defines a top-level module 'Top' that instantiates 'And' three times.
5. Builds 'Top' using the hardened 'And' macro.

**Usage:**

  docker run --rm -v "$(pwd):/sc_work"       ghcr.io/siliconcompiler/sc_runner:latest       python3 make.py

Requires

yosys, openroad, opensta, klayout; skywater130 (via lambdapdk)

Source

[examples/macro_reuse](https://github.com/siliconcompiler/siliconcompiler/tree/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/examples/macro_reuse) (entry point `make.py`)


#### `mlir_hls`

High-level synthesis from LLVM IR to GDSII.

The design's `rtl` fileset holds a `.ll` file rather than Verilog.
`HLSASICFlow` runs the HLS tool over it to produce RTL, then hands that to the
usual synthesis, place and route steps.

Requires

bambu, yosys, openroad, opensta, klayout; freepdk45 (via lambdapdk)

Source

[examples/mlir_hls](https://github.com/siliconcompiler/siliconcompiler/tree/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/examples/mlir_hls) (entry point `mlir_hls.py`)


#### `oh_experiments`

Sweep an adder's datawidth and plot area against it.

Synthesizes `oh_add` from the [oh](https://github.com/aolofsson/oh) library
at four datawidths -- sources fetched from GitHub at a pinned commit -- and
plots cell area per width with matplotlib, falling back to printing if it is not
installed. `check_area.py` alongside it reads the same metric back out of a
finished build.

Requires

yosys, opensta; freepdk45 (via lambdapdk). matplotlib is optional -- without it the results are printed instead of plotted.

Source

[examples/oh_experiments](https://github.com/siliconcompiler/siliconcompiler/tree/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/examples/oh_experiments) (entry point `adder_sweep.py`)


#### `padring`

Wrapping a design in an IO pad ring.

Takes a RISC-V processor and its SRAM to GDSII inside a full sky130 pad ring:
40 bidirectional signal pads, 16 supply pads, corners, IO fill, bond pads, and a
core power grid tied out to the ring. The pad ring is generated by lambdalib, so
no sky130 cell is named in the RTL.

The processor is picorv32, fetched from its own repository at a pinned commit
rather than copied into this one.

Requires

yosys, openroad, opensta, klayout; skywater130 (via lambdapdk)

Source

[examples/padring](https://github.com/siliconcompiler/siliconcompiler/tree/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/examples/padring) (entry point `padring.py`)


#### `parallel`

Three ways to get parallelism out of the same sweep: synthesizing `adder.v`

at several datawidths.

`serial` and `processes` do identical work and differ only in scheduling, so
their times compare directly. `indexed` deliberately does *more* -- four
synthesis variants per datawidth instead of one -- because that is what index
parallelism is for: exploring alternatives inside a job, not splitting fixed
work. Compare it on time-per-variant, not on total time.

Run one approach at a time:

```
./parallel.py serial
./parallel.py indexed
./parallel.py processes
```

See the "Parallel Job Execution" tutorial for the accompanying discussion.

Requires

yosys, opensta; freepdk45 (via lambdapdk)

Source

[examples/parallel](https://github.com/siliconcompiler/siliconcompiler/tree/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/examples/parallel) (entry point `parallel.py`)


#### `pex_calibration`

Calibrate OpenROAD's pre-route parasitic estimate for FreePDK45.

This is a thin wrapper around the reusable utility app
`siliconcompiler.tools.openroad.utils.pex_calibrate`. It runs the two-phase
calibration on the bundled demo survey (gcd, picorv32, aes and jpeg) and prints
the `add_openroad_rclayer` / `add_openroad_rccorrection` lines to paste into
a PDK setup.

The same thing from the command line:

```
python -m siliconcompiler.tools.openroad.utils.pex_calibrate freepdk45_demo
```

To calibrate your own PDK, point `TARGET` at your target and pass your own
designs (see the `designs` argument of `calibrate`). For the full write-up
see the "Calibrating the parasitic estimate (PEX)" tutorial (`pex_calibration`)
in the documentation.

Requires

yosys, openroad, opensta; freepdk45 (via lambdapdk)

Source

[examples/pex_calibration](https://github.com/siliconcompiler/siliconcompiler/tree/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/examples/pex_calibration) (entry point `calibrate.py`)


#### `picorv32`

A RISC-V CPU core, optionally wired to an SRAM.

Sources are fetched from the upstream PicoRV32 repository at a pinned commit
rather than vendored, and the `rtl.memory` fileset composes the core with a
single-port RAM from `lambdalib`. Those two techniques -- third-party sources
and building a design out of other designs -- are what the example is for.

Walked through in [Building Your Own SoC](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/picorv32_ram.html#picorv32-example).

Requires

yosys, openroad, opensta, klayout; freepdk45, asap7 or gf180 (via lambdapdk)

Source

[examples/picorv32](https://github.com/siliconcompiler/siliconcompiler/tree/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/examples/picorv32) (entry point `make.py`)


#### `soda`

The SODA Synthesizer front end, driven from SiliconCompiler.

`mm` is a batched matrix multiply in the TOSA dialect --
`mm-no_weights` model, which is what a stateless `torch.matmul` exports to.
This script takes it through the SODA path, each stage exposed as an
[smake](https://docs.siliconcompiler.com/en/latest/user_guide/howto.html#howto-smake) target:

```
smake elaborate     # MLIR to Verilog: soda-opt plus Bambu, nothing else
smake syn           # ...and on through synthesis and timing
smake asic          # ...and on to GDSII
smake compare       # baseline against optimized, on area and timing
smake unrolled      # the optimized strategy at a different unroll depth
smake model         # regenerate mm.mlir from PyTorch (needs requirements.txt)
smake check         # verify every referenced file resolves
```

`compare` is the reason both strategies are here: `baseline` lowers the
kernel with no HLS-oriented optimization, `optimized` runs soda-opt's Bambu
pipeline over it first, and the difference between the two is what the SODA
papers report. soda-opt has a third strategy, `transformed`, which rewrites the
kernel under a transform dialect schedule; it needs a schedule to be worth
running, so it is left to
`SODATransformedElaborationFlow` rather
than shipped here with a schedule that does nothing.

Each strategy is a flow of its own, and every flow that elaborates a design
takes one as its `frontend`, which is how the SODA front end reaches GDSII
without a backend of its own: everything downstream of Bambu -- which upstream
is an OpenROAD-flow-scripts `config.mk` -- is SiliconCompiler's own ASIC flow.

Requires

mlir, soda, bambu (elaborate); plus yosys, opensta (syn); plus openroad, klayout (asic); freepdk45 (via lambdapdk)

Source

[examples/soda](https://github.com/siliconcompiler/siliconcompiler/tree/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/examples/soda) (entry point `make.py`)


#### `sva_sby`

Formal property checking with SymbiYosys.

Five scripts covering the available `PropertyCheckFlow` modes -- singly, in
combination, and selectable. Run any of them directly:

- `demo.py` -- bounded model check: is the assertion true for 100 cycles?
- `prove.py` -- unbounded proof by k-induction: is it true for *all*
  reachable states?
- `cover.py` -- cover: is a stated condition reachable at all?
- `fifo.py` -- all three modes at once, against a FIFO carrying named
  assertions.
- `counter_formal.py` -- the same on a counter, with the mode as an argument.

The first three mirror the official SymbiYosys quickstart, so they are directly
comparable with its `.sby` files.

Requires

sby, yosys, and an SMT solver -- bitwuzla by default (boolector is the other supported choice; see the `engine` parameter).

Source

[examples/sva_sby](https://github.com/siliconcompiler/siliconcompiler/tree/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/examples/sva_sby) (entry point `demo.py`)


#### `uniquify`

Uniquify parameterized modules for hardening.

A hardened macro has no parameters, so before hardening a parameterized module
we must discover which concrete parameter combinations it is instantiated with
across the design, generate a parameter-free variant for each (to harden), and a
parameterized wrapper that dispatches to them. This mirrors how lambdalib maps an
abstract cell onto hardened macros.

The whole lifecycle is driven by the `Uniquified` helper on the
heartbeat_top design (which depends on the parameterized heartbeat and
prescaler modules):

1. construct -- enumerate + generate, and register the new filesets,
2. build     -- harden each variant into a macro (needs EDA tools),
3. wireup    -- alias the wrappers in and inject the macros into the parent.

Requires

yosys, openroad, opensta, klayout; skywater130 (via lambdapdk)

Source

[examples/uniquify](https://github.com/siliconcompiler/siliconcompiler/tree/811ecd26e4ccb713d6db0aac2c102dbe1fa0e96c/examples/uniquify) (entry point `uniquify.py`)


---

Source: https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html

## Glossary

The following set of terms represents fundamental SiliconCompiler definitions used throughout the documentation.

The first three sections cover vocabulary specific to SiliconCompiler -- its
objects, its execution model, and its schema. The remaining sections cover the
standard semiconductor vocabulary that appears throughout the documentation and
in tool output, grouped by where you meet it: general hardware design, the ASIC
and FPGA implementation flows, verification, and the file formats that move data
between tools.


### SiliconCompiler concepts

checklist

A named set of requirements a design must satisfy, each one
either checked automatically against a recorded metric or signed
off by a person, with the evidence kept in the manifest. Turns
signoff from a conversation into an auditable object. See
Checklists.

dataroot

A named data source that file paths are resolved against.
A dataroot can be a local directory, a git repository, or a downloadable
archive -- see Data Sources for every kind -- and
is registered with set_dataroot(name, path, tag=None).
The optional tag is a version identifier for remote sources -- a git
commit, branch, or tag.
Storing files relative to a dataroot is what lets a design be
shared and rebuilt on another machine.

design

The hardware being compiled, described by a Design object: a
top-level module name plus the filesets that hold its
sources and constraints.
A design is independent of any one technology; pairing it with a
target is what makes it buildable.

fileset

A named group of input files belonging to a design or
library, such as rtl, sdc, or testbench.
Filesets let one design carry several alternative or complementary
sets of sources and select among them per run.

flow

The sequence of compilation steps to run, expressed as a
flowgraph. asicflow, synflow, and signoffflow are
examples. A flow describes what to do; a target chooses which
flow to use along with the technology to do it in.

KPI

Key Performance Indicator -- the handful of metrics a
run is actually judged on: area, power, timing slack, and error
counts. Every KPI is a metric, but a run records plenty of metrics that
nobody is judging it by.

library

A reusable collection of design data added to a project as a dependency.
A standard cell library (StdCellLibrary) supplies the
logic gates a synthesis tool maps to; other libraries package
IP, SRAMs, or I/O cells. Libraries are described with the same
filesets and dataroots as a
design.

mainlib

The primary standard cell library for an ASIC build, set
with set_mainlib(). Additional libraries added with add_asiclib()
supplement it during optimization.

metric

A quantitative result recorded by a task, such as cell area,
setup slack, or error count. Metrics are stored per
flowgraph node, which is why they are read with an explicit step
and index. See Working with Metrics.

PDK

Process Design Kit -- the technology data a foundry supplies for a
specific manufacturing process: layer definitions, design rules, device
models, and the tool setup files that go with them.
Open PDKs supported by SiliconCompiler are packaged in
lambdapdk.

record

Provenance data captured during a run -- tool versions, machine and user
information, timestamps -- stored alongside metrics so a
build can be audited and reproduced. See Execution Records.

target

A function that configures a project for a particular technology in one
call, selecting the PDK, the standard cell
libraries, the flows, and the physical
defaults that go with them. skywater130_demo is a target.

uniquify

To generate a separate, parameter-free copy of a parameterized module for
each distinct set of parameter values it is instantiated with, so each
copy can be hardened independently.
Automated by Uniquified; see
Hardening parameterized modules.


### Compilation model

edge

A directed connection between a tail node and head nodes in a flowgraph.

flowgraph

A directed acyclic graph specification of the hardware compilation.

flowgraph node

A node -- a single executable unit of a flowgraph, identified
by a (step, index) pair. Each node runs one task
with one tool, in its own directory under the job directory, and
carries its own metrics and records.
Nodes are connected by edges.
Not to be confused with the schema parameter field also called
node.

index

A variant of a step operating on identical input data.
Indices are what make a step run more than once in parallel -- to try
several tool configurations, or to explore a parameter sweep -- and the
results are compared to pick a winner.
A step run only once has index 0.

job

Execution of complete or partial compilation flowgraph.

manifest

JSON file representation of the SiliconCompiler schema.
See Directory structures for where
manifests are written during a run.

program

User specified program with one (or more) project instances.

project

Instance of SiliconCompiler Project class used to compile a design.

step

A discrete function in a flowgraph, such as synthesis, linting,
placement, or routing.

task

The unit of work a flowgraph node executes: a specific operation
performed by one tool, such as yosys/syn_asic or
openroad/route.

tool

Executable associated with a task in a flowgraph.


### Schema

default

Reserved SiliconCompiler schema key that can be replaced by any legal string.

dictionary

Associative array, ie. a collection of key-value pairs.

keypath

Ordered list of keys used to access schema parameters.

keys

Immutable strings used as index into dictionary.

keywords

Reserved strings that cannot be used as key names.

list

An ordered and mutable sequence of elements.

parameter

Schema leaf cell with a set of pre-defined key/value pairs.

schema

Nested dictionary of parameters.


### Hardware design

Vocabulary that applies to any hardware compilation, whether the destination is
an ASIC or an FPGA.

elaboration

Turning a design's sources into a resolved design hierarchy: reading
every file, binding each module instance to its definition, and
substituting parameter values. Runs ahead of synthesis, and is where missing
files, unresolved modules and parameter mistakes surface -- which is why
elaborationflow exists as a flow on its own.

HDL

Hardware Description Language -- a language for describing hardware
rather than a program's behavior over time. Verilog,
SystemVerilog and VHDL are the three in wide use, and a
design names its sources by fileset regardless of which
it uses. Higher-level frontends such as Chisel, Amaranth and Bluespec
generate one of them rather than replacing it; see
Hardware Frontends.

HLS

high-level synthesis

Compiling a description of what to compute -- C, or a machine learning
kernel -- into RTL, with the tool deciding the datapath, the state
machine and the schedule rather than the author writing them. What is
gained is that an algorithm becomes hardware without being rewritten;
what is given up is direct control over the microarchitecture, so results
depend heavily on how the input was optimized beforehand. SiliconCompiler
drives Bambu (see the C HLS frontend) and, through
MLIR, SODA Synthesizer (the SODA tutorial).

IP

Intellectual Property -- a reusable design block. Delivered either as
soft IP (RTL you synthesize yourself) or hard IP (a
hardened macro with fixed layout and timing views). Packaged in
SiliconCompiler as a library.

MLIR

A compiler infrastructure, part of the LLVM project, built around
reusable dialects -- self-contained sets of operations and types -- and
progressive lowering between them. A machine learning model enters as a
high-level dialect such as TOSA and is rewritten step by step down to
something a backend can consume, which is what makes it the substrate for
HLS front ends like soda-opt. See
the SODA tutorial.

netlist

A description of a circuit as instantiated components and the
connections between them, as opposed to the behavioral description in
RTL.

place-and-route

P&R

PnR

PNR

Placement and routing taken together, and normally run by
a single tool, because the two decisions constrain each other: a
placement is only a good one if what it implies can actually be routed.
Abbreviated P&R, PnR or PNR interchangeably -- tool documentation is not
consistent about which spelling it uses.

placement

Deciding where each cell in the netlist physically sits: inside
the floorplan for an ASIC, or on the fabric's fixed logic
sites for an FPGA. Runs after synthesis and before
routing, and largely fixes the wire lengths every later step has
to live with.

routing

Connecting placed cells -- drawing metal wires layer by layer within the
PDK's spacing rules on an ASIC, or configuring the
fabric's prefabricated interconnect on an FPGA. The last major
implementation step; on an ASIC its output is what DRC and
LVS check and what PEX measures.

RTL

Register Transfer Level -- a description of hardware in terms of a
clocked flow of data between registers, written in an HDL such as
Verilog, VHDL, or SystemVerilog. The usual
starting point of a compilation.

SoC

System on Chip -- a single chip carrying a whole system rather than one
function: one or more processors, memory, and the peripherals and
interconnect that tie them together. Built by integrating IP,
which is why an SoC design typically depends on several
libraries and instantiates
hardened macros such as
SRAMs. See Building an SoC.

SystemVerilog

An extension of Verilog adding stronger typing, interfaces,
classes, and the constrained-random and assertion constructs
most verification is written in today. Accepted anywhere Verilog is,
though tool support for the verification subset varies more than for
the synthesizable one.

synthesis

Translating RTL into a netlist of concrete cells --
standard cells for an ASIC,
LUTs and hard blocks for an FPGA -- while
optimizing for area, timing and power. The point at which a design stops
being technology-independent.

Verilog

The most widely used HDL, and the lingua franca of the
open-source tool flow: the language SiliconCompiler's built-in
flows assume unless told otherwise, and the output format
most higher-level frontends generate. Extended by
SystemVerilog.

VHDL

An HDL with a stricter type system than Verilog, common
in European and aerospace/defense design. Supported by SiliconCompiler
where the underlying tool supports it -- fewer open-source tools do than
for Verilog, so a VHDL design may need a different flow.


### ASIC design

ASIC

Application-Specific Integrated Circuit -- a chip whose logic is fixed at
manufacture. The counterpart to an FPGA: far better area, power
and speed, paid for with a months-long manufacturing cycle and a mask set
that cannot be changed afterwards. An ASIC build is driven by the
ASIC project class, which pairs a design with a
PDK and a mainlib.

blackbox

Telling a tool to treat a module as an opaque interface with no contents,
so it is neither elaborated nor synthesized. This is how a
hardened macro is wired into a parent design: the parent sees
only the ports, and the physical implementation comes from the macro's
own views. See Instantiating a hardened module.

clock tree synthesis

CTS

Building the buffered network that distributes a clock to every register,
balancing arrival times so skew stays inside what STA will
accept. Runs between placement and routing.

corner

A named combination of process, voltage and temperature at which a design
is analyzed. A cell that is fast in one corner is slow in another, so
timing is checked in several -- typically a slow corner for setup and a
fast one for hold. A library ships one Liberty file per
corner.

delay model

How a Liberty file expresses cell delay: nldm (lookup tables)
or ccs (current source models -- slower to read, more accurate).
A library groups its timing filesets by
(corner, delaymodel) and a target selects one with
set_asic_delaymodel(). See
Timing models and the delay model.

DFM

Design for Manufacturability -- layout changes that raise yield beyond
what the DRC rules strictly demand: extra spacing where there is
room, redundant vias, fill for uniform metal density. Passing DRC says a
layout is legal; DFM is about how many of the manufactured die work.

DFT

Design for Test -- logic added so manufactured parts can be tested: scan
chains that stitch registers into a shift register, compression logic,
and built-in self-test for memories. Costs area and some timing, and is
what makes it possible to tell a good die from a bad one after
tapeout.

DRC

Design Rule Check -- verification that a layout obeys the geometric
rules the foundry requires for manufacturability.

floorplan

The physical plan of a block before detailed implementation: die and core
area, where macros and I/O sit, and the power grid.
Set through the project's area constraints -- see
Floorplanning -- and settled early because
placement and routing both have to work inside it.

hardened macro

hard macro

A block that has been compiled all the way to a physical implementation
and is reused as a fixed, pre-built component -- an abstract layout view
plus timing models -- rather than being resynthesized with the parent.
Hardening gives predictable timing and area at the cost of flexibility: a
hardened macro is a concrete netlist and therefore has no parameters.
See Instantiating a hardened module.

LVS

Layout Versus Schematic -- verification that the manufactured layout is
electrically identical to the netlist it was built from.

macro

A block placed in the floorplan as a unit rather than synthesized
along with its parent -- an SRAM, a PLL, an analog block, or a
hardened macro of your own. Macros are placed before
standard cells, because everything else has to
fit around them.

PEX

Parasitic Extraction -- computing the resistance and capacitance
introduced by the physical wiring, so that timing analysis can account
for real interconnect delay rather than estimates. Its output is a
SPEF file.

scenario

A named timing analysis condition: which library corner to
analyze at, which parasitic corner to use, and which checks (setup,
hold) to run. A target defines one or more with
constraint.timing.make_scenario(), and STA runs against all
of them.

signoff

The final verification pass a design must clear before tapeout --
DRC, LVS, STA at every corner, and
whatever else the foundry demands -- run with signoff-quality tools and
decks rather than the faster in-flow approximations. signoffflow is
the built-in signoff flow; see
Checklists for recording the results.

slack

How much time a path has to spare against its constraint: positive means
it meets timing, negative means it misses by that much. STA
reports it as worst (WNS) and total (TNS) negative slack, recorded as
metrics such as setupwns and holdtns.

SRAM

Static Random Access Memory -- on-chip memory built from a dense,
specially drawn bit cell rather than from standard cells. Too regular and too area-critical to synthesize, so an
SRAM arrives as a hardened macro from a memory compiler or the
PDK and is placed in the floorplan as a
macro. See Building an SoC with a memory.

stackup

The set of metal layers a process offers for routing, named by
how many there are and how they are built -- "12M" for a twelve-metal
stack. Set on the PDK with set_stackup(). Every
library used in a build has to be characterized for the same
stackup, since the abstract views in LEF are drawn on those
layers.

standard cell

A pre-designed, pre-characterized logic gate or flip-flop with a fixed
height, drawn from a standard cell library. Synthesis maps a
design onto these cells, and placement arranges them in rows.

STA

Static Timing Analysis -- verifying that a design meets its timing
constraints by analyzing every path, without simulating any vectors.

tapeout

Sending the final layout database -- usually GDSII, sometimes
OASIS -- to the foundry, the point after which nothing can change
without a new mask set. What signoff and the
checklist machinery exist to gate.

utilization

How much of the core area the cells actually occupy, as a percentage --
also called density, and set with constraint.area.set_density().
The central floorplanning trade-off: pack too tightly and there is no
room left to route; leave too much slack and the die is larger
and more expensive than it needs to be. Typical starting points are
40--70%, lower for congested designs.


### FPGA design

bitstream

The configuration file loaded onto an FPGA to make it behave as
your design. It is the FPGA flow's final output, in the role
GDSII plays for an ASIC -- with the difference that you can
produce one, load it, and change your mind, which is why FPGA builds are
measured in minutes rather than months.

FPGA

Field-Programmable Gate Array -- a chip whose logic is configured after
manufacture by loading a bitstream, rather than fixed at tapeout.
The compilation flow is the same shape as an ASIC's, but targets a
specific device instead of a PDK.

LUT

Look-Up Table -- the small programmable truth table that is an
FPGA's basic logic element, in the role a standard cell
plays in an ASIC. FPGA resource reports are counted in LUTs, and a design
"fits" when it needs no more than the device has.


### Simulation and verification

assertion

A property that must always hold, written alongside the design or in the
testbench -- typically in SystemVerilog Assertions (SVA).
Checked continuously during simulation, and provable outright by
formal verification.

formal verification

Reasoning mathematically about a model of the design under stated
assumptions, rather than exercising it with the stimulus a
testbench happens to apply. Covers bounded model checking (is
this true for the first N cycles?), unbounded proof (is it true in every
reachable state?) and equivalence checking such as LEC.
Complements simulation instead of replacing it: simulation finds the bugs
you thought to look for, formal finds the ones you did not -- within
whatever the assumptions and the bound allow.

LEC

Logical Equivalence Check -- formal proof that two representations of a
design, typically the RTL and a synthesized netlist,
implement identical logic. Catches the class of bug where an
optimization silently changed behavior.

lint

Static analysis of RTL for mistakes a compiler will accept but a
designer did not intend -- width mismatches, undriven or unused signals,
incomplete sensitivity lists. Needs no technology data and no EDA tool
beyond the linter itself, which makes it the cheapest check to run first.
lintflow is the built-in flow.

testbench

Code that drives a design under simulation and checks what comes back.
In SiliconCompiler it lives in its own fileset beside the
RTL, so the same design can carry several -- one per
simulator, or one per scenario -- and a run selects among them.

waveform

The recorded history of every signal in a simulation, written as a
VCD or FST file and read in a viewer such as Surfer or GTKWave.


### File formats

DEF

Design Exchange Format -- a text format describing the physical
implementation of a design: component placement, routing, and pin
locations. Paired with LEF, which describes the cells being
placed.

GDSII

GDS

The standard binary layout format, and the usual final output of an ASIC
flow: the file sent to the foundry for manufacturing.
(OASIS is a more modern alternative with the same role.)

LEF

Library Exchange Format -- a text format describing the abstract physical
view of cells and macros: outline, pin positions, and blockages, without
the full internal layout. Enough for a placer and router to work with.

Liberty

The .lib timing and power format for a standard cell
library: per-cell delay, transition, setup/hold and power tables,
characterized for one corner and one delay model. What
synthesis and STA read to know how fast a cell is.

SDC

Synopsys Design Constraints -- the de facto standard format for
specifying timing constraints: clock definitions, I/O delays, and
exceptions.

SDF

Standard Delay Format -- per-instance delays written out after
implementation and back-annotated onto a gate-level simulation, so the
simulator models real timing instead of unit delays. The bridge between
STA and simulation-based timing verification.

SPEF

Standard Parasitic Exchange Format -- the text format carrying the
resistance and capacitance values PEX extracts, read back by
STA so timing reflects real interconnect. See
Calibrating the parasitic estimate (PEX) for calibrating a pre-route estimate against a
golden SPEF.

VCD

Value Change Dump -- the standard waveform format, a record of every
signal transition in a simulation. Useful twice: for looking at what the
design did, and as switching activity for power analysis, which is far
more accurate than the default assumptions.


---

Source: https://docs.siliconcompiler.com/en/latest/user_guide/faq.html

## Frequently Asked Questions

Questions people actually ask, drawn from the issue tracker and the
[Help (Q&A) discussions](https://github.com/siliconcompiler/siliconcompiler/discussions/categories/help-q-a).

If you are looking for "which method call does X", that is the companion page:
[How do I...?](https://docs.siliconcompiler.com/en/latest/user_guide/howto.html#howto).


### Getting started


#### Do I need to install EDA tools, or can I just try it?

You can try it with nothing but Docker and `pip install siliconcompiler`, by
running the tools in containers:

```bash
python -m siliconcompiler.demos.asic_demo -scheduler docker
```

Running them natively needs four tools -- [Yosys](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/tools.html#tool-yosys),
[OpenROAD](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/tools.html#tool-openroad), [OpenSTA](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/tools.html#tool-opensta) and
[KLayout](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/tools.html#tool-klayout). It is the better answer if you expect to keep
building, but it is not a five-minute detour, so it is not the one to start on.
[Where the compilation runs](https://docs.siliconcompiler.com/en/latest/user_guide/quickstart.html#choose-run-mode) compares the two, and
[Using SiliconCompiler with Docker](https://docs.siliconcompiler.com/en/latest/user_guide/docker.html#docker) sets the container path up.


#### Does my design leave my machine?

Not on a local or [Docker](https://docs.siliconcompiler.com/en/latest/user_guide/docker.html#docker) run -- both read and write your working
directory and nothing else.

It does on a [remote run](https://docs.siliconcompiler.com/en/latest/user_guide/remote_processing.html#remote-processing), which uploads the design to
the server named in your `credentials` file. SiliconCompiler does not host a
server for you, so that is a machine you or your organization operates, under
whatever terms that operator sets. You are responsible for having the right to
distribute any IP contained in what you upload.


#### Can I use SiliconCompiler on Windows?

The package installs and runs on Windows, and is tested there on every commit,
but that testing does not cover running EDA tools. There are no tool install
scripts for Windows and local flows are not supported on it.

From Windows, use the [Docker image](https://docs.siliconcompiler.com/en/latest/user_guide/docker.html#docker), WSL, or a
[remote run](https://docs.siliconcompiler.com/en/latest/user_guide/remote_processing.html#remote-processing).
KLayout is worth installing natively so [sc-show](https://docs.siliconcompiler.com/en/latest/reference_manual/apps.html#app-sc-show) can display
results. See [External Tools](https://docs.siliconcompiler.com/en/latest/user_guide/installation.html#external-tools).


#### Which PDK should I start with?

**Sky130.** It is what the [ASIC demo](https://docs.siliconcompiler.com/en/latest/user_guide/installation.html#asic-demo) and the
[Quickstart](https://docs.siliconcompiler.com/en/latest/user_guide/quickstart.html#quickstart-guide) use, so it is the best-trodden path and the
one most likely to work first time.

Every open [PDK](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-PDK) SiliconCompiler supports is packaged in
[lambdapdk](https://github.com/siliconcompiler/lambdapdk) and listed under
[pre-defined PDKs](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/pdks.html#builtin-pdks). Maturity varies, and the catalogue does
not yet say by how much; if a target does not behave, searching the
[discussions](https://github.com/siliconcompiler/siliconcompiler/discussions)
for its name is usually faster than debugging it.


### Understanding the tool


#### What is the difference between a target, a flow and a PDK?

A [PDK](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-PDK) is foundry data. A [flow](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-flow) is the sequence of steps to run. A
[target](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-target) is a single function that selects both -- PDK, standard cell
[libraries](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-library), flows and physical defaults -- so one call
configures a project for a technology:

```python
from siliconcompiler.targets import skywater130_demo

skywater130_demo(project)     # picks the PDK, libraries and flows in one call
```

The [glossary](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#glossary) defines these and the rest of the vocabulary.


#### I have a new PDK, library or tool. Where does it go?

Three answers depending on what it is: open PDKs go to `lambdapdk`, closed or
proprietary data goes in a package of your own and never into this repository,
and tool drivers, flows and targets go in-tree.

[Where your module belongs](https://docs.siliconcompiler.com/en/latest/development_guide/contribution.html#module-placement) has the decision table,
and [Packaging an External Library](https://docs.siliconcompiler.com/en/latest/development_guide/external_libraries.html#dev-external-libraries) covers the
proprietary case, including how to reference foundry decks out-of-band so they
never enter a published package.


#### What is the difference between the package version and the schema version?

They are versioned independently. The package is currently 0.38.11; the
[schema](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-schema) has its own version (0.57.0 at the time of writing) recorded in
every [manifest](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-manifest).

That is what lets SiliconCompiler tell you a manifest was written by an
incompatible schema. When one does not load, the
[Schema Changes](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#schema-changelog) appendix records what was added,
renamed or removed at each schema version.


#### Should I write `set()`/`get()` or the typed accessors?

Prefer the typed accessor whenever one exists; use a keypath when there is no
accessor, which mostly means reading [metrics](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-metric) and
[records](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-record). Neither is deprecated -- see
[Working with the Schema](https://docs.siliconcompiler.com/en/latest/user_guide/data_model.html#schema-access).


#### How do I set the die area, and what happens if I don't?

`project.constraint.area.set_dieoutline(500, 500, coremargin=10)` -- width and
height in µm, on the **project**. Set nothing and the floorplanner sizes the die
from a [utilization](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-utilization) target instead -- 40% in every demo target, which is
why the [quickstart](https://docs.siliconcompiler.com/en/latest/user_guide/quickstart.html#quickstart-guide) never mentions a die. That holds
until the design contains a [macro](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-macro) or a pad ring, at which point the size
has to be chosen with those in it.

Constraints hang off the project rather than the [`Design`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Design), because a die
size describes one compilation while a design is meant to be reused across
several. There is no `option,floorplan` keypath on either -- it has never
existed in any release, so code that sets one was invented rather than ported.
[Floorplanning](https://docs.siliconcompiler.com/en/latest/user_guide/howto.html#howto-floorplanning) has the rest: macro halos and
placements, pin sides, and pad rings.


#### Where does SiliconCompiler put things?

Build artifacts go under `build/<design>/<jobname>/`; downloaded data,
settings and credentials live in `~/.sc`.
[Directory structures](https://docs.siliconcompiler.com/en/latest/user_guide/directories.html#directory-structures) maps both.


### When things go wrong


#### My run failed. Where are the logs?

In the node directory of the step that failed,
`build/<design>/<jobname>/<step>/<index>/`. There are two logs and they answer
different questions:

- `<step>.log` -- what the tool printed. Start here when the tool failed.
- `sc_<step>_<index>.log` -- what SiliconCompiler did around it: which files
  it resolved, which parameters it passed.

`<step>.errors` and `<step>.warnings` hold the lines matched as errors and
warnings, and are what the [`[metric,errors]`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-project-metric-errors) and
[`[metric,warnings]`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-project-metric-warnings) metrics count. See
[Inside a node directory](https://docs.siliconcompiler.com/en/latest/user_guide/directories.html#directory-structures).


#### How do I file a useful bug report?

Use [sc-issue](https://docs.siliconcompiler.com/en/latest/reference_manual/apps.html#app-sc-issue), which packages a single failing node and its
inputs into a standalone, runnable test case:

```bash
sc-issue -cfg build/<design>/<jobname>/<step>/<index>/inputs/<design>.pkg.json
```

A failing run prints this command with the paths filled in. Attaching its output
saves a round trip of questions.


#### What is the difference between the `drvs` and `drcs` metrics?

They count different kinds of violation, not the same violations at different
stages.

[`[metric,drvs]`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-asic-metric-drvs) -- **electrical and connectivity** rule violations.
[OpenROAD](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/tools.html#tool-openroad) sums max slew, max capacitance and max fanout
violations, floating and overdriven nets, and antenna violations;
[OpenSTA](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/tools.html#tool-opensta) counts its own design rule violators; a
[LEC](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-LEC) task records equivalence mismatches here. No geometry is
involved.

[`[metric,drcs]`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-asic-metric-drcs) -- **geometric** design rule violations, from a tool
that checks geometry against the [PDK](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-PDK) rules.
[Detailed routing](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/tools.html#tool-openroad) reports these as it routes, and a
dedicated checker -- [Magic](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/tools.html#tool-magic) or [KLayout](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/tools.html#tool-klayout)
DRC -- reports them in [signoff](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-signoff). [Netgen](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/tools.html#tool-netgen) also records
[LVS](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-LVS) errors under this metric.

So `drcs` is not exclusively a signoff number:
[asicflow](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/flows.html#schema-siliconcompiler-flows-asicflow-asicflow) reports it from
detailed routing. A clean `drcs` there means the router believes the layout is
legal, which is a weaker statement than a signoff DRC run in
[signoffflow](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/flows.html#schema-siliconcompiler-flows-signoffflow-signoffflow) using
the foundry deck.

See [Working with Metrics](https://docs.siliconcompiler.com/en/latest/development_guide/metrics.html#dev-metrics) for how metrics are recorded and
compared, and the [metric schema](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#schema) for the full list.


#### How do I run only part of the flow, or re-run one step?

Use [`[option,from]`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-project-option-from), [`[option,to]`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-project-option-to) and [`[option,prune]`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-project-option-prune).
A re-run resumes by default, reusing nodes that already completed, so restarting
from a step is enough to re-run it and everything after it:

```python
project.option.add_from('synthesis')     # start here, reusing earlier results
project.option.add_to('route.detailed')  # and stop here
```

`from` and `to` take step names only, not indices -- deliberately, to keep
them simple. To drop individual nodes, use `prune`. To discard previous
results entirely, see [`[option,clean]`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-project-option-clean) in
[Directory structures](https://docs.siliconcompiler.com/en/latest/user_guide/directories.html#directory-structures).


#### Is vector-based power estimation supported?

Yes. If a [VCD](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-VCD) is available, OpenSTA annotates switching activity from
it, so power numbers reflect real toggle rates rather than default assumptions.
Add the [waveform](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-waveform) to a fileset and the timing task picks it up:

```python
with design.active_fileset("vcd"):
    design.add_file("sim.vcd")
```

A VCD produced by an earlier node in the same flow is picked up automatically.
Where the VCD hierarchy does not start at the design top, set the
`power_activities` variable on the OpenSTA timing task to map a scope to the
fileset holding the waveform.


### Doing more


#### Can I run this in CI?

Yes -- a build is an ordinary Python script, so anything that runs Python runs
it. Two things make it practical:

- Point [`[option,cachedir]`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-project-option-cachedir) at a cached directory so [PDKs](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-PDK)
  and [libraries](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-library) are not re-downloaded on every job -- see
  [the data cache](https://docs.siliconcompiler.com/en/latest/user_guide/directories.html#sc-home).
- Use [sc-install](https://docs.siliconcompiler.com/en/latest/reference_manual/apps.html#app-sc-install) in the image build, or the
  [Docker image](https://docs.siliconcompiler.com/en/latest/user_guide/docker.html#docker), rather than installing tools per job.

SiliconCompiler's own CI does both -- it runs inside a prebuilt tools container
and restores the data cache between jobs. The workflows under
`.github/workflows/` are a working reference.


#### Which commercial EDA tools are supported?

SiliconCompiler supports a number of commercial tools, but those drivers cannot
be published for NDA reasons, so they are not in this repository and are not in
the [tool catalogue](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/tools.html#builtin-tools). If you need commercial tool support,
raise it on the
[discussions board](https://github.com/siliconcompiler/siliconcompiler/discussions).

Nothing stops you writing your own driver for a proprietary tool and keeping it
in your own package -- see [Setting up a Tool](https://docs.siliconcompiler.com/en/latest/development_guide/tools.html#dev-tools) and
[Packaging an External Library](https://docs.siliconcompiler.com/en/latest/development_guide/external_libraries.html#dev-external-libraries).


#### I have an old script that uses `Chip()`. How do I port it?

`Chip` was removed in v0.35.0 and split into a [design](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-design) and a project.
[Migrating from the Chip API](https://docs.siliconcompiler.com/en/latest/user_guide/migration.html#migration-guide) maps the old names onto the
new ones, method by method, and shows the same build written both ways.

If a code assistant wrote the script you are porting, this is the most likely
explanation: the `Chip` API is what most of the material written about
SiliconCompiler still describes.


### Still stuck?

If your question is not here, the
[Help (Q&A) discussions](https://github.com/siliconcompiler/siliconcompiler/discussions/categories/help-q-a)
are actively answered, and questions asked there are where this page comes from.


---

Source: https://docs.siliconcompiler.com/en/latest/user_guide/howto.html

## How do I...?

A task-oriented reference: the shortest correct way to do common things.
Feel free to suggest new entries.

For questions rather than method calls -- what a target is, whether the public
server is confidential, why a run failed -- see the
[Frequently Asked Questions](https://docs.siliconcompiler.com/en/latest/user_guide/faq.html#faq).

Entries are grouped by what you are trying to do, roughly in the order people
need them.


### Set up a build


#### Create a design object

```python
from siliconcompiler import Design
design = Design('<design>')
```


#### Dataroot: register a new source of files

```python
design.set_dataroot("<name>", "<path>", tag="<version>")
```

The path may be a local directory, a git URL, or an archive URL. `tag` applies
to remote sources only, and is a git commit, branch, or tag. See
[dataroot](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-dataroot), and [Data Sources](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/resolvers.html#builtin-resolvers) for every scheme a
path can take.


#### Dataroot: authenticate against a private repository

Put the token in the environment variable for its host, and keep it out of the
script:

```bash
export GITHUB_TOKEN=<token>   # github.com
export GITLAB_TOKEN=<token>   # gitlab.com
export GIT_TOKEN=<token>      # a git repository or GitLab instance on any other host
export HTTPS_TOKEN=<token>    # an https:// archive on any other host
```

A `git+ssh://` dataroot needs no token: it uses this machine's SSH keys, and is
the better choice where you can use it. Each scheme's entry in [Data Sources](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/resolvers.html#builtin-resolvers) lists the variables it reads and how it sends the token, with
the full table for `git+https://` under [git](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/resolvers.html#resolver-git). Every variable
also has a [dataroot-specific form](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/resolvers.html#resolver-tokens), for when two dataroots
on one host need different tokens.

A private repository does not need the `+private` marker (`git+ssh+private://`,
`file+private://` and the rest). The marker says a source must never leave this
machine: a [remote run](https://docs.siliconcompiler.com/en/latest/user_guide/remote_processing.html#remote-processing) is not to upload it, so the
SiliconCompiler server has to hold its own copy. Mark a source `+private` only if
it must stay here; a repository this machine can fetch needs no marker.


#### Dataroot: fetch from S3 or an S3-compatible store

Install the `s3` extra (`pip install "siliconcompiler[s3]"`), then name one
archive object, or a prefix whose `<tag>.tar.gz` is the archive:

```python
design.set_dataroot("<name>", "s3://<bucket>/<key>.tar.gz", tag="<version>")
design.set_dataroot("<name>", "s3://<bucket>/<prefix>/", tag="<version>")
```

The object is unpacked as an `https://` archive is, in the same formats.

Credentials come from the AWS chain, as for the AWS CLI: `AWS_PROFILE`,
`AWS_ACCESS_KEY_ID` and `AWS_SECRET_ACCESS_KEY`, `~/.aws/credentials`, SSO,
or an instance role. With none found, the request goes unsigned, which reads a
public bucket. An `s3+private://` source requires credentials instead.

For a store other than AWS -- MinIO, Ceph, Cloudflare R2 -- set its endpoint, and
its keys as the AWS variables:

```bash
export AWS_ENDPOINT_URL_S3=https://<account>.r2.cloudflarestorage.com
export AWS_ACCESS_KEY_ID=<key>
export AWS_SECRET_ACCESS_KEY=<secret>
```


#### Dataroot relative to my current file

```python
design.set_dataroot('<name>', __file__)
```


#### Create an ASIC project object

```python
from siliconcompiler import ASIC
project = ASIC(design)
```


#### Add files to a fileset

Group a design's files into named [filesets](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-fileset) and register them
against a [dataroot](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-dataroot) so the paths survive being run from elsewhere. The
[fileset](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-fileset) and filetype are inferred from the extension:

```python
design.set_dataroot("mydesign", __file__)

with design.active_dataroot("mydesign"), design.active_fileset("rtl"):
    design.set_topmodule("mydesign")
    design.add_file("rtl/mydesign.v")        # -> fileset "rtl", type verilog

with design.active_dataroot("mydesign"), design.active_fileset("sdc"):
    design.add_file("constraints/mydesign.sdc")

with design.active_dataroot("mydesign"), design.active_fileset("testbench"):
    design.add_file("tb/mydesign_tb.sv")
```

Pass `filetype=` explicitly when the extension does not imply it. A design may
carry as many filesets as you like -- only the ones you activate are compiled.


#### Activate filesets

Choose which of the design's filesets this run compiles:

```python
project.add_fileset(["rtl", "sdc"])     # ignores "testbench"
```

This is how one design serves several flows: an ASIC build activates `rtl` and
`sdc`, while a simulation activates `rtl` and `testbench`.


#### Run a compilation

```python
project.run()
```


### See what happened


#### Display my layout

```python
project.show()
```


#### Display a previous run from the command line

```bash
sc-show -design <name>
```


#### Change the logging level, or quieten the output

Two different things control how much you see.

SiliconCompiler's own messages come from a standard Python logger, so set its
level directly. There is no `option` for this:

```python
project.logger.setLevel("DEBUG")     # or "INFO" (the default), "WARNING", "ERROR"
```

Tool output is separate. It is summarised by default; set
[`[option,quiet]`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-project-option-quiet) to suppress it entirely, or unset it to see everything
the tool prints:

```python
project.option.set_quiet(True)                              # whole run
project.option.set_quiet(True, step="synthesis", index="0")  # one node
```

Either way the full tool log is always written to
`<step>.log` in the node directory -- see
[Directory structures](https://docs.siliconcompiler.com/en/latest/user_guide/directories.html#directory-structures).


#### Use the manifest from a previous run

```python
from siliconcompiler import Project

project = Project.from_manifest("build/<design>/<jobname>/<design>.pkg.json")
```


### Control a run


#### Run a build script's targets without editing it

A build script usually holds more than one thing you might want to do -- lint,
synthesize, run the full flow, sweep a parameter. Writing each as a function and
editing the bottom of the file to pick one gets old quickly.

[smake](https://docs.siliconcompiler.com/en/latest/reference_manual/apps.html#app-smake) runs those functions by name. Point it at a `make.py`
and every top-level function becomes a target, with its arguments turned into
command-line switches and its docstring into help text:

```bash
smake --help                        # what this script can do
smake syn                           # call syn()
smake asic --fileset rtl.memory     # call asic(fileset="rtl.memory")
```

Nothing special is needed in the script -- these are ordinary functions:

```python
def syn(fileset: str = "rtl", pdk: str = "freepdk45"):
    """Synthesis only, the quickest check."""
    ...
```

Functions whose names start with `_` are helpers, not targets, and are left
out of `--help`. `smake -C <dir>` runs a script in another directory, and
`smake -f <file>` uses a file that is not called `make.py`.

This is why several [examples](https://docs.siliconcompiler.com/en/latest/user_guide/examples.html#examples) ship a `make.py` rather than a
script with one entry point: `examples/heartbeat/make.py` exposes ten targets
covering every project type. `python3 make.py` still works, but runs whatever
the `__main__` block chooses -- usually one of the targets, not the one you
meant.


#### Run only part of the flow

A re-run resumes by default: nodes that already completed are reused, so
restarting from a step re-runs it and everything downstream.

```python
project.option.add_from("synthesis")    # start here, reusing earlier results
project.option.add_to("synthesis")      # and stop here
```

[`[option,from]`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-project-option-from) and [`[option,to]`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-project-option-to) take **step names only**, not
indices -- a deliberate choice to keep them simple. To drop individual
(step, index) nodes, use [`[option,prune]`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-project-option-prune):

```python
project.option.add_prune(("floorplan.init", "0"))
```


#### Start a fresh run

```python
project.option.set_clean(True)
```


#### Start a fresh run and keep the old one

```python
project.option.set_clean(True)
project.option.set_jobincr(True)
```


#### Start a fresh run using the previous run information

```python
project.option.set_clean(True)
project.option.set_jobincr(True)
project.option.add_from('floorplan')
```


#### Control how much of the machine a run uses

Two job-wide limits, both defaulting to the number of available CPU cores:

```python
project.option.scheduler.set_maxnodes(4)     # concurrent nodes in the job
project.option.scheduler.set_maxthreads(8)   # threads available to each task
```

[`[option,scheduler,maxnodes]`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-project-option-scheduler-maxnodes) bounds how many
[flowgraph nodes](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-flowgraph-node) run at once;
[`[option,scheduler,maxthreads]`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-project-option-scheduler-maxthreads) bounds each task's own threading. On a
machine you are still using for other work, lowering both is usually what you
want -- otherwise a wide flow will happily take every core.

To override the thread count for one task rather than the whole job:

```python
from siliconcompiler.tools.yosys.syn_asic import ASICSynthesis

ASICSynthesis.find_task(project).set_threads(4, step="synthesis", index="0")
```


#### Build directory

```python
project.option.set_builddir("/path/to/build")
```

See [Directory structures](https://docs.siliconcompiler.com/en/latest/user_guide/directories.html#build-directory) for what a run writes there.


#### Cache directory

```python
project.option.set_cachedir("/path/to/cache")
```

Defaults to `~/.sc/cache`, which holds both the downloaded data sources and the
caches the tools keep for themselves; see [the SC home directory](https://docs.siliconcompiler.com/en/latest/user_guide/directories.html#sc-home).


#### Preserve options across sessions

Options such as scheduler information can be preserved [across sessions](https://docs.siliconcompiler.com/en/latest/development_guide/options.html#user-settings):

```python
project.option.write_defaults()
```


#### Check my setup before running

```python
project.check_manifest()
```


### Floorplanning

Floorplan constraints belong to the **project**, not to the design: a die size
is a property of one compilation, while a [`Design`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Design) is meant to be reused
across several. They all hang off `project.constraint` -- `area` for the die
and core, `component` for macros, `pin` for I/O.

> **Warning**
> There is no `option,floorplan` keypath, on the design or anywhere else.
> `design.set('option', 'floorplan', 'diearea', ...)` is not an older
> spelling of something that moved: no release has ever had it, so code that
> contains it was invented rather than ported. The calls below are the real
> ones, and every one of them is on the project.


#### Set the die size

```python
project.constraint.area.set_dieoutline(500, 500, coremargin=10)
```

Width and height in µm, with the die's lower-left corner at the origin.
`coremargin` is the gap between the die edge and the core the standard cells
are placed in -- room for the power ring and the I/O.

Give the core size instead when what you know is how much room the logic needs;
the die is grown outwards from it by the margin:

```python
project.constraint.area.set_coreoutline(480, 480, coremargin=10)
```

Only one of the two is needed -- whichever is missing is derived from the other
and the margin -- but setting both is allowed, and then both are used as given.
For an outline that is not a rectangle, pass the vertices to
[`ASICAreaConstraint.set_diearea()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICAreaConstraint.set_diearea); the core is offset edge by edge so it
follows the die rather than its bounding box.


#### Let the tool pick the die size

Set neither area and the floorplanner sizes the die from a [utilization](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-utilization)
target and an aspect ratio. Every demo target already sets those -- 40% and a
small core margin -- which is why the [quickstart](https://docs.siliconcompiler.com/en/latest/user_guide/quickstart.html#quickstart-guide) never
mentions a die. Change them with:

```python
project.constraint.area.set_density(40, aspectratio=1.0, coremargin=10)
```

Density is the percentage of the core the cells occupy after synthesis; 40--70%
is the usual range, lower for congested designs. Both it and the aspect ratio
are ignored once a die or core area is given.

Automatic sizing is fine until the design contains something the tool cannot
size around. A [macro](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-macro) needs a die chosen with it in mind, and a pad ring
needs one it can be drawn against -- `init_floorplan` refuses to size a ring
from density, because the ring is placed at absolute coordinates and a die
picked afterwards would not line up with it.


#### Place a macro, or keep the placer away from one

Component constraints are made by instance name, and the name may be a glob:

```python
sram = project.constraint.component.make_component("*sram*memory")
sram.set_halo(5.0, 5.0)         # placement keepout around it, in um
sram.set_placement(100, 250)    # pin it down instead of letting the tool choose
sram.set_rotation("R90")
```

A halo on its own is usually enough -- it stops standard cells crowding the
macro's pins, which is the common failure. Fixing the placement starts to matter
once several macros have to share an edge. [Instantiating a hardened module](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/hardened.html#hardened-modules) covers getting the macro into the build in the first place.


#### Put a pin on a particular side

```python
project.constraint.pin.make_pinconstraint("clk").set_side("west")
```

Sides are `left`/`west`, `top`/`north`, `right`/`east` and
`bottom`/`south`. A bus is constrained as a unit rather than a pin at a
time, which is what keeps its order along the edge:

```python
project.constraint.pin.make_buspinconstraints(
    [f"data[{i}]" for i in range(32)], side="north", pitch=2.0)
```

[`ASICPinConstraints.make_buspinconstraints()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICPinConstraints.make_buspinconstraints) documents how `pitch`,
`side_width`, `center` and `side_offset` divide up an edge: one of the
first two sets the spacing, one of the last two sets where the bus sits.


#### Wrap a design in an IO pad ring

[Implementing an IO pad ring](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/padring.html#padring-tutorial) walks through this end to
end, and `examples/padring` is the working design it builds. In short, four
pieces are involved:

1. **The ring in RTL.** Depend on lambdalib's pad ring generator rather than
  naming technology cells, and describe the cell order per side in a
  `CELLMAP`. `lambdalib` installs with `lambdapdk`, so it is already
  present:

  ```
  from lambdalib.padring import Padring
  ...
  self.add_depfileset(Padring(), "rtl")
  ```
2. **A top level whose ports are the pads.** Name them for what they carry, and
  declare the direction each is really used in -- the ring's cells are all
  bidirectional, but a pin on the finished part is not, and only the supplies are
  genuinely `inout`. Underneath, the logic talks to the ring through
  `din`/`dout`/`oen`/`ie` and a technology configuration bus per side,
  never touching a pad cell, which is what keeps it portable between
  technologies.
3. **Physical construction in TCL**, in filesets of your own on the design.
  These names are yours rather than reserved ones, and nothing looks for them
  until step 4 below names them:

  ```python
  with self.active_dataroot("mydesign"), self.active_fileset("padring.sky130"):
      self.add_file("openroad/padring.tcl")
  # likewise "pdn.sky130" and "globalconns.sky130"
  ```
4. **The hooks that point the tasks at those filesets.** These are task
  variables, not schema keys:

  ```python
  InitFloorplanTask.find_task(project).add_openroad_padringfileset("padring.sky130")
  PowerGridTask.find_task(project).add_openroad_powergridfileset("mydesign", "pdn.sky130")
  for task in APRTask.find_task(project):
      task.add_openroad_globalconnectfileset("mydesign", "globalconns.sky130")
  ```

  These three lines are the end of the setup rather than the whole of it --
  each names a fileset that has to have been created first, and copying them
  alone gets you three hooks pointing at nothing. The pad ring hook takes only
  a fileset name because a pad ring is always read from the design being built;
  the power grid and global connect hooks take the owning library first, since
  those two are often supplied by a library instead -- when neither is set,
  both are collected from the ASIC libraries in the build, and setting one
  turns that fallback off.

The TCL itself places pads into IO rows, then corners, then fill, then calls
`connect_by_abutment` so the supply and configuration signals pass between
neighbouring cells, then adds bond pads. The order matters. Use
`-connect_to_pads` on the core power rings so the core is fed from the ring.

These are OpenROAD commands rather than SiliconCompiler ones, so their arguments
are documented upstream: [pad](https://openroad.readthedocs.io/en/latest/main/src/pad/README.html) for `place_pads`, `place_corners`,
`place_io_fill`, `connect_by_abutment` and `place_bondpad`, and
[pdn](https://openroad.readthedocs.io/en/latest/main/src/pdn/README.html) for `define_pdn_grid`, `add_pdn_ring`, `add_pdn_stripe` and
`add_global_connection`.

A die with a ring is usually **pad limited**: its size is set by how many pads
must fit around the edge, not by the logic inside. Set it explicitly --
`init_floorplan` will not size a ring from density, because the ring is placed
at absolute coordinates and a die chosen afterwards would not line up with it.


### Extend SiliconCompiler


#### Set up a new tool

See [Tools](https://docs.siliconcompiler.com/en/latest/development_guide/tools.html#dev-tools)


#### Set up a new flow

See [Flows](https://docs.siliconcompiler.com/en/latest/development_guide/flows.html#dev-flows)


#### Set up a new PDK

See [PDKs](https://docs.siliconcompiler.com/en/latest/development_guide/pdks.html#dev-pdks)


#### Set up a new library

See [Libraries](https://docs.siliconcompiler.com/en/latest/development_guide/libraries.html#dev-libraries)


#### Set up a new target

See [Targets](https://docs.siliconcompiler.com/en/latest/development_guide/targets.html#dev-targets)


### Reuse a block as a hardened macro


#### Use a macro I already have

> **Warning**
> Adding a `.lef` to your design's own fileset does **not** work:
>
> ```
> design.add_file("mymacro.lef", fileset="rtl")   # wrong
> ```
>
> The parent will synthesize the macro's RTL anyway, and place-and-route then
> fails with `LEF master ... not found`. A macro is a *library*, not a source
> file.

Package the views into a [`StdCellLibrary`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.StdCellLibrary):

```python
from siliconcompiler import StdCellLibrary

macro = StdCellLibrary("mymacro")
macro.set_dataroot("macro", __file__)
macro.add_asic_pdk("skywater130")            # must match the parent's PDK

with macro.active_dataroot("macro"), macro.active_fileset("models.physical"):
    macro.add_file("mymacro.lef")            # abstract view for place & route
    macro.add_file("mymacro.gds")            # layout, merged into the final GDS
    macro.add_asic_aprfileset()

with macro.active_dataroot("macro"), macro.active_fileset("models.timing.typical"):
    macro.add_file("mymacro_typical.lib")    # timing view
    macro.add_asic_libcornerfileset("typical", "nldm")
```

Then, in the parent project, do two things -- **both are required**:

```python
# MyMacro() is the Design holding the macro's RTL -- the same sources the
# parent would otherwise synthesize, and what the alias tells it to skip.
project.add_alias(MyMacro(), "rtl", None, None)        # 1. blackbox the RTL
project.add_asiclib(macro)                             # 2. inject the views

# Macros need room. Too small a die and the placer cannot fit them.
project.constraint.area.set_dieoutline(250, 250, coremargin=10)
```

Without the alias the parent re-synthesizes the block instead of instantiating
the hardened version; without the library the tools have no physical or timing
view of it.

[Instantiating a hardened module](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/hardened.html#hardened-modules) works through this
end to end, including producing the macro from a first build.


#### Harden a parameterized module so I can reuse it as a macro

A [hardened macro](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-hardened-macro) has no parameters, so a parameterized module cannot be
hardened directly. Use [`Uniquified`](https://docs.siliconcompiler.com/en/latest/reference_manual/uniquify_api.html#siliconcompiler.tools.slang.utils.macro.Uniquified), which generates a parameter-free
variant per used parameter combination plus a wrapper that dispatches to
them. See the [uniquify tutorial](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/uniquify.html#uniquify-modules) and the
[Uniquify API](https://docs.siliconcompiler.com/en/latest/reference_manual/uniquify_api.html#uniquify-api).

```python
from siliconcompiler import ASIC
from siliconcompiler.targets import freepdk45_demo
from siliconcompiler.tools.slang.utils.macro import Uniquified

# parent_design: your Design that instantiates the parameterized module.
uq = Uniquified(parent_design, ["mymodule"])
uq.build(target=freepdk45_demo)   # harden every used parameterization

project = ASIC(parent_design)
project.add_fileset("rtl")
freepdk45_demo(project)
uq.wireup(project)                # alias wrappers + inject macros
```


#### Find out which parameter values my module is instantiated with

Construct [`Uniquified`](https://docs.siliconcompiler.com/en/latest/reference_manual/uniquify_api.html#siliconcompiler.tools.slang.utils.macro.Uniquified) (construction only elaborates and generates in
memory -- no disk writes, no tools) and read its state:

```python
uq = Uniquified(parent_design, ["mymodule"])
print(uq.variants)   # {'mymodule': ['mymodule__N8', 'mymodule__N16']}
```


#### Rebuild only some hardened variants

Pass `macros` to [`Uniquified.build()`](https://docs.siliconcompiler.com/en/latest/reference_manual/uniquify_api.html#siliconcompiler.tools.slang.utils.macro.Uniquified.build) as a variant name, a module
name, or a glob; add `rebuild=True` to force a rebuild even if a cached
macro exists.

```python
uq.build(target=freepdk45_demo, macros="mymodule__N8", rebuild=True)
```


### Schema internals


#### Avoid rebuilding an expensive object (such as a PDK) many times

If a schema object is a pure function of its construction arguments, base it
on `CachedSchema`. Instances are built once per unique (hashable) set of
arguments, and the shared, frozen instance is returned on subsequent
constructions. This is useful for heavy objects, like PDKs, that would
otherwise be re-created dozens of times while loading a target.

```python
from siliconcompiler import PDK
from siliconcompiler.schema import CachedSchema

class MyPDK(PDK, CachedSchema):
    def __init__(self):
        super().__init__("mypdk")
        # ... expensive schema population ...

MyPDK() is MyPDK()   # True -- same shared instance, built only once
```

The shared instance is *frozen*: calling `set`, `add`, `unset`,
`remove`, or using `EditableSchema` on it raises a
`SchemaFrozenError`. This protects the shared object from accidental
modification.


#### Get a modifiable version of a frozen (cached) object

Use `copy()`. A copy is always mutable and fully independent of the shared
instance, so you are free to modify it. Objects reloaded from a manifest
(for example, inside a run) are likewise mutable.

```python
my_pdk = MyPDK()          # frozen, shared
local = my_pdk.copy()     # mutable, independent
local.set("pdk", "foundry", "virtual")
```

To modify a frozen object in place (for example, to write resolved file
paths or hashes back into a shared object during a run), use the `_thaw`
context manager, which restores the frozen state on exit:

```python
with my_pdk._thaw():
    my_pdk.set(*keypath, hashes, field="filehash")
```

> **Warning**
> `_thaw()` is internal API -- the leading underscore is not decorative. It
> exists for SiliconCompiler's own run machinery, carries no compatibility
> guarantee, and mutating a shared instance affects every holder of it.
> `copy()` is the supported answer; reach for `_thaw()` only when you
> genuinely need the mutation to be visible through the shared object.


---

Source: https://docs.siliconcompiler.com/en/latest/user_guide/migration.html

## Migrating from the `Chip` API

If you have a script that starts like this, you are using an API that no longer
exists:

```python
from siliconcompiler import Chip

chip = Chip('heartbeat')
chip.input('heartbeat.v')
chip.load_target('freepdk45_demo')
chip.run()
```

The `Chip` class was removed in **v0.35.0** (October 2025) and replaced by a
[`Design`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Design) object plus a project object. This page maps the
old names onto the new ones.

> **Note**
> This page is kept indefinitely, and deliberately spells out the old names in
> full. Years of tutorials, papers, forum answers and blog posts use the
> `Chip` API, search engines still surface documentation for releases that
> predate the change, and code assistants trained on all of it will happily
> write `Chip('mydesign')` today. If you arrived here from one of those, you
> are in the right place.
>
> Parameter-level changes -- keys added, renamed or removed inside the schema
> itself -- are recorded separately in [Schema Changes](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#schema-changelog).


### Why it changed

`Chip` was one object holding two unrelated things: *what* you are building
and *how* this particular build is configured. That made a design impossible to
reuse -- to build the same RTL for two processes, or reuse a block inside a
larger chip, you rebuilt the object from scratch.

The replacement separates them:

- A [`Design`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Design) describes source code: files, grouped into
  [filesets](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-fileset), with a top module and include paths. It says
  nothing about a process or a flow, so the same `Design` can be built many
  ways, and one design can depend on another.
- A **project** describes one compilation of a design. Use the class that
  matches the job -- [`ASIC`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.ASIC), [`FPGA`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGA), [`Lint`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Lint) or
  [`Sim`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Sim) -- which is what replaces the old `option,mode` flag. Each one
  brings the schema, constraints and metrics for its domain, so an `ASIC`
  carries the `asic,*` parameters that a `Lint` has no use for.
  [`Project`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.project.Project) is the base class they extend, and is not the one to write a
  build script against: it has no domain section, so an ASIC target applied to a
  bare `Project` fails with `AttributeError`.

The second change is that configuration moved from string keypaths to **typed
accessors** -- `project.option.set_remote(True)` rather than
`chip.set('option', 'remote', True)`. Keypaths still work and are still the
layer underneath; see [Working with the Schema](https://docs.siliconcompiler.com/en/latest/user_guide/data_model.html#schema-access) for when to
use which.


### The same script, before and after

The old form, from the `heartbeat` example as it shipped in v0.34.3:

```python
from siliconcompiler import Chip
from siliconcompiler.targets import freepdk45_demo

chip = Chip('heartbeat')
chip.register_source("heartbeat-example", __file__)
chip.input("heartbeat.v", package="heartbeat-example")
chip.input("heartbeat.sdc", package="heartbeat-example")
chip.use(freepdk45_demo)
chip.run()
chip.summary()
chip.show()
```

The same build today. It is pulled in from `examples/heartbeat/heartbeat.py`,
so it is exercised by the test suite rather than transcribed here:

```python
design = Design("heartbeat")

# Set the root directory for the design's source files.
design.set_dataroot("heartbeat", __file__)

# Configure the RTL (Verilog) source files.
design.set_topmodule("heartbeat", fileset="rtl")
design.add_file("heartbeat.v", dataroot="heartbeat", fileset="rtl")

# Configure the SDC (timing constraints) file.
design.add_file("heartbeat.sdc", dataroot="heartbeat", fileset="sdc")

# Create an ASIC project from the design configuration.
project = ASIC(design)

# Enable the necessary filesets for the compilation flow.
project.add_fileset(["rtl", "sdc"])

# Load the pre-defined target for the Skywater130 demo process.
skywater130_demo(project)

# Execute the compilation flow.
project.run()

# Print a summary of the results (timing, area, power, etc.).
project.summary()

# Display the final physical layout in a GDS viewer.
project.show()

```

Four differences to notice, because they account for most of the porting work:

1. **Two objects instead of one.** `Design` for the sources, `ASIC` for the
  build.
2. **Files carry a fileset.** `input()` guessed a file's role from its
  extension; `add_file()` requires you to name it, and the project then
  selects which filesets to compile with `add_fileset()`.
3. **The top module is explicit.** It used to be inferred from the `Chip` name.
4. **A target is called, not "used".** `skywater130_demo(project)` instead of
  `chip.use(...)` or `chip.load_target(...)`.


### Objects and imports

| Removed | Use instead |
| --- | --- |
| `Chip` | [`Design`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Design) for the sources, plus one of [`ASIC`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.ASIC) / [`FPGA`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGA) / [`Lint`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Lint) / [`Sim`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Sim) for the build ([`Project`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.project.Project) is their base class, not a substitute for them) |
| `ASICProject` | [`ASIC`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.ASIC) |
| `Library`, `LibrarySchema` | [`Design`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Design). Since schema 0.54.0 a library *is* a design; [`StdCellLibrary`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.StdCellLibrary) adds the standard-cell specifics |
| `Flow`, `FlowgraphSchema` | [`Flowgraph`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Flowgraph) |
| `Schema` (top-level export) | Nothing to import. A project *is* a schema -- `get`, `set`, `getkeys` and `write_manifest` are methods on it |
| `DesignSchema`, `PDKSchema`, `ASICSchema`, `MetricSchema`, ... | The `...Schema` suffix is gone from the public names: [`Design`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Design), [`PDK`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.PDK), [`Checklist`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Checklist), [`Task`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task) |
| `SiliconCompilerError` | Standard Python exceptions |

> **Warning**
> `FPGA` still exists and **means something different**. It used to be the
> FPGA *device* class; it is now the FPGA *project* class. The device is
> [`FPGADevice`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGADevice). Old code reading
> `FPGA('mydevice')` needs `FPGADevice('mydevice')`.


### Setting up a design

| Old | New |
| --- | --- |
| `Chip('mydesign')` | `Design('mydesign')` |
| `chip.set('design', 'top')` | `design.set_topmodule('top', fileset='rtl')` |
| `chip.top()` | `design.get_topmodule(fileset='rtl')` |
| `chip.input('f.v')` | `design.add_file('f.v', fileset='rtl')` -- the fileset is explicit rather than guessed from the extension |
| `chip.output(...)` | Outputs are produced by tasks, not declared on the design |
| `chip.register_source('name', __file__)` | `design.set_dataroot('name', __file__)` |
| `package='name'` keyword | `dataroot='name'`. The schema field was renamed in schema 0.52.0, along with the `find_files` and `check_filepaths` arguments |
| `chip.add('option', 'idir', 'include')` | `design.add_idir('include', fileset='rtl')` |
| `chip.add('option', 'define', 'SYNTHESIS')` | `design.add_define('SYNTHESIS', fileset='rtl')` |
| `chip.import_flist('files.f')` | `design.read_fileset('files.f', fileset='rtl')` |
| `chip.clock('clk', period=1.0)` | Removed with no direct equivalent -- the `datasheet` pin timing parameters it wrote are gone. Define clocks in an SDC file and add it to an `sdc` fileset |
| `chip.use(mylib)` for a library | `project.add_dep(mylib)`, or list its filesets through `design.add_depfileset()` |
| `chip.swap_library(old, new)` | `project.add_alias(old_dep, old_fileset, new_dep, new_fileset)` |


### Configuring and running

| Old | New |
| --- | --- |
| `chip.use(freepdk45_demo)` | `freepdk45_demo(project)` -- targets are still plain functions, and are called with the project |
| `chip.load_target('freepdk45_demo')` | Import the target and call it. The string form, and the `option,target` parameter behind it, are both gone |
| `chip.set('option', 'mode', 'asic')` | Use the [`ASIC`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.ASIC) project class. `option,mode` was removed in schema 0.42.7 |
| `chip.set('option', 'remote', True)` | `project.option.set_remote(True)` |
| `chip.set('option', 'builddir', 'out')` | `project.option.set_builddir('out')` |
| `chip.set('option', 'jobname', 'run1')` | `project.option.set_jobname('run1')` |
| `chip.set('option', 'quiet', True)` | `project.option.set_quiet(True)` |
| `chip.set('option', 'to', 'syn')` | `project.option.add_to('syn')`; likewise `add_from` and `add_prune` |
| `chip.set('option', 'flow', 'asicflow')` | `project.set_flow(ASICFlow())`, or let the target set it |
| `chip.run()`, `chip.summary()`, `chip.show()` | Unchanged -- same names on the project |
| `chip.check_manifest()` | `project.check_manifest()`, but call it **after** `run()`: library dependencies are resolved during the run, so a pre-run call reports failures on a correct configuration |
| `chip.dashboard()` | The CLI dashboard now runs during `run()` automatically; disable it with `project.option.set_nodashboard(True)`. For the web dashboard, use `python3 -m siliconcompiler.apps.utils.dashboard` |
| `chip.check_checklist()` | `Checklist.check()` -- see [Checklists and signoff](https://docs.siliconcompiler.com/en/latest/user_guide/checklist.html#checklists) |
| `chip.create_cmdline()` | Unchanged in name, now provided by `CommandLineSchema` on the project |
| `chip.error('message')` | Raise an exception, or log through `project.logger` |


### Reading results and paths

| Old | New |
| --- | --- |
| `chip.get('metric', 'cellarea', step=..., index=...)` | Unchanged, but read it from the object `run()` returns: job metrics are reset on the live project when a run completes |
| `chip.getworkdir()` | `siliconcompiler.utils.paths.workdir(project, step=..., index=...)` |
| `chip.getbuilddir()` | `siliconcompiler.utils.paths.builddir(project)` |
| `chip.collect()`, `chip.archive()` | `siliconcompiler.utils.curation.collect(project)` and `archive(project)` |
| `chip.find_result(...)`, `chip.snapshot()` | Unchanged -- same names on the project |
| `chip.find_node_file(...)` | `project.find_result(...)` |
| `chip.hash_files(...)`, `chip.check_filepaths()` | Unchanged in name, now schema methods; `hash_files` takes `dataroot` where it took `package` |
| `chip.help('option', 'remote')` | Removed. Parameter help text is in the [Schema Reference](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#schema), or `project.getdict()` |
| `<design>.cfg` | `<design>.pkg.json`. Manifests have been JSON with a `.pkg.json` extension since well before the `Chip` removal; a `.cfg` path in a script or a dashboard `-cfg` invocation is stale |


### Building flows, tools and libraries

Module-style setup functions became classes. Old flows, tool tasks, PDKs and
libraries were modules exposing a `setup(chip)` function plus a `make_docs`
hook, discovered by import:

```python
# old: siliconcompiler/flows/myflow.py
def make_docs(chip):
    return setup()

def setup(flowname='myflow'):
    flow = siliconcompiler.Flow(flowname)
    flow.node(flowname, 'import', parse)
    flow.node(flowname, 'syn', syn_asic)
    flow.edge(flowname, 'import', 'syn')
    return flow
```

Now each is a class, and `make_docs` is gone -- the documentation is generated
from the class and its docstring:

```python
# new
from siliconcompiler import Flowgraph

class MyFlow(Flowgraph):
    '''One-line summary, which becomes the description in the docs.'''
    def __init__(self):
        super().__init__("myflow")
        self.node("elaborate", Elaborate())
        self.node("synthesis", ASICSynthesis())
        self.edge("elaborate", "synthesis")
```

The same shape applies elsewhere: a tool task subclasses
[`Task`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task) instead of exposing `setup(chip)`,
`pre_process(chip)` and `post_process(chip)` module functions; a standard
cell library subclasses [`StdCellLibrary`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.StdCellLibrary); a PDK
subclasses [`PDK`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.PDK). Nodes take a task *instance* rather
than a module reference, and `node()`/`edge()` are methods on the flowgraph
rather than on the chip.

Targets are the exception: they are still functions taking a project, because a
target's job is to configure one.

See the [Development Guide](https://docs.siliconcompiler.com/en/latest/development_guide/index.html#development-guide) for how to write each of these, and
[Where your module belongs](https://docs.siliconcompiler.com/en/latest/development_guide/contribution.html#module-placement) before you decide which
repository it goes in -- that answer also changed.


### The command line

There is **no** `sc` command, and there never was one after v0.35.0. The
entry points are `sc-config`, `sc-issue`, `sc-remote`, `sc-show`,
`sc-install` and `smake`.

| Old | New |
| --- | --- |
| `sc heartbeat.v -target freepdk45_demo` | Write a Python script -- see the example above -- or use `smake` with a `make.py` |
| `sc -target asic_demo` | `python3 -m siliconcompiler.demos.asic_demo` |
| `sc -target asic_demo -remote` | `python3 -m siliconcompiler.demos.asic_demo -remote` |
| `sc-dashboard` | `python3 -m siliconcompiler.apps.utils.dashboard`, same arguments |
| `sc-server` | `python3 -m siliconcompiler.remote.server`, same arguments |
| `python3 -m siliconcompiler.apps.utils.cleanup` | `sc-config cache clean`, same arguments, except that `-dryrun` takes no value: drop a `true` after it |

Everything else -- `sc-show`, `sc-issue`, `sc-remote` and the rest --
kept its name and its arguments.


### Still stuck?

If a symbol is not listed here, two places are worth checking before asking:
[Schema Changes](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#schema-changelog) for anything that looks like a schema
key, and the [Python API](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#schema-api) for a method name. Failing that, ask
in [Discussions](https://github.com/siliconcompiler/siliconcompiler/discussions) -- and please
say which version the old script targeted, because it tells us which era of the
API to translate from.


---

Source: https://docs.siliconcompiler.com/en/latest/development_guide/index.html

## Development Guide

The following sections describe how to build your own custom modules in SiliconCompiler so that you can customize your own flow.
If you don't plan to build your own modules and just want to use SiliconCompiler with pre-defined modules, see the [Reference Manual](https://docs.siliconcompiler.com/en/latest/reference_manual/index.html#reference-manual).

If you intend to contribute your module back to the project, two pages are worth
reading first: [Where your module belongs](https://docs.siliconcompiler.com/en/latest/development_guide/contribution.html#module-placement) covers the
choice -- in this repository, in `lambdapdk`, or in a package of
your own -- and [CONTRIBUTING.md](https://github.com/siliconcompiler/siliconcompiler/blob/main/CONTRIBUTING.md)
covers the process: branches, tests, the four lint gates every pull request is
checked against, and how to build the docs.

Building modules[Defining a Target](https://docs.siliconcompiler.com/en/latest/development_guide/targets.html)[Why Create a Target?](https://docs.siliconcompiler.com/en/latest/development_guide/targets.html#why-create-a-target)[Anatomy of a Target Function](https://docs.siliconcompiler.com/en/latest/development_guide/targets.html#anatomy-of-a-target-function)[Example: A Target for a Simple ASIC](https://docs.siliconcompiler.com/en/latest/development_guide/targets.html#example-a-target-for-a-simple-asic)[How to Use the Target](https://docs.siliconcompiler.com/en/latest/development_guide/targets.html#how-to-use-the-target)[Next Steps](https://docs.siliconcompiler.com/en/latest/development_guide/targets.html#next-steps)[Building a Flowgraph](https://docs.siliconcompiler.com/en/latest/development_guide/flows.html)[Key Concepts](https://docs.siliconcompiler.com/en/latest/development_guide/flows.html#key-concepts)[Example: A Basic Synthesis Flow](https://docs.siliconcompiler.com/en/latest/development_guide/flows.html#example-a-basic-synthesis-flow)[Useful APIs](https://docs.siliconcompiler.com/en/latest/development_guide/flows.html#useful-apis)[Create a Flowgraph](https://docs.siliconcompiler.com/en/latest/development_guide/flows.html#create-a-flowgraph)[Modifying a Flowgraph](https://docs.siliconcompiler.com/en/latest/development_guide/flows.html#modifying-a-flowgraph)[Inspecting a Flowgraph](https://docs.siliconcompiler.com/en/latest/development_guide/flows.html#inspecting-a-flowgraph)[Documentation](https://docs.siliconcompiler.com/en/latest/development_guide/flows.html#documentation)[Class Reference](https://docs.siliconcompiler.com/en/latest/development_guide/flows.html#class-reference)[Flowgraph](https://docs.siliconcompiler.com/en/latest/development_guide/flows.html#autosummarysiliconcompiler-flowgraph)[Supporting Classes](https://docs.siliconcompiler.com/en/latest/development_guide/flows.html#supporting-classes)[FlowgraphNodeSchema](https://docs.siliconcompiler.com/en/latest/development_guide/flows.html#autosummarysiliconcompiler-flowgraph-flowgraphnodeschema)[RuntimeFlowgraph](https://docs.siliconcompiler.com/en/latest/development_guide/flows.html#autosummarysiliconcompiler-flowgraph-runtimeflowgraph)[Integrating a New Tool](https://docs.siliconcompiler.com/en/latest/development_guide/tools.html)[The Structure of a Tool Driver](https://docs.siliconcompiler.com/en/latest/development_guide/tools.html#the-structure-of-a-tool-driver)[The setup() Method: Core Configuration](https://docs.siliconcompiler.com/en/latest/development_guide/tools.html#the-setup-method-core-configuration)[Execution Lifecycle Methods](https://docs.siliconcompiler.com/en/latest/development_guide/tools.html#execution-lifecycle-methods)[Version Handling](https://docs.siliconcompiler.com/en/latest/development_guide/tools.html#version-handling)[Interface for TCL-Based Tools](https://docs.siliconcompiler.com/en/latest/development_guide/tools.html#interface-for-tcl-based-tools)[Reading ASIC standard-cell timing](https://docs.siliconcompiler.com/en/latest/development_guide/tools.html#reading-asic-standard-cell-timing)[Declaring what a task needs remotely](https://docs.siliconcompiler.com/en/latest/development_guide/tools.html#declaring-what-a-task-needs-remotely)[API Quick Reference](https://docs.siliconcompiler.com/en/latest/development_guide/tools.html#api-quick-reference)[Task __init__ methods](https://docs.siliconcompiler.com/en/latest/development_guide/tools.html#task-init-methods)[Core Implementation Methods](https://docs.siliconcompiler.com/en/latest/development_guide/tools.html#core-implementation-methods)[Remote Placement Properties](https://docs.siliconcompiler.com/en/latest/development_guide/tools.html#remote-placement-properties)[Configuration Methods](https://docs.siliconcompiler.com/en/latest/development_guide/tools.html#configuration-methods)[Runtime Accessor Methods](https://docs.siliconcompiler.com/en/latest/development_guide/tools.html#runtime-accessor-methods)[Tool post process methods](https://docs.siliconcompiler.com/en/latest/development_guide/tools.html#tool-post-process-methods)[Documentation methods](https://docs.siliconcompiler.com/en/latest/development_guide/tools.html#documentation-methods)[Class Reference](https://docs.siliconcompiler.com/en/latest/development_guide/tools.html#class-reference)[Task](https://docs.siliconcompiler.com/en/latest/development_guide/tools.html#autosummarysiliconcompiler-task)[Defining a Process Design Kit (PDK)](https://docs.siliconcompiler.com/en/latest/development_guide/pdks.html)[Key Concepts](https://docs.siliconcompiler.com/en/latest/development_guide/pdks.html#key-concepts)[Example: Defining a Virtual PDK](https://docs.siliconcompiler.com/en/latest/development_guide/pdks.html#example-defining-a-virtual-pdk)[Useful APIs](https://docs.siliconcompiler.com/en/latest/development_guide/pdks.html#useful-apis)[Setting Process Metadata](https://docs.siliconcompiler.com/en/latest/development_guide/pdks.html#setting-process-metadata)[Organizing Filesets](https://docs.siliconcompiler.com/en/latest/development_guide/pdks.html#organizing-filesets)[Manufacturing Calculations](https://docs.siliconcompiler.com/en/latest/development_guide/pdks.html#manufacturing-calculations)[Class Reference](https://docs.siliconcompiler.com/en/latest/development_guide/pdks.html#class-reference)[PDK](https://docs.siliconcompiler.com/en/latest/development_guide/pdks.html#autosummarysiliconcompiler-pdk)[Defining a Library](https://docs.siliconcompiler.com/en/latest/development_guide/libraries.html)[Types of Libraries](https://docs.siliconcompiler.com/en/latest/development_guide/libraries.html#types-of-libraries)[Example 1: Hard IP Library](https://docs.siliconcompiler.com/en/latest/development_guide/libraries.html#example-1-hard-ip-library)[Using the Library](https://docs.siliconcompiler.com/en/latest/development_guide/libraries.html#using-the-library)[Example 2: Soft IP Library](https://docs.siliconcompiler.com/en/latest/development_guide/libraries.html#example-2-soft-ip-library)[Using the Library](https://docs.siliconcompiler.com/en/latest/development_guide/libraries.html#lib-example2-using)[Timing models and the delay model](https://docs.siliconcompiler.com/en/latest/development_guide/libraries.html#timing-models-and-the-delay-model)[Useful APIs](https://docs.siliconcompiler.com/en/latest/development_guide/libraries.html#useful-apis)[Core Configuration](https://docs.siliconcompiler.com/en/latest/development_guide/libraries.html#core-configuration)[PDK and Physical Views](https://docs.siliconcompiler.com/en/latest/development_guide/libraries.html#pdk-and-physical-views)[Class Reference](https://docs.siliconcompiler.com/en/latest/development_guide/libraries.html#class-reference)[Design](https://docs.siliconcompiler.com/en/latest/development_guide/libraries.html#autosummarysiliconcompiler-design)[StdCellLibrary](https://docs.siliconcompiler.com/en/latest/development_guide/libraries.html#autosummarysiliconcompiler-stdcelllibrary)[Packaging an External Library](https://docs.siliconcompiler.com/en/latest/development_guide/external_libraries.html)[Why package a library](https://docs.siliconcompiler.com/en/latest/development_guide/external_libraries.html#why-package-a-library)[Package layout](https://docs.siliconcompiler.com/en/latest/development_guide/external_libraries.html#package-layout)[The `pyproject.toml`](https://docs.siliconcompiler.com/en/latest/development_guide/external_libraries.html#the-pyproject-toml)[Locating data files](https://docs.siliconcompiler.com/en/latest/development_guide/external_libraries.html#locating-data-files)[Two dataroot strategies](https://docs.siliconcompiler.com/en/latest/development_guide/external_libraries.html#two-dataroot-strategies)[Defining modules inside the package](https://docs.siliconcompiler.com/en/latest/development_guide/external_libraries.html#defining-modules-inside-the-package)[ASIC timing models and the delay model](https://docs.siliconcompiler.com/en/latest/development_guide/external_libraries.html#asic-timing-models-and-the-delay-model)[Bundling into a target](https://docs.siliconcompiler.com/en/latest/development_guide/external_libraries.html#bundling-into-a-target)[Adding tools to sc-install](https://docs.siliconcompiler.com/en/latest/development_guide/external_libraries.html#adding-tools-to-sc-install)[Publishing to PyPI](https://docs.siliconcompiler.com/en/latest/development_guide/external_libraries.html#publishing-to-pypi)[Installing and using the library](https://docs.siliconcompiler.com/en/latest/development_guide/external_libraries.html#installing-and-using-the-library)[Reference](https://docs.siliconcompiler.com/en/latest/development_guide/external_libraries.html#reference)

Appendix[Working with Metrics](https://docs.siliconcompiler.com/en/latest/development_guide/metrics.html)[1. Automated Optimization with Goals and Weights](https://docs.siliconcompiler.com/en/latest/development_guide/metrics.html#automated-optimization-with-goals-and-weights)[2. Reporting and Analysis](https://docs.siliconcompiler.com/en/latest/development_guide/metrics.html#reporting-and-analysis)[The Metric Lifecycle](https://docs.siliconcompiler.com/en/latest/development_guide/metrics.html#the-metric-lifecycle)[List of Available Metrics](https://docs.siliconcompiler.com/en/latest/development_guide/metrics.html#list-of-available-metrics)[Execution Records and Provenance](https://docs.siliconcompiler.com/en/latest/development_guide/records.html)[What Information is Recorded?](https://docs.siliconcompiler.com/en/latest/development_guide/records.html#what-information-is-recorded)[Default Tracking (Always On)](https://docs.siliconcompiler.com/en/latest/development_guide/records.html#default-tracking-always-on)[Optional Full Tracking](https://docs.siliconcompiler.com/en/latest/development_guide/records.html#optional-full-tracking)[Enabling Full Tracking](https://docs.siliconcompiler.com/en/latest/development_guide/records.html#enabling-full-tracking)[How Records Are Stored](https://docs.siliconcompiler.com/en/latest/development_guide/records.html#how-records-are-stored)[User Settings](https://docs.siliconcompiler.com/en/latest/development_guide/options.html)[Storage Format](https://docs.siliconcompiler.com/en/latest/development_guide/options.html#storage-format)[Changing Settings](https://docs.siliconcompiler.com/en/latest/development_guide/options.html#changing-settings)[Declaring a Setting](https://docs.siliconcompiler.com/en/latest/development_guide/options.html#declaring-a-setting)[System-Wide Defaults](https://docs.siliconcompiler.com/en/latest/development_guide/options.html#system-wide-defaults)[Precedence and System Priority](https://docs.siliconcompiler.com/en/latest/development_guide/options.html#precedence-and-system-priority)[Concurrency & Safety](https://docs.siliconcompiler.com/en/latest/development_guide/options.html#concurrency-safety)[Schema Defaults (The 'schema-options' Category)](https://docs.siliconcompiler.com/en/latest/development_guide/options.html#schema-defaults-the-schema-options-category)[Key Mapping](https://docs.siliconcompiler.com/en/latest/development_guide/options.html#key-mapping)[Slurm Scheduler Settings (The 'scheduler-slurm' Category)](https://docs.siliconcompiler.com/en/latest/development_guide/options.html#slurm-scheduler-settings-the-scheduler-slurm-category)[Workflow: Slurm Settings](https://docs.siliconcompiler.com/en/latest/development_guide/options.html#workflow-slurm-settings)[Show Task Preferences (The 'showtask' Category)](https://docs.siliconcompiler.com/en/latest/development_guide/options.html#show-task-preferences-the-showtask-category)[Cache Cleanup Settings (The 'cache' Category)](https://docs.siliconcompiler.com/en/latest/development_guide/options.html#cache-cleanup-settings-the-cache-category)[Record Settings (The 'record' Category)](https://docs.siliconcompiler.com/en/latest/development_guide/options.html#record-settings-the-record-category)


---

Source: https://docs.siliconcompiler.com/en/latest/development_guide/targets.html

## Defining a Target

A [target](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-target) in SiliconCompiler is a reusable "build configuration" for a specific type of project. Think of it as a master recipe that bundles together everything needed to compile a design for a particular goal, such as creating a low-power IoT chip on the Skywater 130nm process or a high-performance block on FreePDK45.

Targets are implemented as simple Python functions that configure a Project object. They are loaded by directly calling the function and passing in the project to configure, making it incredibly easy to set up a complex build.

A full list of built-in targets can be found on the [targets](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/targets.html#builtin-targets) page.

> **Seealso**
> Writing the module is only half the job -- where it ships matters too. Open
> PDKs and standard cell libraries belong in [lambdapdk](https://github.com/siliconcompiler/lambdapdk), closed or proprietary ones
> in your own package (see [Packaging an External Library](https://docs.siliconcompiler.com/en/latest/development_guide/external_libraries.html#dev-external-libraries)), and tools, flows and targets in the
> SiliconCompiler repository itself. [Where does my module go?](https://docs.siliconcompiler.com/en/latest/development_guide/contribution.html#module-placement) walks through the choice.
>
> Contributing the module back? [CONTRIBUTING.md](https://github.com/siliconcompiler/siliconcompiler/blob/main/CONTRIBUTING.md)
> covers the pull request process, the four lint gates every PR is checked
> against, and how to build the docs.


### Why Create a Target?

While you can configure a project's [PDK](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-PDK), [flow](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-flow), and [libraries](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-library) manually, creating a target is the recommended approach for any serious project. The benefits include:

- **Encapsulation**: It bundles all technology-specific and flow-specific settings into one place.
- **Reusability**: The same target can be used across multiple designs, ensuring consistency.
- **Simplicity**: It reduces a complex setup process to a single line of code in your build script.


### Anatomy of a Target Function

A target is a Python function that accepts a [`Project`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.project.Project) object as its first argument. Inside this function, you will typically perform the following actions:

1. **Load Core Components**: Set the fundamental building blocks of your compilation:

  - **PDK**: The process design kit for the manufacturing technology.
  - **Flow**: The sequence of EDA tool [steps](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-step) to run (e.g., [synthesis](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-synthesis), [place-and-route](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-place-and-route)).
  - **Libraries**: The [standard cell](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-standard-cell) libraries and/or macros to use. The primary one is the [mainlib](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-mainlib); the rest supplement it.
2. **Set Default Constraints**: Define the default goals and physical constraints for the design.

  - **Timing Constraints**: Clock speeds, I/O delays, and other performance goals.
  - **Physical Constraints**: Desired die area, core [utilization](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-utilization) (density), and pin placement.
3. **Configure Tool Options**: Set default options for specific tools in the flow, such as the number of cores to use for a given step.


### Example: A Target for a Simple ASIC

Let's create a target for a generic ASIC design. This function will load a standard ASIC flow, a fictional PDK and library, and set some common physical and timing constraints.

```python
from siliconcompiler import ASIC
from siliconcompiler.flows import asicflow
from siliconcompiler.tools.yosys import syn_asic

# It's common practice to import the PDK and library schemas
# that your target will use.
from my_designs.pdks import my_freepdk45
from my_designs.libs import my_nangate45

def my_asic_target(project: ASIC,
                   # Targets can be parameterized. Here, we allow the user
                   # to specify the number of cores for parallelizable steps.
                   place_np=1,
                   route_np=1):
    '''
    A simple target for a generic 45nm ASIC design.
    '''

    # 1. Load Core Components
    # The order is important: load libraries and PDK first, then the flow.
    project.set_mainlib(my_nangate45.Nangate45())
    project.set_pdk(my_freepdk45.FreePDK45())
    project.set_flow(asicflow.ASICFlow(place_np=place_np, route_np=route_np))

    # 2. Set Default Constraints

    # Timing Constraints: Define a "typical" corner for setup/hold analysis.
    # This sets the performance goals for the design.
    scenario = project.constraint.timing.make_scenario("typical")
    scenario.add_libcorner("typical")
    scenario.set_pexcorner("typical")
    scenario.add_check(["setup", "hold"])

    # Physical Constraints: Define the physical layout goals.
    # Here, we aim for 40% core utilization and a 1-micron margin.
    area = project.constraint.area
    area.set_density(40)
    area.set_coremargin(1)

    # 3. Configure Tool Options
    syn_asic.ASICSynthesis.find_task(project).set_strategy("AREA3")
```


### How to Use the Target

Once the target function is defined, you can load it into your project like this:

```python
import siliconcompiler

# Create a project
project = siliconcompiler.ASIC()

# Load the entire configuration by calling the target function.
# We can also pass values for the parameterized arguments.
my_asic_target(project, place_np=4, route_np=4)

# Now the project is fully configured and ready to run!
# project.run()
```


### Next Steps

A target is composed of other SiliconCompiler modules. To build effective targets, you will need to understand how to define these components:

- **PDKs**: Learn how to define a PDK in the [PDK](https://docs.siliconcompiler.com/en/latest/development_guide/pdks.html#dev-pdks) documentation.
- **Libraries**: Learn how to define a standard cell library in the [Library](https://docs.siliconcompiler.com/en/latest/development_guide/libraries.html#dev-libraries) documentation.
- **Flows**: Learn how to build a custom flow in the [Flow](https://docs.siliconcompiler.com/en/latest/development_guide/flows.html#dev-flows) documentation.


---

Source: https://docs.siliconcompiler.com/en/latest/development_guide/flows.html

## Building a Flowgraph

> **Seealso**
> Contributing this back to the project? [Where your module belongs](https://docs.siliconcompiler.com/en/latest/development_guide/contribution.html#module-placement) covers the choice and [CONTRIBUTING.md](https://github.com/siliconcompiler/siliconcompiler/blob/main/CONTRIBUTING.md)
> covers the process: branches, tests, the four lint gates, and the docs build.

A [flowgraph](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-flowgraph) in SiliconCompiler defines the sequence of [steps](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-step) (or [tasks](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-task)) required to transform your hardware design from source code into a physical layout.
Think of it as a recipe for your project, where each step is a specific [tool](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-tool) run (like [synthesis](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-synthesis) or [place-and-route](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-place-and-route)).

Flowgraphs are highly flexible and allow you to create custom compilation flows tailored to your specific needs. You can build them in two primary ways:

1. **Instantiate Flowgraph**: For simple or dynamically generated flows, you can create an object directly from the [`Flowgraph`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Flowgraph) class and configure it.
2. **Subclass Flowgraph**: For creating reusable, complex flows, you can define your own Python class that inherits from [`Flowgraph`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Flowgraph).

Once defined, you load your flowgraph into a project using the [`Project.set_flow()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.project.Project.set_flow) method before starting a run. This tells SiliconCompiler which set of tasks to execute.

A complete set of supported builtin flows can be found in [flows](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/flows.html#builtin-flows).


### Key Concepts

Before we build a flowgraph, let's define the core components:

- **Node**: A [node](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-flowgraph-node) represents a single task or step in the flow, identified by a (step, [index](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-index)) pair. Each node is typically an instance of a Task class, which wraps a specific EDA tool (e.g., Yosys for synthesis, OpenROAD for place-and-route).
- **Edge**: An [edge](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-edge) defines a dependency between two nodes. If you create an edge from nodeA to nodeB, it means that nodeA must complete successfully before nodeB can begin. This creates the directed, acyclic graph that SiliconCompiler executes.


### Example: A Basic Synthesis Flow

Here's how to build a simple flow that [elaborates](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-elaboration) Verilog, runs synthesis, and then performs a timing analysis.
This example demonstrates the fundamental [`node()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Flowgraph.node) and [`edge()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Flowgraph.edge) API calls.

We'll create a new class called SynthesisFlow that inherits from [`Flowgraph`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Flowgraph).

```python
# Import the base class and the specific tool tasks we need.
from siliconcompiler import Flowgraph
from siliconcompiler.tools.yosys import syn_asic
from siliconcompiler.tools.opensta import timing
from siliconcompiler.tools.slang import elaborate

class SynthesisFlow(Flowgraph):
    """
    A simple synthesis flow that demonstrates the basic principles
    of creating a SiliconCompiler flowgraph.
    """
    def __init__(self):
        # It's important to call the parent constructor and give the flow a name.
        super().__init__("synthesis_flow")

        # Step 1: Create the nodes for our flow.
        # Each node is given a name (e.g., "elaborate") and is associated
        # with a Task object that knows how to run a specific tool.
        self.node("elaborate", elaborate.Elaborate())
        self.node("synthesis", syn_asic.ASICSynthesis())
        self.node("timing", timing.TimingTask())

        # Step 2: Create the edges to define the execution order.
        # This tells SiliconCompiler that 'elaborate' must run before 'synthesis',
        # and 'synthesis' must run before 'timing'.
        self.edge("elaborate", "synthesis")
        self.edge("synthesis", "timing")
```

To use this flow, you would instantiate it and set it in your project:

```python
import siliconcompiler

# Create a project
project = siliconcompiler.Project()

# Instantiate and set the flow
flow = SynthesisFlow()
project.set_flow(flow)

# Now you can configure the rest of your project and run it.
# project.run()
```


### Useful APIs

The [`Flowgraph`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Flowgraph) class provides a rich API for creating, modifying, and inspecting flowgraphs.


#### Create a Flowgraph

These are the fundamental methods for building the graph structure.


#### Modifying a Flowgraph

These methods allow you to alter an existing flowgraph, which is useful for dynamically adjusting a pre-defined flow.


#### Inspecting a Flowgraph

These methods help you understand the structure and execution order of your flow.


#### Documentation

This method helps you generate documentation for your custom flow.


### Class Reference

For more detailed information, refer to the full API documentation for the primary classes involved in creating and managing flowgraphs.


#### Flowgraph

Class [`siliconcompiler.Flowgraph`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Flowgraph)


### Supporting Classes

These classes are used internally by the flowgraph but can be useful to understand.


#### FlowgraphNodeSchema

Class [`siliconcompiler.flowgraph.FlowgraphNodeSchema`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.flowgraph.FlowgraphNodeSchema)


#### RuntimeFlowgraph

Class [`siliconcompiler.flowgraph.RuntimeFlowgraph`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.flowgraph.RuntimeFlowgraph)


---

Source: https://docs.siliconcompiler.com/en/latest/development_guide/tools.html

A complete set of supported tools can be found in [tools](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/tools.html#builtin-tools).


## Integrating a New Tool

> **Seealso**
> Contributing this back to the project? [Where your module belongs](https://docs.siliconcompiler.com/en/latest/development_guide/contribution.html#module-placement) covers the choice and [CONTRIBUTING.md](https://github.com/siliconcompiler/siliconcompiler/blob/main/CONTRIBUTING.md)
> covers the process: branches, tests, the four lint gates, and the docs build.

To add support for a new EDA tool, you need to create a Python-based "driver" that teaches SiliconCompiler how to interact with it. Think of a driver as a universal adapter: it translates SiliconCompiler's standardized hardware compilation flow into the specific commands, scripts, and file formats that a particular tool understands.

A complete driver consists of:

- **One or more Task classes**: Defines a specific [task](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-task) that the [tool](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-tool) can perform, such as [synthesis](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-synthesis) (syn) or [place-and-route](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-place-and-route) (place). Each task specifies its inputs, outputs, and how to generate the command-line arguments.

A complete list of built-in tools can be found in the [Tools](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/tools.html#builtin-tools) reference.


### The Structure of a Tool Driver

A tool driver is a Python module that typically defines at least one [`Task`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task) class.

```python
from siliconcompiler import Task

class MyTask(Task):
    """A task for running the tool in a specific way."""
    # Task-level implementation goes here.

    def setup(self):
        # This is the main configuration method.
        pass

    # Other required methods (runtime_options, post_process, etc.)
```


#### The setup() Method: Core Configuration

The [`Task.setup()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.setup) method is the heart of the driver. It's called for each [step](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-step) in the flow and is responsible for configuring all aspects of the tool and task.
Inside this method, you have access to the project object to define your settings.


##### Step 1: Basic Tool Configuration

First, you tell SiliconCompiler about the tool's executable and how to check its version.

```python
def setup(self):
    # 1. Point to the executable.
    self.set_exe('my_tool_binary')

    # 2. Define how to check the version.
    #    'vswitch' is the command-line flag to print the version.
    #    'version' is a list of known-good version specifiers.
    self.add_vswitch('--version')
    self.add_version('>=2.1')
```


##### Step 2: Task-Specific Configuration

Next, you define what the specific task needs to run and what it will produce.

```python
def setup(self):
    # ... (tool setup from above)

    # 3. Define required inputs.
    #    This tells SC to expect a Verilog file from the 'input' node.
    self.add_input_file('verilog.v')

    # 4. Define expected outputs.
    #    This tells SC that this task will produce a new Verilog netlist.
    self.add_output_file('verilog.vg')

    # 5. Define required schema parameters.
    #    This ensures the flow will fail early if a critical setting is missing.
    self.add_required_key('asic', 'pdk')
    self.add_required_key('asic', 'asiclib')

    # 6. For script-based tools (like TCL), define the entry script.
    self.set_script('run_my_tool.tcl')
```

> **Important**
> **Require every file the task reads, not only the settings it cannot do
> without.** The required keys are also what a node's rerun check compares
> and what `sc-issue` packages: a file the task reads without requiring it
> -- a view reached through `asic,asiclib` and a fileset, say -- can change
> without the node running again, and is missing from an issue built to
> reproduce it. Where the task reads a library's files, require those
> filesets' files, as the OpenROAD and Yosys tasks do.

> **Important**
> `setup()` **SHOULD NOT call** `find_files` **(or anything else that
> resolves a path)**. `setup()` runs for every node in the flow, before the
> rerun check decides which of them will run -- nodes outside `-from`/`-to`
> and nodes whose previous result is reused included -- and resolving a path
> there fetches a remote PDK just to answer it for a node that does nothing. It
> also runs to build the task's page in the reference manual, against a
> placeholder design with nothing to find. Declare keys in `setup()`; resolve
> the files they name in [`Task.runtime_options()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.runtime_options) or later, where the task
> actually runs.


#### Execution Lifecycle Methods

Beyond the initial setup, a [`Task`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task) class implements several methods that are called at different points during the [`Task.run()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.run) process.


##### runtime_options()

This method generates the command-line options for the tool. It is called at execution time, which is critical for distributed systems where absolute file paths are only known on the execution machine.

**Why is this separate from setup()?** [`Task.setup()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.setup) is run early to validate the entire flow, while [`Task.runtime_options()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.runtime_options) runs just-in-time to build the command, ensuring all paths are resolved correctly.

```python
def runtime_options(self):
    '''
    Generates the command-line arguments for the tool.
    '''
    cmdlist = []

    # Each option token is its own list item -- never "-flag value" as a
    # single string.
    cmdlist.append("verilog.v")

    # Add the output file path.
    cmdlist.extend(['-o', 'verilog.vg'])

    # Add the top module name.
    cmdlist.extend(['-top', self.design_topmodule])

    return cmdlist
```


##### post_process()

This method is called after the tool executable has finished. Its primary purpose is to parse log files and report metrics back to the SiliconCompiler database. It can also be used to modify or reformat output files.

```python
def post_process(self):
    '''
    Parses tool output and reports metrics.
    '''
    # Get the path to the log file for this step.
    log_file = self.get_logpath("exe")

    # Example: Parse the log file for the final cell area.
    with open(log_file, 'r') as f:
        for line in f:
            if line.startswith('Final Area:'):
                area = float(line.split()[-1])
                # Record the metric in the SC database.
                self.record_metric('cellarea', area, 'um^2')
```


##### pre_process() and run()

- [`Task.pre_process()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.pre_process): A hook that runs immediately before the tool executable is launched. Useful for last-minute adjustments based on results from prior steps.
- [`Task.run()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.run): For pure-Python tools. If this method is defined, SiliconCompiler will execute this Python function instead of an external command-line executable. It should return 0 on success.


#### Version Handling

To ensure reproducible builds, SiliconCompiler has a robust version-checking system. You may need to implement these helper methods in your Tool class.

- [`Task.parse_version()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.parse_version): The output of exe --version can be messy. This function parses the raw stdout string and returns a clean version number (e.g., "2.1.3").
- [`Task.normalize_version()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.normalize_version): SC's version checker uses the Python PEP-440 standard. If your tool uses a non-standard versioning scheme (e.g., 2.1+a4b8c1), this function should convert it to a compatible format (e.g., 2.1.post0.dev-a4b8c1).
- [`Task.get_exe_version()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.get_exe_version): A pure-Python tool has no executable to ask, so override this to return the version of the package it runs (e.g., `pyslang`). The version is recorded with the run and checked against [`Task.add_version()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.add_version) like any other.


#### Interface for TCL-Based Tools

For tools that are driven by TCL scripts, SiliconCompiler simplifies configuration by writing a [manifest](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-manifest) file (sc_manifest.tcl) in the work directory.
Your TCL script should source this file. It provides a nested TCL dictionary called sc_cfg containing the entire project configuration.

Your TCL script is responsible for reading from this dictionary and applying the settings.

```tcl
# In your run_my_tool.tcl script:

# Source the manifest to load the configuration
source sc_manifest.tcl

# Helper function to get the top-level module name
set sc_design [sc_top]

# Extract values from the configuration dictionary
set sc_asiclibs [sc_cfg_get asic asiclib]
set sc_pdk      [sc_cfg_get asic pdk]

# These variables hold library *names*. Use the sc_cfg_get_fileset helper to
# resolve a library + fileset into actual files before passing them to tool
# commands such as read_liberty or read_lef.
...
```


#### Reading ASIC standard-cell timing

An [ASIC](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-ASIC) tool that needs standard-cell timing -- [synthesis](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-synthesis),
[static timing analysis](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-STA), place-and-route -- reads the library's
timing files for the active [delay model](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-delay-model) and timing
[corners](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-corner). A [standard cell](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-standard-cell) [library](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-library)
groups those files into *libcorner* [filesets](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-fileset), keyed by
`(corner, delaymodel)` via
[`StdCellLibrary.add_asic_libcornerfileset()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.StdCellLibrary.add_asic_libcornerfileset) (see
[Timing models and the delay model](https://docs.siliconcompiler.com/en/latest/development_guide/libraries.html#lib-delaymodel) for the library side).

A driver looks the timing fileset up by name, keyed on `(corner, delaymodel)`.
Every built-in ASIC driver (OpenROAD, OpenSTA) does this the same way. In Python,
inside [`Task.setup()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.setup), read `asic,delaymodel`, walk the timing scenarios
and their library corners, and declare the matching filesets' files as required
inputs:

```python
def setup(self):
    super().setup()
    # ... exe / script setup ...
    delaymodel = self.project.get("asic", "delaymodel")
    for libname in self.project.get("asic", "asiclib"):
        lib = self.project.get_library(libname)
        for scenario in self.project.constraint.timing.get_scenario().values():
            for corner in scenario.get_libcorner(self.step, self.index):
                if not lib.valid("asic", "libcornerfileset", corner, delaymodel):
                    continue
                for fileset in lib.get("asic", "libcornerfileset", corner, delaymodel):
                    self.add_required_key(lib, "fileset", fileset, "file", "liberty")
```

The reference script performs the identical lookup against the manifest with the
`sc_cfg_*` helpers, then reads each file:

```tcl
set sc_delaymodel [sc_cfg_get asic delaymodel]
foreach corner $sc_scenarios {
    foreach lib $sc_asiclibs {
        set lib_filesets []
        foreach libcorner [sc_cfg_get constraint timing scenario $corner libcorner] {
            if { [sc_cfg_exists library $lib asic libcornerfileset $libcorner $sc_delaymodel] } {
                lappend lib_filesets {*}[sc_cfg_get library $lib asic libcornerfileset $libcorner $sc_delaymodel]
            }
        }
        foreach lib_file [sc_cfg_get_fileset $lib $lib_filesets liberty] {
            read_liberty -corner $corner $lib_file
        }
    }
}
```

A library may also provide a compiled, binary timing model (here `.bin`) that a
tool loads faster than parsing Liberty. It is shipped under a `<model>-bin`
variant (`nldm-bin`, `ccs-bin`); the target selects it with
`set_asic_delaymodel("nldm-bin")`, and the driver performs the same
`(corner, delaymodel)` lookup but loads the compiled files with the tool's own
reader in place of `read_liberty`.

If a tool always prefers the compiled model, the driver can select it *itself*
instead of relying on the target -- append `-bin` to the active delay model and
use it whenever that fileset exists:

```python
delaymodel = self.project.get("asic", "delaymodel")
if not delaymodel.endswith("-bin") and \
        lib.valid("asic", "libcornerfileset", corner, f"{delaymodel}-bin"):
    delaymodel = f"{delaymodel}-bin"   # prefer the compiled model when available
```

That way a target can leave `delaymodel` as `nldm` and the driver still picks
up `nldm-bin` automatically when the library ships it.


#### Declaring what a task needs remotely

A remote run can place each node in its own environment, such as a container
image that holds the node's tool. Two properties of [`Task`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task) tell it what a
node needs. The leading underscore does not make them internal: they are the
supported interface for any driver, including one outside this repository.

- [`Task._remote_toolname`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task._remote_toolname) names the tool that must be installed. It
  defaults to [`Task.tool()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.tool), so most drivers never override it. That
  includes a task with no executable that drives its tool's Python package, as
  the slang tasks do. Return another tool's name when the task runs that tool.
  Return `None` when it needs nothing beyond SiliconCompiler, as the builtin
  tasks do.
- [`Task._remote_inherits_env`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task._remote_inherits_env) returns `True` when the node should run
  wherever its input node ran. `exec_input` does this to run what an earlier
  node built. It defaults to `False`.

Both are read from a task that has not been set up and has no project, so
return a constant:

```python
from typing import Optional

from siliconcompiler import Task

class RunBuiltBinary(Task):
    def tool(self):
        return "mytool"

    def task(self):
        return "run"

    @property
    def _remote_toolname(self) -> Optional[str]:
        # Nothing to install: the program comes from the input node.
        return None

    @property
    def _remote_inherits_env(self) -> bool:
        # Run where the node that built the program ran.
        return True
```


### API Quick Reference

The [`Task`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task) class provides a rich API for defining and controlling how a tool operates. The methods are grouped below by their primary function.


#### Task __init__ methods


#### Core Implementation Methods

These are the main methods you will implement in your [`Task`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task) subclass to define its behavior.


#### Remote Placement Properties

Override these to declare what a node needs on a remote server. See
Declaring what a task needs remotely.


#### Configuration Methods

These methods are called within your [`Task.setup()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.setup) implementation to configure the task's properties.


##### Tools settings


##### Task settings


#### Runtime Accessor Methods

These methods are used to get information about the current state of the flow during execution (e.g., inside [`Task.runtime_options()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.runtime_options) or [`Task.post_process()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.post_process)).


#### Tool post process methods


#### Documentation methods

These methods are used for auto-generating documentation for your tool.


### Class Reference


#### Task

Class [`siliconcompiler.Task`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task)


---

Source: https://docs.siliconcompiler.com/en/latest/development_guide/pdks.html

## Defining a Process Design Kit (PDK)

In semiconductor design, a Process Design Kit ([PDK](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-PDK)) contains all the technology-specific data--such as transistor models, layout rules, and [standard cell](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-standard-cell) [libraries](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-library)--required to manufacture a chip on a particular process node.
These kits are often complex and vary significantly between foundries.

SiliconCompiler simplifies this by providing a standardized Python object, the [`PDK`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.PDK), to define and package a PDK.
This object acts as a structured "manifest" that describes the PDK's properties and points to all the necessary files.
Once defined, a PDK can be easily reused and loaded into any project with a single command: [`ASIC.set_pdk()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.ASIC.set_pdk).

> **Seealso**
> Writing the module is only half the job -- where it ships matters too. Open
> PDKs and standard cell libraries belong in [lambdapdk](https://github.com/siliconcompiler/lambdapdk), closed or proprietary ones
> in your own package (see [Packaging an External Library](https://docs.siliconcompiler.com/en/latest/development_guide/external_libraries.html#dev-external-libraries)), and tools, flows and targets in the
> SiliconCompiler repository itself. [Where does my module go?](https://docs.siliconcompiler.com/en/latest/development_guide/contribution.html#module-placement) walks through the choice.
>
> Contributing the module back? [CONTRIBUTING.md](https://github.com/siliconcompiler/siliconcompiler/blob/main/CONTRIBUTING.md)
> covers the pull request process, the four lint gates every PR is checked
> against, and how to build the docs.


### Key Concepts

A [`PDK`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.PDK) is built around two main concepts:

- **Metadata**: High-level information that describes the manufacturing process, such as the foundry, process node (e.g., 28nm), and metal [stackup](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-stackup). This data is essential for design tools and for calculating manufacturing metrics.
- **Filesets**: A [fileset](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-fileset) is a named group of files that serve a specific purpose. For example, a views.lef fileset contains all the [LEF](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-LEF) files needed for abstract layout views, while a models.spice fileset would contain SPICE models for simulation. This organization ensures that each tool gets exactly the files it needs.


### Example: Defining a Virtual PDK

The following example demonstrates how to create a basic PDK definition by subclassing [`PDK`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.PDK). We will define a fictional 28nm process.

```python
from pathlib import Path
from siliconcompiler import PDK

class ExamplePDK(PDK):
    """
    A demonstration PDK for a fictional 28nm process.
    """
    def __init__(self):
        super().__init__()

        # 1. Give the PDK a unique name.
        self.set_name("examplepdk")

        # Assume the PDK files are in a local directory named "examplepdk/"
        pdk_path = Path("examplepdk")

        # 2. Define the high-level process metadata.
        self.set_foundry("virtual")
        self.set_version("v1.0")
        self.set_node(28)  # Process node in nanometers
        self.set_stackup("12M") # Number of metal layers
        self.set_wafersize(300) # Wafer diameter in millimeters

        # Define manufacturing and cost parameters.
        self.set_scribewidth(0.1, 0.1)
        self.set_edgemargin(2)
        self.set_defectdensity(1.25)

        # 3. Define the data source for the PDK files.
        # Here, we point to a fictional Git repository.
        self.set_dataroot("pdksource", "git+https://data.com/source.tar.gz")

        # 4. Organize the PDK files into filesets.
        # The 'with self.active_dataroot(...)' block tells SiliconCompiler
        # that all files added inside this block are relative to this data source.
        with self.active_dataroot("pdksource"):
            # The 'with self.active_fileset(...)' block groups related files.
            # Here, we are defining the LEF files for the abstract view.
            with self.active_fileset("views.lef"):
                self.add_file(pdk_path / "apr" / "examplepdk.lef")
                # This helper function automatically adds technology LEF files
                # for common open-source tools.
                for tool in ('openroad', 'klayout', 'magic'):
                    self.add_aprtechfileset(tool)

            # Define which metal layers are available for routing.
            self.set_aprroutinglayers(min="metal2", max="metal7")
```

To use this PDK, you would instantiate it and pass it to your project:

```python
import siliconcompiler

# Create a project
project = siliconcompiler.ASIC()

# Instantiate and set the PDK
pdk = ExamplePDK()
project.set_pdk(pdk)

# Now, when project.run() is called, the tools in the flow
# will be able to find and use the files defined in the PDK.
```


### Useful APIs

The PDK class provides a comprehensive API for defining all aspects of a PDK.


#### Setting Process Metadata

These methods define the core physical and manufacturing properties of the process.


#### Organizing Filesets

These methods are used to group files for different tools and design views.

> **Seealso**
> Once a PDK ships an OpenRCX signoff deck (`add_pexmodelfileset("openroad",
> ...)` with an `openrcx` file), OpenROAD's pre-route parasitic *estimate*
> can be derived and calibrated directly from that deck instead of hand-tuned.
> The OpenROAD-specific PDK subclass
> ([`OpenROADPDK`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.tools.openroad.OpenROADPDK)) exposes the knobs that
> result -- [`add_openroad_rclayer()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.tools.openroad.OpenROADPDK.add_openroad_rclayer)
> (the per-layer estimate model) and
> [`add_openroad_rccorrection()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.tools.openroad.OpenROADPDK.add_openroad_rccorrection)
> (the calibrated correction on top of it). See the
> [Calibrating the parasitic estimate (PEX)](https://docs.siliconcompiler.com/en/latest/user_guide/tutorials/pex_calibration.html#pex-calibration) tutorial for how to generate the values to paste into
> a PDK setup.


#### Manufacturing Calculations

These methods use the defined metadata to compute key manufacturing metrics.


### Class Reference


#### PDK

Class [`siliconcompiler.PDK`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.PDK)


---

Source: https://docs.siliconcompiler.com/en/latest/development_guide/libraries.html

## Defining a Library

In hardware design, a [library](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-library) is a collection of reusable components.
SiliconCompiler generalizes this concept with the [`Design`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Design) object, which acts as a standardized "manifest" for any piece of IP (Intellectual Property) you want to include in your design.

This could be a [hard macro](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-hardened-macro) with pre-defined physical layouts ([GDS](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-GDSII), [LEF](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-LEF)), a [standard cell](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-standard-cell) library from a foundry, or a soft [IP](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-IP) delivered as [RTL](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-RTL) source code ([Verilog](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-Verilog), [VHDL](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-VHDL)).

By packaging IP into a [`Design`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Design), you make it easy to manage, version, and reuse across different projects.
Libraries are loaded into a project using the [`Project.add_dep()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.project.Project.add_dep) method.

> **Seealso**
> Writing the module is only half the job -- where it ships matters too. Open
> PDKs and standard cell libraries belong in [lambdapdk](https://github.com/siliconcompiler/lambdapdk), closed or proprietary ones
> in your own package (see [Packaging an External Library](https://docs.siliconcompiler.com/en/latest/development_guide/external_libraries.html#dev-external-libraries)), and tools, flows and targets in the
> SiliconCompiler repository itself. [Where does my module go?](https://docs.siliconcompiler.com/en/latest/development_guide/contribution.html#module-placement) walks through the choice.
>
> Contributing the module back? [CONTRIBUTING.md](https://github.com/siliconcompiler/siliconcompiler/blob/main/CONTRIBUTING.md)
> covers the pull request process, the four lint gates every PR is checked
> against, and how to build the docs.


### Types of Libraries

There are two primary categories of libraries you can define:

- **Hard Libraries (StdCellLibrary)**: These represent foundational, physical IP. This includes standard cell libraries, I/O cells, or hard macros (like SRAMs or SERDES) that have fixed layouts. They are defined using the specialized [`StdCellLibrary`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.StdCellLibrary) class, which has extra features for handling physical and timing models.
- **Soft Libraries (Design)**: These represent synthesizable IP delivered as source code. This is common for digital IP cores that you want to integrate into your design before synthesis. They are defined using the base [`Design`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Design) class.


### Example 1: Hard IP Library

This example demonstrates how to define a library for a hard macro. This macro is a pre-designed block with its own physical layout (LEF, GDS) and timing models (.lib).
We will use the [`StdCellLibrary`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.StdCellLibrary) because it is a physical, foundational component.

```python
from pathlib import Path
from siliconcompiler import StdCellLibrary
from my_pdk import FakePDK # Assuming a PDK is defined elsewhere

class FakeHardIPLibrary(StdCellLibrary):
    def __init__(self):
        # 1. Call the parent constructor with a unique name for the library.
        super().__init__("fakeip")

        # 2. Associate this library with a specific PDK.
        # This tells SiliconCompiler that this IP is designed for this technology.
        self.add_asic_pdk(FakePDK())

        # 3. Define the location of the library's source files.
        # Here, we point to a local directory.
        path_base = Path("fakeip")
        self.set_dataroot("fakedata", "python://fakedata_module")

        # 4. Organize the library's files into standardized filesets.
        with self.active_dataroot("fakedata"):
            # Define the physical view files (LEF and GDS).
            with self.active_fileset("models.physical"):
                self.add_file(path_base / "lef" / "fakeip.lef")
                self.add_file(path_base / "gds" / "fakeip.gds")
                # Helper function to add standard APR tech files.
                self.add_asic_aprfileset()

            # Define the timing models. This library provides an NLDM model
            # for the "typical" corner.
            with self.active_fileset("models.timing.nldm"):
                self.add_file(path_base / "nldm" / "fakeip.lib")
                # Helper to associate the file with a specific corner.
                self.add_asic_libcornerfileset("typical", "nldm")
```


#### Using the Library

To use either of these libraries in your design, you would instantiate the class and add it as a dependency to your project.

```python
import siliconcompiler

project = siliconcompiler.ASIC()

# Instantiate and add the hard IP library.
hard_ip_lib = FakeHardIPLibrary()
project.add_asiclib(hard_ip_lib)

# Now, the 'fakeip' will be included during compilation.
# project.run()
```

[`ASIC.add_asiclib()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.ASIC.add_asiclib) supplements the [mainlib](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-mainlib) -- the primary
standard cell library synthesis maps to, set with [`ASIC.set_mainlib()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.ASIC.set_mainlib). A
library of macros like this one is an addition to that primary library, not a
replacement for it.


### Example 2: Soft IP Library

This example shows how to define a library for a soft IP core, which is just a reusable block of RTL code. Since there are no physical or timing views, we use the [`Design`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Design).

```python
from siliconcompiler import Design

class FakeSoftIP(Design):
    def __init__(self):
        # 1. Call the parent constructor with a unique name.
        super().__init__("fakesoftip")

        # 2. Set metadata for the library.
        self.set_version("v1.0")

        # 3. Define the location of the source files.
        self.set_dataroot("fakedata", "python://fakedata_module")

        # 4. Add the RTL source code to the 'rtl' fileset.
        # When this library is included in a project, this Verilog file
        # will be passed to the synthesis tool.
        with self.active_dataroot("fakedata"), self.active_fileset("rtl"):
                self.add_file("rtl/fakeip.v")
```


#### Using the Library

To use either of these libraries in your design, you would instantiate the class and add it as a dependency to your project.

```python
import siliconcompiler

project = siliconcompiler.Project()

# Instantiate and add the soft IP library.
soft_ip_lib = FakeSoftIP()
project.add_dep(soft_ip_lib)

# Now, the 'fakeip.v' source file will be included during compilation.
# project.run()
```


### Timing models and the delay model

A standard-cell library can provide its timing in several formats. [Liberty](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-Liberty)
(`.lib`) is read by the open-source tools; some libraries also provide a
compiled, binary timing model (here `.bin`) that a tool can load without
parsing Liberty. Each format goes in its own [fileset](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-fileset), tagged by
[corner](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-corner) and [delay model](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-delay-model) with
[`StdCellLibrary.add_asic_libcornerfileset()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.StdCellLibrary.add_asic_libcornerfileset): Liberty
uses a model such as `nldm` or `ccs`, and the compiled files use the
`<model>-bin` variant (`nldm-bin`, `ccs-bin`).

```python
with self.active_fileset(f"models.timing.{corner}.nldm"):
    self.add_file(f"lib/mylib_{corner}.lib.gz")
    self.add_asic_libcornerfileset(corner, "nldm")

# Compiled binary timing model for the same corner.
with self.active_fileset(f"models.timing.{corner}.nldm-bin"):
    self.add_file(f"bin/mylib_{corner}.bin", filetype="bin")
    self.add_asic_libcornerfileset(corner, "nldm-bin")
```

A [target](https://docs.siliconcompiler.com/en/latest/development_guide/targets.html#dev-targets) chooses which set the tools read with
`project.set_asic_delaymodel("nldm")` (or `"nldm-bin"` for a flow that reads
the compiled files). Each tool driver then resolves the files by looking up
`(corner, delaymodel)`, the same way the built-in drivers do. For how a driver
consumes these filesets in Python and TCL, see
[Reading ASIC standard-cell timing](https://docs.siliconcompiler.com/en/latest/development_guide/tools.html#dev-tools-asic-timing).


### Useful APIs


#### Core Configuration


#### PDK and Physical Views


### Class Reference

For a complete list of all available methods, please see the full class documentation.


#### Design

Class [`siliconcompiler.Design`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Design)


#### StdCellLibrary

Class [`siliconcompiler.StdCellLibrary`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.StdCellLibrary)


---

Source: https://docs.siliconcompiler.com/en/latest/development_guide/external_libraries.html

## Packaging an External Library

The [Defining a Library](https://docs.siliconcompiler.com/en/latest/development_guide/libraries.html#dev-libraries) guide shows how to subclass
[`Design`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Design), [`StdCellLibrary`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.StdCellLibrary), and [`PDK`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.PDK) to describe a
piece of IP. That is enough when the library class lives alongside the design
that uses it. Once you want to *share* a library, across projects, across a
team, or as a versioned deliverable, you package it as a standalone,
`pip`-installable Python distribution.

This guide covers that packaging layer: the project layout, the
`pyproject.toml`, and how bundled data files are located no matter where the
package is installed. A single package can bundle
[libraries](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-library), [PDKs](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-PDK), [flows](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-flow), and even
custom tool drivers, and expose them through a [target](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-target). For the details of the individual module classes, this guide links back
to [libraries](https://docs.siliconcompiler.com/en/latest/development_guide/libraries.html#dev-libraries), [pdks](https://docs.siliconcompiler.com/en/latest/development_guide/pdks.html#dev-pdks),
[flows](https://docs.siliconcompiler.com/en/latest/development_guide/flows.html#dev-flows), [tools](https://docs.siliconcompiler.com/en/latest/development_guide/tools.html#dev-tools), and
[targets](https://docs.siliconcompiler.com/en/latest/development_guide/targets.html#dev-targets). Throughout, the package is given the generic name
`mylib` so you can substitute your own.


### Why package a library

Distributing a library as its own package buys you:

- **Reuse** -- any project can `pip install mylib` and `import` it, instead
  of copying files into each design.
- **Versioning** -- the package carries a version, so a design can pin the exact
  library revision it was signed off against.
- **Data locality** -- data files ([LEF](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-LEF), [GDS](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-GDSII),
  [.lib](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-Liberty), ...) travel with the
  package and resolve automatically, whether the package is installed from PyPI
  or in editable mode from a local checkout.


### Package layout

A library package is an ordinary Python distribution with an importable module
at its root. A typical layout mirrors the categories of module you provide:

```text
mylib/                    # repository root
├── pyproject.toml        # build + packaging configuration
├── MANIFEST.in           # controls which files land in the sdist
├── README.md
├── LICENSE
└── mylib/                # the importable Python package
    ├── __init__.py       # package init (optionally a shared dataroot mixin)
    ├── _version.py       # auto-generated by setuptools_scm
    ├── libs/             # standard-cell / hard IP (StdCellLibrary subclasses)
    ├── pdks/             # PDK definitions (siliconcompiler.PDK subclasses)
    ├── flows/            # custom Flowgraph definitions
    ├── tools/            # custom tool/task drivers
    └── targets/          # targets bundling any of the above
```

Every module subpackage is **optional** -- include only what you ship. A package
might provide just a library, just a PDK, just a flow or tool driver, or any
combination, and expose it through a target.

Small data files (a hand-edited LEF, a [black-box](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-blackbox)
[Verilog](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-Verilog) stub) can be committed
directly under the relevant subpackage, e.g.
`mylib/libs/mymacro/mymacro.lef`. Large or proprietary data (full foundry
decks) is usually kept *outside* the package and referenced through an
environment variable, see Two dataroot strategies.


### The `pyproject.toml`

The build configuration does two jobs: build the package and derive its
version.

```
[build-system]
requires = ["setuptools >= 80", "setuptools_scm[toml] >= 8"]
build-backend = "setuptools.build_meta"

# Derive the version from git tags and write it into the package.
[tool.setuptools_scm]
version_file = "mylib/_version.py"

[project]
name = "mylib"
description = "Example external library for SiliconCompiler."
readme = "README.md"
requires-python = ">= 3.10"
# For proprietary IP, use a license reference instead of an SPDX id, e.g.
# license = "LicenseRef-MyCompany-Proprietary"
license = "Apache-2.0"
license-files = ["LICENSE"]
dynamic = ["version"]
dependencies = [
    "siliconcompiler == 0.38.11",
    # Depend on other libraries you build on, e.g.:
    # "lambdapdk",
]

[tool.setuptools]
include-package-data = true
```

Points worth calling out:

- **Versioning** -- `setuptools_scm` derives the package version from git tags
  and writes it into `mylib/_version.py` on every build, so each release is
  stamped with a version that designs can pin against. Because that file is
  generated, add it to `.gitignore` rather than committing it:

  ```text
  # .gitignore
  mylib/_version.py
  ```
- **``include-package-data = true``** -- together with `MANIFEST.in`, this
  ensures committed data files ship inside the wheel. Prune what you do not
  need (tests, examples) and explicitly include your package sources and data:

  ```text
  # MANIFEST.in
  prune tests
  prune examples
  recursive-include mylib *.py
  recursive-include mylib *.lef *.gds *.v
  ```
- **Pinning SiliconCompiler** -- pin `siliconcompiler` in `dependencies` to
  the exact release you develop against using an `==` constraint; the current
  release is 0.38.11.

> **Ext_lib_entry_points**
> More advanced packages can also register SiliconCompiler *entry points* to plug into
> documentation source links, `show`/`open` tasks, [data source resolvers](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/resolvers.html#builtin-resolvers), and tool-install helpers, plus `[project.scripts]` for CLI
> apps. SiliconCompiler registers its own built-ins in code before consulting these
> groups, so an entry point you provide takes precedence wherever the two overlap.
>
> ```toml
> # pyproject.toml
> [project.entry-points."siliconcompiler.showtask"]
> mylib = "mylib.showtools:showtasks"
>
> [project.entry-points."siliconcompiler.path_resolver"]
> myscheme = "mylib.resolver:get_resolver"
>
> [project.entry-points."siliconcompiler.docs"]
> linkcode = "mylib.docs:get_codeurl"
>
> [project.entry-points."siliconcompiler.install"]
> toolscripts = "mylib.install:get_toolscripts_dir"
> groups = "mylib.install:get_install_groups"
> fingerprint = "mylib.install:compute_fingerprint"
> ```
>
> The names in the `siliconcompiler.docs` and `siliconcompiler.install` groups are
> fixed, since SiliconCompiler looks them up by name. Adding tools to sc-install
> covers `toolscripts`. Names in the
> `siliconcompiler.showtask` and `siliconcompiler.path_resolver` groups are
> free-form; pick something unique to your package.


### Locating data files

For SiliconCompiler to find a module's data files no matter where the package is
installed, each module registers a **dataroot**. The simplest approach anchors
the dataroot to the module's own source file: passing `__file__` to
`set_dataroot` roots the data at the directory containing that module, so
files are added relative to it.

```python
self.set_dataroot(f"mylib-{self.name}", __file__)
```

Giving the dataroot a name unique to the module (here `mylib-<name>`) keeps it
from clashing when several libraries are combined into one project.

> **Note**
> If you would rather share a single dataroot across the whole package -- for
> example to reference files that live in sibling subpackages -- define a small
> mixin that every module inherits and point it at the installed package:
>
> ```python
> # mylib/__init__.py
> from siliconcompiler.schema_support.pathschema import PathSchema
>
>
> class _MyLibPath(PathSchema):
>     def __init__(self):
>         super().__init__()
>         self.set_dataroot("mylib", "python://mylib")
> ```
>
> The `python://mylib` dataroot resolves to the installed location of the
> `mylib` package, and `python://mylib/libs/mymacro` to a directory inside
> it. To additionally fetch large data files that are *not*
> shipped in the wheel, give the dataroot a git fallback keyed to the package
> version with `PythonPathResolver.set_dataroot` (see [python://](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/resolvers.html#resolver-python)).


#### Two dataroot strategies

Real libraries commonly mix two kinds of [dataroot](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-dataroot):

1. **Packaged data** -- the per-module dataroot rooted at `__file__` above, for
  files committed to and shipped with the package. Use this for small files
  (edited LEFs, black-box stubs, RTL stubs).
2. **External data** -- foundry decks are often too large or too restricted to
  commit. Point a second dataroot at an environment variable so users supply
  the data out-of-band:

  ```python
  self.set_dataroot("foundry", "$FOUNDRY_ROOT/tech/mylib/v1p0")
  ```

  Files added under this dataroot resolve against `$FOUNDRY_ROOT` at run time.
  Whenever a module relies on an environment variable like this, set a default
  for it in the target so users are not left to
  configure it by hand.


### Defining modules inside the package

Libraries, PDKs, flows, and tool drivers are defined exactly as in the
[libraries](https://docs.siliconcompiler.com/en/latest/development_guide/libraries.html#dev-libraries), [pdks](https://docs.siliconcompiler.com/en/latest/development_guide/pdks.html#dev-pdks),
[flows](https://docs.siliconcompiler.com/en/latest/development_guide/flows.html#dev-flows), and [tools](https://docs.siliconcompiler.com/en/latest/development_guide/tools.html#dev-tools) guides. The only packaging
addition is that any module shipping data files sets a dataroot from `__file__`
(and typically mixes in `CachedSchema`) so those files travel with the package.
A hard-IP library looks like:

```python
# mylib/libs/mymacro/__init__.py
from siliconcompiler import StdCellLibrary
from siliconcompiler.schema import CachedSchema
from siliconcompiler.tools.openroad import OpenROADStdCellLibrary
from siliconcompiler.tools.klayout import KLayoutLibrary

from mylib.pdks import mypdk


class MyMacro(OpenROADStdCellLibrary, KLayoutLibrary,
              StdCellLibrary, CachedSchema):
    def __init__(self):
        super().__init__()
        self.set_name("mymacro")
        self.package.set_vendor("MyVendor")
        self.package.set_version("v1p0")

        # Root data files at this module's own directory.
        self.set_dataroot(f"mylib-{self.name}", __file__)

        # Associate the PDK this IP targets.
        self.add_asic_pdk(mypdk.MyPDK())

        # Files committed next to this module, added relative to its directory.
        with self.active_dataroot(f"mylib-{self.name}"):
            with self.active_fileset("models.physical"):
                self.add_file("mymacro.lef")
                self.add_file("mymacro.gds")
                self.add_asic_aprfileset()

        # Timing models come from an external dataroot. Keep each format in
        # its own fileset, tagged by corner and delay model with
        # add_asic_libcornerfileset(corner, model). Liberty (.lib) uses a
        # model like "nldm"; a compiled binary timing model (here ".bin")
        # uses the "<model>-bin" variant.
        self.set_dataroot("foundry", "$FOUNDRY_ROOT/tech/mylib/v1p0")
        with self.active_dataroot("foundry"):
            for corner in ("slow", "typical", "fast"):
                with self.active_fileset(f"models.timing.{corner}.nldm"):
                    self.add_file(f"lib/mymacro_{corner}.lib.gz")
                    self.add_asic_libcornerfileset(corner, "nldm")

                # Compiled binary timing model for the same corner.
                with self.active_fileset(f"models.timing.{corner}.nldm-bin"):
                    self.add_file(f"bin/mymacro_{corner}.bin", filetype="bin")
                    self.add_asic_libcornerfileset(corner, "nldm-bin")
```

The tool mixins ([`OpenROADStdCellLibrary`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.tools.openroad.OpenROADStdCellLibrary),
[`KLayoutLibrary`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.tools.klayout.KLayoutLibrary), ...) attach tool-specific
parameters so the library carries everything a flow needs; see
[Tool Extension Classes](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#tool-extension-classes) for the full list. PDKs
follow the same recipe with [`PDK`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.PDK) and the tool `*PDK` mixins; see
[pdks](https://docs.siliconcompiler.com/en/latest/development_guide/pdks.html#dev-pdks).

> **Note**
> **Base class order matters when building on a bundled base class.** Some
> packages ship a base class that already combines several mixins -- lambdapdk's
> `LambdaLibrary`, for example, bundles the Yosys, OpenROAD, KLayout and Bambu
> library mixins together with [`StdCellLibrary`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.StdCellLibrary). Such a base class has to
> be listed **before** anything it already inherits, so extend it like this:
>
> ```python
> from lambdapdk import LambdaLibrary
> from mylib.tools.mytool import MyToolStdCellLibrary
>
>
> # LambdaLibrary first, and no separate StdCellLibrary: it brings its own.
> class MyMacro(LambdaLibrary, MyToolStdCellLibrary, CachedSchema):
>     ...
> ```
>
> Repeating [`StdCellLibrary`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.StdCellLibrary) in the base list *after* the bundled class
> asks Python for an inheritance order that cannot exist, and the class fails to
> define with `TypeError: Cannot create a consistent method resolution order
> (MRO)`. If you hit that error, remove the mixins the bundled base class
> already provides and move it to the front of the list.

A **tool driver** is a [`Task`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task) subclass. It names its tool and task,
declares the executable, and ships any reference scripts alongside the module:

```python
# mylib/tools/mytool/__init__.py
from siliconcompiler import Task


class MyToolTask(Task):
    def tool(self):
        return "mytool"

    def task(self):
        return "convert"

    def parse_version(self, stdout):
        return stdout.strip()

    def setup(self):
        super().setup()
        self.set_exe("mytool", vswitch="--version", format="tcl")
        self.add_version(">=1.0.0")

        # Reference scripts committed next to this module.
        self.set_dataroot("mytool-scripts", __file__)
        with self.active_dataroot("mytool-scripts"):
            self.set_refdir("scripts")
        self.set_script("convert.tcl")

    def runtime_options(self):
        options = super().runtime_options()
        # Each token is its own list item -- never "-flag value" as one string.
        options.append("-batch")
        options.extend(["-log", "convert.log"])
        return options
```

A task with no external executable overrides `run()` (returning an exit code)
instead of declaring an `exe`; everything else about the class is the same.
See [tools](https://docs.siliconcompiler.com/en/latest/development_guide/tools.html#dev-tools) for the full task API.

A **flow** is a [`Flowgraph`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Flowgraph) subclass that wires tasks into a graph of
steps with `node()` and `edge()` -- and it can reference both built-in tasks
and the package's own:

```python
# mylib/flows/myflow.py
from siliconcompiler import Flowgraph
from siliconcompiler.tools.slang.elaborate import Elaborate

from mylib.tools.mytool import MyToolTask


class MyFlow(Flowgraph):
    def __init__(self, name: str = "myflow"):
        super().__init__(name)
        self.node("elaborate", Elaborate())
        self.node("convert", MyToolTask())
        self.edge("elaborate", "convert")
```

See [flows](https://docs.siliconcompiler.com/en/latest/development_guide/flows.html#dev-flows) for composing larger graphs.


### ASIC timing models and the delay model

Standard-cell timing ships in more than one format. [Liberty](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-Liberty) (`.lib`)
is read by the open-source tools; some libraries also provide a compiled, binary
timing model (here `.bin`) that a tool can load without parsing Liberty. A
library keeps each format in its own [fileset](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-fileset), tagged with a
[corner](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-corner) and a [delay model](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-delay-model) using
`add_asic_libcornerfileset(corner, model)` (see the library
example above). By convention the compiled variant of a delay model is named
`<model>-bin`:

| Delay model | Fileset | Files |
| --- | --- | --- |
| `nldm` | `models.timing.<corner>.nldm` | Liberty (`.lib`) |
| `nldm-bin` | `models.timing.<corner>.nldm-bin` | compiled (`.bin`) |
| `ccs` | `models.timing.<corner>.ccs` | CCS Liberty (`.lib`) |
| `ccs-bin` | `models.timing.<corner>.ccs-bin` | compiled (`.bin`) |

A target chooses one with
`project.set_asic_delaymodel("nldm")` (or `"nldm-bin"` for a flow that reads
the compiled files). `delaymodel` is a free-form string, so `<model>-bin`
works purely by matching the fileset name you registered. Tool drivers resolve
the files by looking up `(corner, delaymodel)`; for how a driver consumes these
filesets in Python and TCL, see
[Reading ASIC standard-cell timing](https://docs.siliconcompiler.com/en/latest/development_guide/tools.html#dev-tools-asic-timing).


### Bundling into a target

To give users a one-call setup, provide a [target](https://docs.siliconcompiler.com/en/latest/development_guide/targets.html#dev-targets) function
that assembles the PDK, libraries, and flow -- and sets a default for any
environment variable the modules depend on:

```python
# mylib/targets/mytarget.py
import os

from siliconcompiler import ASIC

from mylib.pdks import mypdk
from mylib.libs import mymacro
from mylib.flows.myflow import MyFlow


def mytarget(project: ASIC):
    # Default the external dataroot only if the user has not already set it,
    # in the environment or on the project.
    if os.getenv("FOUNDRY_ROOT") is None and \
            project.option.get_env("FOUNDRY_ROOT") is None:
        project.option.set_env("FOUNDRY_ROOT", "/opt/foundry")

    project.set_pdk(mypdk.MyPDK())
    project.set_mainlib(mymacro.MyMacro())
    project.set_flow(MyFlow())

    # Pick the timing view the tools read (see the delay-model section above);
    # use "nldm-bin" instead for a flow that reads the compiled timing model.
    project.set_asic_delaymodel("nldm")
```

If a module points a dataroot at an environment variable such as
`$FOUNDRY_ROOT`, setting it here with `project.option.set_env` means users
get a working default without configuring anything themselves.


### Adding tools to sc-install

A package that drives a tool SiliconCompiler does not build can make it
installable with [sc-install](https://docs.siliconcompiler.com/en/latest/reference_manual/apps.html#app-sc-install). Lay out a directory the
way SiliconCompiler lays out its own `toolscripts`, and return it from a
`toolscripts` entry point:

```text
mylib/toolscripts/
├── _tools.json                  <- pins, in the same fields as SiliconCompiler's
└── ubuntu24/
    └── install-mytool.sh        <- one directory per supported OS
```

```toml
# pyproject.toml
[project.entry-points."siliconcompiler.install"]
toolscripts = "mylib.install:get_toolscripts_dir"
```

```python
# mylib/install.py
import os.path


def get_toolscripts_dir():
    return os.path.join(os.path.dirname(__file__), "toolscripts")
```

`sc-install` runs each script where it is installed, with `SC_TOOLSCRIPTS`
naming a directory that holds the shared helpers, `_prereqs.sh` and
`_tools.py`, beside a `_tools.json` that merges your pins into
SiliconCompiler's. An install script finds the helpers there and reads its pins
through `_tools.py`:

```bash
#!/bin/bash

set -ex

src_path="${SC_TOOLSCRIPTS:?run this script through sc-install}"

. "${src_path}/_prereqs.sh"
install_prereqs git

git clone $(python3 ${src_path}/_tools.py --tool mytool --field git-url) mytool
cd mytool
git checkout $(python3 ${src_path}/_tools.py --tool mytool --field git-commit)
```

Commit the script executable (`git update-index --chmod=+x`), since it is run
directly.

- **Overriding a pin.** An entry for a tool SiliconCompiler already pins changes
  only the fields it names: `{"yosys": {"git-commit": "v0.70"}}` builds yosys
  v0.70 with SiliconCompiler's own script. Ship `ubuntu24/install-yosys.sh` as
  well only to replace the recipe on that OS.
- **Rebuilds.** A tool's fingerprint covers its own pin and the pins of what it
  lists in `docker-depends`, so `sc-install` rebuilds it when either moves,
  including when the move comes from your override.
- **One package per tool.** Two installed packages supplying the same tool,
  whether by pin or by script, are an error.

The older `tools` entry point, which maps tool names straight to scripts,
still works, and its scripts are given `SC_TOOLSCRIPTS` too.

To keep your pins current the way SiliconCompiler keeps its own, call its tool
updater from a workflow of yours. Every entry in your `_tools.json` that has a
`git-url` and `"auto-update": true` gets a pull request moving it to the
newest commit or release tag. An override is read on its own, without
SiliconCompiler's fields, so it is updated only if it carries both itself.

```yaml
# .github/workflows/tool_updater.yml
name: 'Tool Updater'

on:
  workflow_dispatch:
  schedule:
    - cron: '0 0 * * *'

jobs:
  update:
    permissions:
      contents: read
      pull-requests: read
    uses: siliconcompiler/siliconcompiler/.github/workflows/update_tools.yml@main
    with:
      manifest: mylib/toolscripts/_tools.json
      app-client-id: ${{ vars.MYLIB_BOT_CLIENT_ID }}
      # Only for pins cloned from private repositories of the same owner
      repositories: mytool
      source-app-client-id: ${{ vars.MYLIB_READ_BOT_CLIENT_ID }}
    secrets:
      app-private-key: ${{ secrets.MYLIB_BOT_PRIVATE_KEY }}
      source-app-private-key: ${{ secrets.MYLIB_READ_BOT_PRIVATE_KEY }}
```

The pull requests are opened by a GitHub App you name with `app-client-id` and
`app-private-key`, which needs contents and pull requests write on your
repository. A pull request opened with `GITHUB_TOKEN` would run none of your
checks, and that token cannot read another private repository. The repositories
listed in `repositories` are read through `source-app-client-id` and
`source-app-private-key`, an App that needs only contents read on them; without
one, the App that opens the pull requests reads them too.

SiliconCompiler builds a docker image of each tool, tagged by a hash of
everything that goes into it, and yours can be built the same way, on
SiliconCompiler's images:

```bash
python3 -m siliconcompiler.utils.toolimages --image_prefix myorg/mylib_ --plan
python3 -m siliconcompiler.utils.toolimages --image_prefix myorg/mylib_ \
    --generate_files --output_dir docker
```

The tags are computed over your pins merged into SiliconCompiler's. An image
that would come out the same as SiliconCompiler's is taken from ghcr.io, where
SiliconCompiler publishes it; the rest are built as `ghcr.io/myorg/mylib_<tool>`,
or under another registry given with `--registry`: your own tools, any tool you
override, and everything built against one. `--plan` lists both, and
`--json_tools --stage 1`, then `2` and so on, gives the order to build them
in: an image is built after every built image it is built on. Each generated
directory is a build context. A token that can read a private source goes in the
`git_token` build secret, where every install script built with it can read it:

```bash
docker build --secret id=git_token,env=GIT_TOKEN docker/mylib_mytool
```

The image your CI runs in is `mylib_tools`, and `--plan` says which of three
it is:

- `sc_tools` itself, when you build nothing.
- `sc_tools` with your tools added as one layer, when you only add tools.
- Assembled from every tool's image, the way `sc_tools` is, when you change a
  pin or a recipe of one of SiliconCompiler's: the version it replaces would
  otherwise survive underneath.

SiliconCompiler's workflow builds whatever does not exist yet and returns the
image's name:

```yaml
jobs:
  images:
    permissions:
      contents: read
      packages: write
    uses: siliconcompiler/siliconcompiler/.github/workflows/tool_images.yml@main
    with:
      image-prefix: myorg/mylib_
      # Only for pins cloned from private repositories of the same owner
      repositories: mytool
      source-app-client-id: ${{ vars.MYLIB_READ_BOT_CLIENT_ID }}
    secrets:
      source-app-private-key: ${{ secrets.MYLIB_READ_BOT_PRIVATE_KEY }}

  test:
    needs: images
    runs-on: ubuntu-latest
    container:
      image: ${{ needs.images.outputs.image }}
      credentials:
        username: ${{ github.actor }}
        password: ${{ secrets.GITHUB_TOKEN }}
```

It installs your package from the calling repository, editable so that its data
resolves to the checkout, and pushes to ghcr.io with `GITHUB_TOKEN`; another
registry is named with `registry`, logged in to with `registry-username` and
the `registry-password` secret. SiliconCompiler's images are always pulled from
ghcr.io.


### Publishing to PyPI

For an open-source library, publishing to [PyPI](https://pypi.org) lets anyone
install it with a plain `pip install mylib`. Build the wheel and upload it:

```bash
python3 -m build                 # build the wheel and sdist into dist/
python3 -m twine upload dist/*   # publish to PyPI
```

Most projects prefer to automate this with a CI workflow -- for example a GitHub
Action using [pypa/gh-action-pypi-publish](https://github.com/pypa/gh-action-pypi-publish) -- that builds and publishes on
every tagged release. Proprietary libraries skip PyPI and are shared instead
through a private package index or straight from the git remote (see the VCS
install form below).


### Installing and using the library

Once published, the library is installed like any Python package:

```bash
pip install mylib
# for local development against your working tree:
pip install -e .
# or install a specific tagged revision straight from a git remote:
pip install "mylib @ git+https://company.com/git/mylib.git@v1.0.5"
```

The last form uses pip's [VCS direct-reference syntax](https://pip.pypa.io/en/stable/topics/vcs-support/), which is handy for
private libraries hosted on an internal git server.

> **Note**
> **Installing next to a SiliconCompiler source checkout.** If the environment
> runs SiliconCompiler from a git checkout (`pip install -e .`) rather than from
> a PyPI release, install the library with `--no-deps`:
>
> ```bash
> pip install --no-deps mylib
> ```
>
> `setuptools_scm` stamps a checkout with a development version such as
> `0.38.5.dev4+g1a2b3c4`, and no `==` pin matches a development version. The
> exact pin recommended above therefore looks unsatisfied, so pip resolves it by
> replacing the editable checkout with a release wheel from PyPI, silently undoing
> the source install. `--no-deps` leaves the checkout alone; install the
> library's remaining dependencies yourself, or relax the pin to `>=` while
> developing against a checkout.

The package is consumed either through its target or by adding its modules
directly:

```python
import siliconcompiler
from mylib.libs import mymacro
from mylib.targets.mytarget import mytarget

project = siliconcompiler.ASIC()

# Option A: one-call setup via the target.
mytarget(project)

# Option B: attach modules directly.
project.add_asiclib(mymacro.MyMacro())

# project.run()
```

Because each library roots its dataroot at its own `__file__`, all of its data
files resolve automatically, whether it was installed from PyPI or checked out
in editable mode.


### Reference

- [Defining a Library](https://docs.siliconcompiler.com/en/latest/development_guide/libraries.html#dev-libraries) -- the library classes and filesets.
- [Defining a PDK](https://docs.siliconcompiler.com/en/latest/development_guide/pdks.html#dev-pdks) -- packaging a process kit.
- [Building a Flowgraph](https://docs.siliconcompiler.com/en/latest/development_guide/flows.html#dev-flows) -- defining flows to ship in the package.
- [Integrating a New Tool](https://docs.siliconcompiler.com/en/latest/development_guide/tools.html#dev-tools) -- writing custom tool drivers.
- [Creating a Target](https://docs.siliconcompiler.com/en/latest/development_guide/targets.html#dev-targets) -- bundling modules into a target.


---

Source: https://docs.siliconcompiler.com/en/latest/development_guide/metrics.html

## Working with Metrics

In SiliconCompiler, [metrics](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-metric) measure the quality of a compilation run; the ones a run is judged on are its key performance indicators ([KPIs](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-KPI)).
They are numerical values--like area, power, timing, and error counts--tracked per [flowgraph node](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-flowgraph-node), which a ([step](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-step), [index](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-index)) pair identifies.

Metrics serve three primary purposes:

- **Automated Optimization:** To automatically select the best compilation result from multiple runs.
- **Reporting:** To display a high-level summary of a run's performance.
- **Custom Scripting:** To allow you to build custom analysis and optimization loops.


### 1. Automated Optimization with Goals and Weights

SiliconCompiler's minimum task uses metrics to find the optimal design result.
To guide this process, you can configure two parameters for any given metric in the [flowgraph](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-flowgraph):

- `goal:` The target value for a metric. This defines a hard requirement.
- `weight:` A value that tells the optimizer how much to prioritize one metric over another.

The default `asicflow` provides a great example of a typical optimization strategy. Let's break it down:

```python
# For critical metrics, set a high weight and a strict goal of 0.
if metric in ('errors', 'warnings', 'drvs', 'holdwns', 'setupwns', 'holdtns', 'setuptns'):
    flow.get_graph_node(step, index).add_weight(metric, 1.0)
    flow.get_graph_node(step, index).add_goal(metric, 0)

# For "soft" optimization metrics, set a high weight but no specific goal.
elif metric in ('cellarea', 'peakpower', 'standbypower'):
    flow.get_graph_node(step, index).add_weight(metric, 1.0)
```

This configuration establishes:

- **Hard Constraints:** Critical violations like errors, DRCs, and setup/hold time violations have a weight of 1.0 and a goal of 0. Any run that fails to meet this goal is considered a failure.
- **Soft Constraints:** Key optimization targets like area and power also have a high weight of 1.0. The optimizer will work to minimize these values, but there is no single pass/fail number.


### 2. Reporting and Analysis

Metrics are used by the [`Project.summary()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.project.Project.summary) function to generate a dashboard view of the compilation results.
You can also access them directly with [`Project.get()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.project.Project.get) to create custom reports or to feed into your own analysis scripts.

```python
# Example: Get the cell area after the 'place' step
cell_area = proj.history("job0").get('metric', 'cellarea', step='place', index='0')
print(f"Cell area after placement: {cell_area} um^2")
```


### The Metric Lifecycle

Metrics are populated automatically during a run. For each [flowgraph node](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-flowgraph-node) -- one ([step](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-step), [index](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-index)) pair:

1. All metric values in the schema are cleared.
2. The tool (e.g., OpenROAD, Yosys) is executed.
3. The tool's [`Task.post_process()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.post_process) function runs, which parses the tool's log files and reports to extract the new metric values and save them to the schema.

If you are adding a new tool, you will need to implement a [`Task.post_process()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.post_process) function to parse its outputs.


### List of Available Metrics

The following table summarizes all metrics available in the SiliconCompiler schema.
For detailed descriptions of each, please refer to the [Schema](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#schema) section of the reference manual.


---

Source: https://docs.siliconcompiler.com/en/latest/development_guide/records.html

## Execution Records and Provenance

To support hardware provenance and ensure reproducibility, SiliconCompiler automatically records key information during every compilation run.
This creates a detailed history, or "provenance," for your design, which is crucial for tracking a complete and unbroken chain of custody from source code to final layout.


### What Information is Recorded?

Tracking is broken into two categories to protect potentially sensitive information by default.


#### Default Tracking (Always On)

For every run, SiliconCompiler will automatically record the following without any special configuration:

- **SiliconCompiler Version:** The exact version of the framework used.
- **Tool Details:** The version of each [tool](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-tool) executed (e.g., Yosys, OpenROAD) and the specific command-line options used.
- **Timestamps:** The start and end times for each [task](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-task).


#### Optional Full Tracking

You can enable a more detailed level of tracking that also records environmental information.

- **User:** The username of the person who initiated the run.
- **Machine:** The hostname of the machine where the run was executed.

> **Note**
> Please be aware that user and machine information can be considered sensitive.
> Use caution and ensure you are complying with your organization's privacy policies before enabling this feature, especially if you plan to share the results.


### Enabling Full Tracking

To capture all available provenance data, you must explicitly enable the [`[option,track]`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-project-option-track) parameter on your project object:

```python
import siliconcompiler

# Create a project object
proj = siliconcompiler.Project('my_design')

# Enable full tracking to record user and machine information
proj.option.set_track(True)

# ... continue with your compilation setup
```


### How Records Are Stored

[Records](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-record) are captured for each individual [flowgraph node](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-flowgraph-node) -- defined by its [step](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-step) and [index](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-index) -- with each node executing one [task](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-task).
This granular approach ensures that every action performed on the design is documented, leaving no gaps in the history of the compilation process.


---

Source: https://docs.siliconcompiler.com/en/latest/development_guide/options.html

## User Settings

SiliconCompiler provides a robust system for managing persistent user configuration across different sessions and tools.
This system allows you to define default behaviors--such as your preferred scheduler, remote processing credentials, or compilation flags--once, and have them automatically applied to every new [`Project`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.project.Project).

The settings are managed by a centralized [`SettingsManager`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.utils.settings.SettingsManager) which ensures thread-safe and process-safe access to the configuration file using file locking.
This is particularly important in environments where multiple SiliconCompiler processes (e.g., parallel build steps) might attempt to read or write settings simultaneously.
The user is not expected to directly interact with the [`SettingsManager`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.utils.settings.SettingsManager): the `sc-config settings` app changes settings from the command line, and the associated classes change them from Python.


### Storage Format

Settings are stored in a JSON file (typically located at `~/.sc/settings.json`).
The file is organized into **categories**, allowing different tools and subsystems within SiliconCompiler to maintain their own isolated configuration spaces.

The JSON structure generally looks like this:

```json
{
    "schema-options": {
        "scheduler,name": "slurm",
        "scheduler,queue": "hw_queue",
        "remote": true,
        "optmode": 2
    },
    "other-category": {
        "setting_name": "value"
    }
}
```

> **Note**
> The settings manager uses a "last-write-wins" policy per key and protects file integrity with strict error handling.
> If the settings file becomes malformed, the manager will log an error and start with an empty configuration to prevent crashes.


### Changing Settings

The [sc-config settings](https://docs.siliconcompiler.com/en/latest/reference_manual/apps.html#app-sc-config-settings) app lists, reads and changes settings, so `settings.json` need not be edited by hand:

```bash
# Every setting and its value, defaults included
sc-config settings list

# Change a setting, or put it back to its default
sc-config settings set cache cleanupdays 30
sc-config settings unset cache cleanupdays

# Add entries to a list, or remove them
sc-config settings add scheduler-slurm sharedpaths /nfs/tools
sc-config settings remove scheduler-slurm sharedpaths /nfs/tools

# Make an option the default for every project
sc-config settings set schema-options scheduler,name slurm
```

A value is checked before it is written: a key the app does not know, or a value of the wrong type, is refused rather than saved.
`set` replaces a whole list; `add` and `remove` change one in place, starting from the list in effect, a system default included.
`-raw` writes any category and key, reading the value as JSON.
A setting the system file fixes (see below) cannot be changed, and the app says so.


### Declaring a Setting

A module that reads a setting declares it once, as a [`Setting`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.utils.settings.Setting), and reads it through [`Setting.get()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.utils.settings.Setting.get), so its default is written in one place:

```python
from siliconcompiler.utils.settings import Setting, SettingsCategory

REGION = Setting("record", "region", "str", "local",
                 "the region recorded in every run's manifest")
RECORD_SETTINGS = SettingsCategory("record", REGION)

region = REGION.get()
```

Declaring a setting reads nothing.
`sc-config` lists and changes the categories its `settings` command imports, in `siliconcompiler/utils/settings.py`, so a new category is added there too.
A category whose keys the user names, such as a file extension, is a [`KeyedSettingsCategory`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.utils.settings.KeyedSettingsCategory).


### System-Wide Defaults

In addition to the per-user file, SiliconCompiler can read a **system-wide settings file** managed by an administrator.
This is useful on shared machines--such as an HPC login node--where an administrator wants to provide sensible defaults (for example, cluster-wide Slurm `sharedpaths`) to every user without asking each of them to configure their own `~/.sc/settings.json`.

The system-wide file uses the same JSON structure as the per-user file. Its location is resolved in the following order:

1. The `SC_SYSTEM_SETTINGS` environment variable, if set, is used verbatim as the path to the file.
  This is the recommended override for non-root installs, virtual environments, containers, and continuous integration.
2. Otherwise, a platform-specific default location is used:

  - Linux/macOS: `/etc/siliconcompiler/settings.json`
  - Windows: `%PROGRAMDATA%\siliconcompiler\settings.json` (typically `C:\ProgramData\siliconcompiler\settings.json`)

> **Note**
> The default system location (`/etc`) requires administrator privileges to write, which is intentional: only an administrator should be able to change machine-wide defaults.
> Users who need their own machine-wide file without root access should point `SC_SYSTEM_SETTINGS` at a writable location.


#### Precedence and System Priority

By default, system-wide values act as **defaults** that a user may override in their own `~/.sc/settings.json`. When resolving a setting, SiliconCompiler applies the following precedence:

1. If the setting has **system priority**, the system value is used and the user value is ignored.
2. Otherwise, the user value is used if present.
3. Otherwise, the (plain) system default is used if present.
4. Otherwise, the built-in default is used.

An administrator can promote any default to a **system-priority** (non-overridable) value by co-locating a flag with the value.
Instead of writing a bare value, write an object with a `"system_priority"` flag (and, optionally, a `"value"`):

```json
{
    "record": {
        "region": {"value": "us-east-1", "system_priority": true}
    },
    "scheduler-slurm": {
        "sharedpaths": ["/nfs/tools"]
    }
}
```

In this example every user is pinned to `region = us-east-1` (it cannot be overridden), while `sharedpaths` is a plain default that users may override.
Attempts to change or delete a system-priority setting are ignored with a warning.
A priority wrapper may also omit `"value"` (e.g. `{"system_priority": true}`) to force a setting to stay unset, so callers fall back to their built-in default.

> **Note**
> Priority flags are only honored in the **system** file. A value written in this `{"value": ..., "system_priority": ...}` shape inside a user's `settings.json` is treated as an ordinary dictionary value, so existing user files are unaffected by this feature. User files are never modified to include system defaults; saving only ever writes the user's own values.


### Concurrency & Safety

The underlying [`SettingsManager`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.utils.settings.SettingsManager) utilizes a file lock (`.lock`) alongside the JSON file. This ensures that:

1. **Atomic Writes**: A save writes the settings to a temporary file beside `settings.json` and renames it into place, so a crash or an error part way through leaves the previous file whole. A symlinked `settings.json` is followed and its target replaced.
2. **Process Safety**: A change that another run may also be making goes through [`SettingsManager.transaction()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.utils.settings.SettingsManager.transaction), which re-reads the file under the lock before changing it, so neither run puts back a stale copy over the other's write. [`OptionSchema.write_defaults()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.option.OptionSchema.write_defaults) works this way. The lock also keeps out the other threads of the same process.
3. **Error Recovery**: Waiting for the lock is bounded by a timeout (default 1.0s), so your build pipeline doesn't hang indefinitely.
  If the file cannot be loaded when SiliconCompiler starts, an error is logged and SiliconCompiler continues with empty settings.
  Where the lock was not had in time or the file could not be read, a later plain save then refuses rather than write that empty copy over the file.
  A transaction, or a save, that cannot get the lock raises [`TimeoutError`](https://docs.python.org/3/builtins/exceptions.html#TimeoutError) and writes nothing.
  A malformed `settings.json` is never replaced by a transaction: fix or delete it. A plain save does replace one, with the settings in memory.
4. **Filesystems Without Locking**: Where `~/.sc` is on a filesystem that cannot lock files, such as an NFS home directory mounted without lock support, a held lock is marked instead by a `settings.json.sc_lock` file, deleted on release.
  A process killed while holding it leaves that file behind, and every later save waits out its timeout and names it: delete it once no SiliconCompiler process is running.


### Schema Defaults (The 'schema-options' Category)

The most common use case for user settings is defining default values for the SiliconCompiler [`OptionSchema`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.option.OptionSchema).
When a new [`Project`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.project.Project) is initialized, it automatically queries the settings manager for the `schema-options` category.


#### Key Mapping

Because the Schema is hierarchical (e.g., [`[option,scheduler,name]`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-project-option-scheduler-name)), the keys in the JSON settings file are flattened using comma separation.

- Schema path: [`[option,scheduler,name]`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-project-option-scheduler-name) \rightarrow JSON key: `"scheduler,name"`
- Schema path: [`[option,remote]`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-project-option-remote) \rightarrow JSON key: `"remote"`


##### Workflow: Schema Defaults

1. **Loading Defaults**:
  When you instantiate a project, SiliconCompiler automatically loads values from the settings file. These values act as the baseline defaults.

  ```python
  # If settings.json contains "scheduler,name": "slurm"
  project = siliconcompiler.Project()

  # The project starts with slurm enabled
  print(project.option.scheduler.get_name())
  # Output: slurm
  ```
2. **Saving Defaults**:
  You can programmatically save your current configuration as the new user default using [`OptionSchema.write_defaults()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.option.OptionSchema.write_defaults).
  This method compares your current configuration against the built-in defaults and saves only the modified parameters to the `schema-options` category in the settings file.

  ```python
  import siliconcompiler

  project = siliconcompiler.Project()

  # Configure your preferred environment
  project.option.scheduler.set_name("slurm")
  project.option.scheduler.set_queue("priority_queue")
  project.option.set_quiet(True)

  # Persist these settings to disk
  project.option.write_defaults()

  # Now, any future script you run will default to using Slurm on the 'priority_queue'
  # with quiet logging enabled.
  ```

  Only the `schema-options` category is replaced; the rest of the file is kept.
  With every option back at its default, [`OptionSchema.write_defaults()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.option.OptionSchema.write_defaults) removes the category, which resets your defaults.

  From the command line, `sc-config settings set schema-options <keypath> <value>` saves one default at a time and leaves the others alone.
  Options that describe one run, such as [`[option,flow]`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-project-option-flow) and [`[option,fileset]`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-project-option-fileset), are not saved by either.


### Slurm Scheduler Settings (The 'scheduler-slurm' Category)

In addition to the standard schema options, specific schedulers may require their own configuration settings.
For example, the Slurm scheduler uses the `scheduler-slurm` category to manage cluster-specific behaviors.

**Shared Paths**

One key setting for Slurm is `sharedpaths`.
This defines a list of directory prefixes that are available on all nodes in the cluster (e.g., via NFS or GPFS).
When SiliconCompiler runs on a compute node, it checks if input files are located within these shared paths.
If they are, the files are used directly; otherwise, they are copied to the build directory to ensure accessibility.
This optimization significantly reduces network traffic and disk usage for large designs.

```json
{
    "scheduler-slurm": {
        "sharedpaths": ["/nfs/tools", "/work/project"]
    }
}
```


#### Workflow: Slurm Settings

Unlike standard schema options, scheduler-specific settings (like `sharedpaths`) are stored in their own category.

```bash
# These paths must be visible on all compute nodes.
sc-config settings set scheduler-slurm sharedpaths /nfs/tools /work/project
```


### Show Task Preferences (The 'showtask' Category)

SiliconCompiler allows you to define preferred viewers for specific file extensions.
This is useful when multiple tools are capable of opening a specific file type (e.g., both KLayout and OpenROAD can view `.def` files) and you want to enforce a specific default.

This configuration is stored in the `showtask` category of your `settings.json` file. The key is the file extension (without the dot), and the value is the name of the tool (and optionally the task).

**Example Configuration**

```json
{
    "showtask": {
        "gds": "klayout",
        "def": "openroad/show",
        "vcd": "gtkwave"
    }
}
```

In this example:

- `.gds` files will always open with KLayout.
- `.def` files will always open with OpenROAD, specifically using the `show` task.
- `.vcd` files will always open with GTKWave.

If the preferred tool is not found or not registered, SiliconCompiler will fall back to its default discovery mechanism.

`sc-config settings set showtask gds klayout` sets one, and refuses a tool that cannot open that extension.
The `opentask` category works the same way for the interactive tool a file is opened in.


### Cache Cleanup Settings (The 'cache' Category)

The data source cache in `~/.sc/cache/dataroot` grows every time a project asks
for a version of a PDK, library, or design that is not already there, and nothing
in a normal run removes what an older project needed.
At the start of every run SiliconCompiler sweeps that area and deletes entries
that have gone unused, along with the lock files of entries that are already
gone. The cache's other area, `tools/`, is left alone: a tool that keeps a
cache between runs caps it itself, so there is nothing here to tune for it.

The sweep is deliberately conservative, because nothing asked for it: it runs at
most once a week per cache directory and only collects entries that have not been
resolved in 90 days. Orphaned lock files are collected whatever their age -- an
empty file guarding a directory that no longer exists is residue, and a lock
costs nothing to recreate -- except one taken in the last hour, which may belong
to a download that has yet to create its directory.
Deleting a cache entry costs a download, not data -- it is fetched again the next
time something resolves it.
The `cache` category tunes both numbers:

```json
{
    "cache": {
        "cleanupdays": 30,
        "cleanupinterval": 1
    }
}
```

- `cleanupdays` -- days an entry must go unused before it is collected
  (default 90); orphaned lock files ignore it. Set it to `0` to turn the
  automatic sweep off entirely.
- `cleanupinterval` -- minimum days between two sweeps of the same cache
  directory (default 7).

Each cache directory records when it was last swept in a `.sc_cleanup` file,
which is how the interval is enforced across independent runs.
An entry's last-use time is the modification time of its `.lock` file, which
every resolve stamps -- including one that hits the cache and downloads nothing.

To sweep on demand, or with a different threshold, use
[sc-config cache](https://docs.siliconcompiler.com/en/latest/reference_manual/apps.html#app-sc-config-cache), which also shows the cache's size
and when it was last swept:

```bash
sc-config cache clean -days 30 -dryrun
sc-config cache show
```


### Record Settings (The 'record' Category)

The `record` category allows you to define metadata about the execution environment, which is useful for tracking and aggregating results across different cloud regions or clusters.

**Example Configuration**

```json
{
    "record": {
        "region": "us-east-1"
    }
}
```

In this example, the `region` key specifies the cloud region.
This information is retrieved by the schema support tools to tag records with the appropriate environment details.
If omitted, the region defaults to `local`.


---

Source: https://docs.siliconcompiler.com/en/latest/reference_manual/index.html

## References

The following sections provides details on the functions, modules and objects included in SiliconCompiler.
To learn how to use SiliconCompiler, see the [user guide](https://docs.siliconcompiler.com/en/latest/user_guide/index.html#user-guide).

Building Blocks[Targets](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/targets.html)[Flows](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/flows.html)[Tools](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/tools.html)[PDKs](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/pdks.html)[Libraries](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/libs.html)[Checklists](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/checklists.html)[Data Sources](https://docs.siliconcompiler.com/en/latest/reference_manual/predef_modules/resolvers.html)

API References[Schema](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html)[Parameter Fields](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#parameter-fields)[Per-node Parameter Fields](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#per-node-parameter-fields)[Project Parameters](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#project-parameters)[Project](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#project)[arg](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-project-arg)[checklist](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-project-checklist)[flowgraph](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-project-flowgraph)[history](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-project-history)[library](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-project-library)[metric](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-project-metric)[option](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-project-option)[record](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-project-record)[schemaversion](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-project-schemaversion)[tool](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-project-tool)[ASIC](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#asic)[arg](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-asic-arg)[asic](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-asic-asic)[checklist](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-asic-checklist)[constraint](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-asic-constraint)[flowgraph](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-asic-flowgraph)[history](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-asic-history)[library](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-asic-library)[metric](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-asic-metric)[option](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-asic-option)[record](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-asic-record)[schemaversion](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-asic-schemaversion)[tool](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-asic-tool)[FPGA](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#fpga)[arg](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-fpga-arg)[checklist](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-fpga-checklist)[constraint](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-fpga-constraint)[flowgraph](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-fpga-flowgraph)[fpga](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-fpga-fpga)[history](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-fpga-history)[library](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-fpga-library)[metric](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-fpga-metric)[option](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-fpga-option)[record](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-fpga-record)[schemaversion](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-fpga-schemaversion)[tool](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-fpga-tool)[Lint](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#lint)[arg](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-lint-arg)[checklist](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-lint-checklist)[flowgraph](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-lint-flowgraph)[history](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-lint-history)[library](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-lint-library)[metric](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-lint-metric)[option](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-lint-option)[record](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-lint-record)[schemaversion](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-lint-schemaversion)[tool](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-lint-tool)[Sim](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#sim)[arg](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-sim-arg)[checklist](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-sim-checklist)[flowgraph](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-sim-flowgraph)[history](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-sim-history)[library](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-sim-library)[metric](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-sim-metric)[option](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-sim-option)[record](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-sim-record)[schemaversion](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-sim-schemaversion)[tool](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-sim-tool)[Library Parameters](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#library-parameters)[General](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#general)[Design](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#design)[ASIC Specific](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#asic-specific)[StdCellLibrary](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#stdcelllibrary)[PDK](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#pdk)[FPGA Specific](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#fpga-specific)[FPGADevice](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#fpgadevice)[meta data](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#meta-data)[Journaling](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#journaling)[Schema API](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html)[Useful APIs](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#useful-apis)[Project Classes](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#project-classes)[`Project`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.project.Project)[`Project.add()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.project.Project.add)[`Project.add_alias()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.project.Project.add_alias)[`Project.add_dep()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.project.Project.add_dep)[`Project.add_fileset()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.project.Project.add_fileset)[`Project.allkeys()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.project.Project.allkeys)[`Project.check_filepaths()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.project.Project.check_filepaths)[`Project.check_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.project.Project.check_manifest)[`Project.convert()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.project.Project.convert)[`Project.copy()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.project.Project.copy)[`Project.create_cmdline()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.project.Project.create_cmdline)[`Project.design`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.project.Project.design)[`Project.find_files()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.project.Project.find_files)[`Project.find_result()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.project.Project.find_result)[`Project.from_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.project.Project.from_manifest)[`Project.get()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.project.Project.get)[`Project.get_filesets()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.project.Project.get_filesets)[`Project.get_flow()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.project.Project.get_flow)[`Project.get_library()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.project.Project.get_library)[`Project.getdict()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.project.Project.getdict)[`Project.getkeys()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.project.Project.getkeys)[`Project.hash_files()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.project.Project.hash_files)[`Project.history()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.project.Project.history)[`Project.logger`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.project.Project.logger)[`Project.name`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.project.Project.name)[`Project.option`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.project.Project.option)[`Project.read_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.project.Project.read_manifest)[`Project.remove()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.project.Project.remove)[`Project.run()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.project.Project.run)[`Project.set()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.project.Project.set)[`Project.set_design()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.project.Project.set_design)[`Project.set_flow()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.project.Project.set_flow)[`Project.show()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.project.Project.show)[`Project.snapshot()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.project.Project.snapshot)[`Project.summary()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.project.Project.summary)[`Project.unset()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.project.Project.unset)[`Project.valid()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.project.Project.valid)[`Project.write_depgraph()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.project.Project.write_depgraph)[`Project.write_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.project.Project.write_manifest)[`ASIC`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.ASIC)[`ASIC.add()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.ASIC.add)[`ASIC.add_alias()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.ASIC.add_alias)[`ASIC.add_asiclib()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.ASIC.add_asiclib)[`ASIC.add_dep()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.ASIC.add_dep)[`ASIC.add_fileset()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.ASIC.add_fileset)[`ASIC.allkeys()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.ASIC.allkeys)[`ASIC.check_filepaths()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.ASIC.check_filepaths)[`ASIC.check_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.ASIC.check_manifest)[`ASIC.constraint`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.ASIC.constraint)[`ASIC.convert()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.ASIC.convert)[`ASIC.copy()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.ASIC.copy)[`ASIC.create_cmdline()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.ASIC.create_cmdline)[`ASIC.design`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.ASIC.design)[`ASIC.find_files()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.ASIC.find_files)[`ASIC.find_result()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.ASIC.find_result)[`ASIC.from_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.ASIC.from_manifest)[`ASIC.get()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.ASIC.get)[`ASIC.get_filesets()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.ASIC.get_filesets)[`ASIC.get_flow()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.ASIC.get_flow)[`ASIC.get_library()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.ASIC.get_library)[`ASIC.getdict()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.ASIC.getdict)[`ASIC.getkeys()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.ASIC.getkeys)[`ASIC.hash_files()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.ASIC.hash_files)[`ASIC.history()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.ASIC.history)[`ASIC.logger`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.ASIC.logger)[`ASIC.name`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.ASIC.name)[`ASIC.option`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.ASIC.option)[`ASIC.read_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.ASIC.read_manifest)[`ASIC.remove()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.ASIC.remove)[`ASIC.run()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.ASIC.run)[`ASIC.set()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.ASIC.set)[`ASIC.set_asic_delaymodel()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.ASIC.set_asic_delaymodel)[`ASIC.set_asic_routinglayers()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.ASIC.set_asic_routinglayers)[`ASIC.set_design()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.ASIC.set_design)[`ASIC.set_flow()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.ASIC.set_flow)[`ASIC.set_mainlib()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.ASIC.set_mainlib)[`ASIC.set_pdk()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.ASIC.set_pdk)[`ASIC.show()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.ASIC.show)[`ASIC.snapshot()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.ASIC.snapshot)[`ASIC.summary()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.ASIC.summary)[`ASIC.unset()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.ASIC.unset)[`ASIC.valid()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.ASIC.valid)[`ASIC.write_depgraph()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.ASIC.write_depgraph)[`ASIC.write_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.ASIC.write_manifest)[`FPGA`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGA)[`FPGA.add()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGA.add)[`FPGA.add_alias()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGA.add_alias)[`FPGA.add_dep()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGA.add_dep)[`FPGA.add_fileset()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGA.add_fileset)[`FPGA.allkeys()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGA.allkeys)[`FPGA.check_filepaths()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGA.check_filepaths)[`FPGA.check_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGA.check_manifest)[`FPGA.constraint`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGA.constraint)[`FPGA.convert()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGA.convert)[`FPGA.copy()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGA.copy)[`FPGA.create_cmdline()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGA.create_cmdline)[`FPGA.design`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGA.design)[`FPGA.find_files()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGA.find_files)[`FPGA.find_result()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGA.find_result)[`FPGA.from_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGA.from_manifest)[`FPGA.get()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGA.get)[`FPGA.get_filesets()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGA.get_filesets)[`FPGA.get_flow()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGA.get_flow)[`FPGA.get_library()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGA.get_library)[`FPGA.getdict()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGA.getdict)[`FPGA.getkeys()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGA.getkeys)[`FPGA.hash_files()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGA.hash_files)[`FPGA.history()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGA.history)[`FPGA.logger`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGA.logger)[`FPGA.name`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGA.name)[`FPGA.option`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGA.option)[`FPGA.read_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGA.read_manifest)[`FPGA.remove()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGA.remove)[`FPGA.run()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGA.run)[`FPGA.set()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGA.set)[`FPGA.set_design()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGA.set_design)[`FPGA.set_flow()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGA.set_flow)[`FPGA.set_fpga()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGA.set_fpga)[`FPGA.show()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGA.show)[`FPGA.snapshot()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGA.snapshot)[`FPGA.summary()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGA.summary)[`FPGA.unset()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGA.unset)[`FPGA.valid()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGA.valid)[`FPGA.write_depgraph()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGA.write_depgraph)[`FPGA.write_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGA.write_manifest)[`Lint`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Lint)[`Lint.add()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Lint.add)[`Lint.add_alias()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Lint.add_alias)[`Lint.add_dep()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Lint.add_dep)[`Lint.add_fileset()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Lint.add_fileset)[`Lint.allkeys()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Lint.allkeys)[`Lint.check_filepaths()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Lint.check_filepaths)[`Lint.check_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Lint.check_manifest)[`Lint.convert()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Lint.convert)[`Lint.copy()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Lint.copy)[`Lint.create_cmdline()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Lint.create_cmdline)[`Lint.design`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Lint.design)[`Lint.find_files()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Lint.find_files)[`Lint.find_result()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Lint.find_result)[`Lint.from_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Lint.from_manifest)[`Lint.get()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Lint.get)[`Lint.get_filesets()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Lint.get_filesets)[`Lint.get_flow()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Lint.get_flow)[`Lint.get_library()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Lint.get_library)[`Lint.getdict()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Lint.getdict)[`Lint.getkeys()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Lint.getkeys)[`Lint.hash_files()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Lint.hash_files)[`Lint.history()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Lint.history)[`Lint.logger`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Lint.logger)[`Lint.name`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Lint.name)[`Lint.option`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Lint.option)[`Lint.read_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Lint.read_manifest)[`Lint.remove()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Lint.remove)[`Lint.run()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Lint.run)[`Lint.set()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Lint.set)[`Lint.set_design()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Lint.set_design)[`Lint.set_flow()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Lint.set_flow)[`Lint.show()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Lint.show)[`Lint.snapshot()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Lint.snapshot)[`Lint.summary()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Lint.summary)[`Lint.unset()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Lint.unset)[`Lint.valid()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Lint.valid)[`Lint.write_depgraph()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Lint.write_depgraph)[`Lint.write_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Lint.write_manifest)[`Sim`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Sim)[`Sim.add()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Sim.add)[`Sim.add_alias()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Sim.add_alias)[`Sim.add_dep()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Sim.add_dep)[`Sim.add_fileset()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Sim.add_fileset)[`Sim.allkeys()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Sim.allkeys)[`Sim.check_filepaths()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Sim.check_filepaths)[`Sim.check_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Sim.check_manifest)[`Sim.convert()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Sim.convert)[`Sim.copy()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Sim.copy)[`Sim.create_cmdline()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Sim.create_cmdline)[`Sim.design`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Sim.design)[`Sim.find_files()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Sim.find_files)[`Sim.find_result()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Sim.find_result)[`Sim.from_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Sim.from_manifest)[`Sim.get()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Sim.get)[`Sim.get_filesets()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Sim.get_filesets)[`Sim.get_flow()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Sim.get_flow)[`Sim.get_library()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Sim.get_library)[`Sim.getdict()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Sim.getdict)[`Sim.getkeys()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Sim.getkeys)[`Sim.hash_files()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Sim.hash_files)[`Sim.history()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Sim.history)[`Sim.logger`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Sim.logger)[`Sim.name`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Sim.name)[`Sim.option`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Sim.option)[`Sim.read_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Sim.read_manifest)[`Sim.remove()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Sim.remove)[`Sim.run()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Sim.run)[`Sim.set()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Sim.set)[`Sim.set_design()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Sim.set_design)[`Sim.set_flow()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Sim.set_flow)[`Sim.show()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Sim.show)[`Sim.snapshot()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Sim.snapshot)[`Sim.summary()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Sim.summary)[`Sim.unset()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Sim.unset)[`Sim.valid()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Sim.valid)[`Sim.write_depgraph()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Sim.write_depgraph)[`Sim.write_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Sim.write_manifest)[User Classes](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#user-classes)[`Design`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Design)[`Design.active_dataroot()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Design.active_dataroot)[`Design.active_fileset()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Design.active_fileset)[`Design.add()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Design.add)[`Design.add_define()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Design.add_define)[`Design.add_dep()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Design.add_dep)[`Design.add_depfileset()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Design.add_depfileset)[`Design.add_file()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Design.add_file)[`Design.add_idir()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Design.add_idir)[`Design.add_lib()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Design.add_lib)[`Design.add_libdir()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Design.add_libdir)[`Design.add_undefine()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Design.add_undefine)[`Design.allkeys()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Design.allkeys)[`Design.check_filepaths()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Design.check_filepaths)[`Design.copy()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Design.copy)[`Design.copy_fileset()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Design.copy_fileset)[`Design.find_files()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Design.find_files)[`Design.from_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Design.from_manifest)[`Design.get()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Design.get)[`Design.get_dataroot()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Design.get_dataroot)[`Design.get_define()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Design.get_define)[`Design.get_dep()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Design.get_dep)[`Design.get_depfileset()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Design.get_depfileset)[`Design.get_file()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Design.get_file)[`Design.get_fileset()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Design.get_fileset)[`Design.get_idir()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Design.get_idir)[`Design.get_lib()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Design.get_lib)[`Design.get_libdir()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Design.get_libdir)[`Design.get_param()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Design.get_param)[`Design.get_topmodule()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Design.get_topmodule)[`Design.get_undefine()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Design.get_undefine)[`Design.getdict()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Design.getdict)[`Design.getkeys()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Design.getkeys)[`Design.has_dep()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Design.has_dep)[`Design.has_file()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Design.has_file)[`Design.has_fileset()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Design.has_fileset)[`Design.has_idir()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Design.has_idir)[`Design.has_libdir()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Design.has_libdir)[`Design.hash_files()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Design.hash_files)[`Design.name`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Design.name)[`Design.package`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Design.package)[`Design.read_fileset()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Design.read_fileset)[`Design.read_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Design.read_manifest)[`Design.remove()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Design.remove)[`Design.remove_dep()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Design.remove_dep)[`Design.set()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Design.set)[`Design.set_dataroot()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Design.set_dataroot)[`Design.set_name()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Design.set_name)[`Design.set_param()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Design.set_param)[`Design.set_topmodule()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Design.set_topmodule)[`Design.type()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Design.type)[`Design.unset()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Design.unset)[`Design.valid()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Design.valid)[`Design.write_depgraph()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Design.write_depgraph)[`Design.write_fileset()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Design.write_fileset)[`Design.write_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Design.write_manifest)[`PDK`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.PDK)[`PDK.active_dataroot()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.PDK.active_dataroot)[`PDK.active_fileset()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.PDK.active_fileset)[`PDK.add()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.PDK.add)[`PDK.add_aprtechfileset()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.PDK.add_aprtechfileset)[`PDK.add_define()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.PDK.add_define)[`PDK.add_dep()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.PDK.add_dep)[`PDK.add_depfileset()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.PDK.add_depfileset)[`PDK.add_devmodelfileset()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.PDK.add_devmodelfileset)[`PDK.add_displayfileset()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.PDK.add_displayfileset)[`PDK.add_file()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.PDK.add_file)[`PDK.add_idir()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.PDK.add_idir)[`PDK.add_layermapfileset()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.PDK.add_layermapfileset)[`PDK.add_lib()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.PDK.add_lib)[`PDK.add_libdir()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.PDK.add_libdir)[`PDK.add_pexmodelfileset()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.PDK.add_pexmodelfileset)[`PDK.add_runsetfileset()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.PDK.add_runsetfileset)[`PDK.add_undefine()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.PDK.add_undefine)[`PDK.add_waiverfileset()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.PDK.add_waiverfileset)[`PDK.allkeys()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.PDK.allkeys)[`PDK.calc_dpw()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.PDK.calc_dpw)[`PDK.calc_yield()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.PDK.calc_yield)[`PDK.check_filepaths()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.PDK.check_filepaths)[`PDK.copy()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.PDK.copy)[`PDK.copy_fileset()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.PDK.copy_fileset)[`PDK.define_tool_parameter()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.PDK.define_tool_parameter)[`PDK.find_files()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.PDK.find_files)[`PDK.from_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.PDK.from_manifest)[`PDK.get()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.PDK.get)[`PDK.get_dataroot()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.PDK.get_dataroot)[`PDK.get_define()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.PDK.get_define)[`PDK.get_dep()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.PDK.get_dep)[`PDK.get_depfileset()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.PDK.get_depfileset)[`PDK.get_file()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.PDK.get_file)[`PDK.get_fileset()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.PDK.get_fileset)[`PDK.get_idir()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.PDK.get_idir)[`PDK.get_lib()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.PDK.get_lib)[`PDK.get_libdir()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.PDK.get_libdir)[`PDK.get_param()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.PDK.get_param)[`PDK.get_topmodule()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.PDK.get_topmodule)[`PDK.get_undefine()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.PDK.get_undefine)[`PDK.getdict()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.PDK.getdict)[`PDK.getkeys()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.PDK.getkeys)[`PDK.has_dep()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.PDK.has_dep)[`PDK.has_file()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.PDK.has_file)[`PDK.has_fileset()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.PDK.has_fileset)[`PDK.has_idir()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.PDK.has_idir)[`PDK.has_libdir()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.PDK.has_libdir)[`PDK.hash_files()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.PDK.hash_files)[`PDK.name`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.PDK.name)[`PDK.package`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.PDK.package)[`PDK.read_fileset()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.PDK.read_fileset)[`PDK.read_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.PDK.read_manifest)[`PDK.remove()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.PDK.remove)[`PDK.remove_dep()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.PDK.remove_dep)[`PDK.set()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.PDK.set)[`PDK.set_aprroutinglayers()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.PDK.set_aprroutinglayers)[`PDK.set_dataroot()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.PDK.set_dataroot)[`PDK.set_defectdensity()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.PDK.set_defectdensity)[`PDK.set_edgemargin()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.PDK.set_edgemargin)[`PDK.set_foundry()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.PDK.set_foundry)[`PDK.set_name()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.PDK.set_name)[`PDK.set_node()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.PDK.set_node)[`PDK.set_param()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.PDK.set_param)[`PDK.set_scribewidth()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.PDK.set_scribewidth)[`PDK.set_stackup()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.PDK.set_stackup)[`PDK.set_topmodule()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.PDK.set_topmodule)[`PDK.set_unitcost()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.PDK.set_unitcost)[`PDK.set_wafersize()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.PDK.set_wafersize)[`PDK.type()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.PDK.type)[`PDK.unset()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.PDK.unset)[`PDK.valid()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.PDK.valid)[`PDK.write_depgraph()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.PDK.write_depgraph)[`PDK.write_fileset()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.PDK.write_fileset)[`PDK.write_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.PDK.write_manifest)[`Flowgraph`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Flowgraph)[`Flowgraph.add()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Flowgraph.add)[`Flowgraph.allkeys()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Flowgraph.allkeys)[`Flowgraph.check_node_name()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Flowgraph.check_node_name)[`Flowgraph.copy()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Flowgraph.copy)[`Flowgraph.edge()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Flowgraph.edge)[`Flowgraph.from_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Flowgraph.from_manifest)[`Flowgraph.get()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Flowgraph.get)[`Flowgraph.get_all_tasks()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Flowgraph.get_all_tasks)[`Flowgraph.get_entry_nodes()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Flowgraph.get_entry_nodes)[`Flowgraph.get_execution_order()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Flowgraph.get_execution_order)[`Flowgraph.get_exit_nodes()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Flowgraph.get_exit_nodes)[`Flowgraph.get_graph_node()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Flowgraph.get_graph_node)[`Flowgraph.get_node_outputs()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Flowgraph.get_node_outputs)[`Flowgraph.get_nodes()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Flowgraph.get_nodes)[`Flowgraph.get_task_module()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Flowgraph.get_task_module)[`Flowgraph.getdict()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Flowgraph.getdict)[`Flowgraph.getkeys()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Flowgraph.getkeys)[`Flowgraph.graph()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Flowgraph.graph)[`Flowgraph.insert_node()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Flowgraph.insert_node)[`Flowgraph.make_docs()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Flowgraph.make_docs)[`Flowgraph.name`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Flowgraph.name)[`Flowgraph.node()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Flowgraph.node)[`Flowgraph.read_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Flowgraph.read_manifest)[`Flowgraph.remove()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Flowgraph.remove)[`Flowgraph.remove_node()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Flowgraph.remove_node)[`Flowgraph.rename_node()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Flowgraph.rename_node)[`Flowgraph.set()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Flowgraph.set)[`Flowgraph.set_name()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Flowgraph.set_name)[`Flowgraph.type()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Flowgraph.type)[`Flowgraph.unset()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Flowgraph.unset)[`Flowgraph.valid()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Flowgraph.valid)[`Flowgraph.validate()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Flowgraph.validate)[`Flowgraph.write_flowgraph()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Flowgraph.write_flowgraph)[`Flowgraph.write_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Flowgraph.write_manifest)[`Checklist`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Checklist)[`Checklist.add()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Checklist.add)[`Checklist.allkeys()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Checklist.allkeys)[`Checklist.check()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Checklist.check)[`Checklist.copy()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Checklist.copy)[`Checklist.from_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Checklist.from_manifest)[`Checklist.get()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Checklist.get)[`Checklist.get_criteria()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Checklist.get_criteria)[`Checklist.getdict()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Checklist.getdict)[`Checklist.getkeys()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Checklist.getkeys)[`Checklist.make_criteria()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Checklist.make_criteria)[`Checklist.name`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Checklist.name)[`Checklist.read_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Checklist.read_manifest)[`Checklist.remove()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Checklist.remove)[`Checklist.set()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Checklist.set)[`Checklist.set_name()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Checklist.set_name)[`Checklist.type()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Checklist.type)[`Checklist.unset()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Checklist.unset)[`Checklist.valid()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Checklist.valid)[`Checklist.write_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Checklist.write_manifest)[`Task`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task)[`Task._remote_inherits_env`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task._remote_inherits_env)[`Task._remote_toolname`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task._remote_toolname)[`Task.active_dataroot()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.active_dataroot)[`Task.add()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.add)[`Task.add_commandline_option()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.add_commandline_option)[`Task.add_input_file()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.add_input_file)[`Task.add_licenseserver()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.add_licenseserver)[`Task.add_output_file()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.add_output_file)[`Task.add_parameter()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.add_parameter)[`Task.add_postscript()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.add_postscript)[`Task.add_prescript()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.add_prescript)[`Task.add_regex()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.add_regex)[`Task.add_required_key()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.add_required_key)[`Task.add_sbom()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.add_sbom)[`Task.add_version()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.add_version)[`Task.add_vswitch()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.add_vswitch)[`Task.add_warningoff()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.add_warningoff)[`Task.allkeys()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.allkeys)[`Task.cachedir`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.cachedir)[`Task.check_exe_version()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.check_exe_version)[`Task.check_filepaths()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.check_filepaths)[`Task.compute_input_file_node_name()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.compute_input_file_node_name)[`Task.copy()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.copy)[`Task.design_name`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.design_name)[`Task.design_topmodule`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.design_topmodule)[`Task.find_files()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.find_files)[`Task.find_task()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.find_task)[`Task.from_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.from_manifest)[`Task.generate_replay_script()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.generate_replay_script)[`Task.get()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.get)[`Task.get_commandline_options()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.get_commandline_options)[`Task.get_dataroot()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.get_dataroot)[`Task.get_digest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.get_digest)[`Task.get_digest_keys()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.get_digest_keys)[`Task.get_exe()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.get_exe)[`Task.get_exe_version()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.get_exe_version)[`Task.get_files_from_input_nodes()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.get_files_from_input_nodes)[`Task.get_fileset_file_keys()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.get_fileset_file_keys)[`Task.get_logpath()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.get_logpath)[`Task.get_output_files()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.get_output_files)[`Task.get_runtime_arguments()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.get_runtime_arguments)[`Task.get_runtime_environmental_variables()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.get_runtime_environmental_variables)[`Task.get_tcl_variables()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.get_tcl_variables)[`Task.get_threads()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.get_threads)[`Task.getdict()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.getdict)[`Task.getkeys()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.getkeys)[`Task.has_breakpoint()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.has_breakpoint)[`Task.has_postscript()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.has_postscript)[`Task.has_prescript()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.has_prescript)[`Task.hash_files()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.hash_files)[`Task.index`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.index)[`Task.logger`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.logger)[`Task.make_docs()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.make_docs)[`Task.name`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.name)[`Task.node`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.node)[`Task.nodeworkdir`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.nodeworkdir)[`Task.normalize_version()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.normalize_version)[`Task.parse_version()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.parse_version)[`Task.post_process()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.post_process)[`Task.pre_process()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.pre_process)[`Task.read_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.read_manifest)[`Task.record_metric()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.record_metric)[`Task.remove()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.remove)[`Task.remove_stdio_sidecars()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.remove_stdio_sidecars)[`Task.replay_modes()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.replay_modes)[`Task.run()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.run)[`Task.run_task()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.run_task)[`Task.runtime()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.runtime)[`Task.runtime_options()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.runtime_options)[`Task.select_input_nodes()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.select_input_nodes)[`Task.set()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.set)[`Task.set_dataroot()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.set_dataroot)[`Task.set_environmentalvariable()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.set_environmentalvariable)[`Task.set_exe()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.set_exe)[`Task.set_logdestination()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.set_logdestination)[`Task.set_name()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.set_name)[`Task.set_path()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.set_path)[`Task.set_refdir()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.set_refdir)[`Task.set_script()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.set_script)[`Task.set_threads()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.set_threads)[`Task.setup()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.setup)[`Task.setup_work_directory()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.setup_work_directory)[`Task.step`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.step)[`Task.task()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.task)[`Task.tool()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.tool)[`Task.type()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.type)[`Task.unset()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.unset)[`Task.valid()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.valid)[`Task.write_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.write_manifest)[`Task.write_task_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.Task.write_task_manifest)[`FPGADevice`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGADevice)[`FPGADevice.active_dataroot()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGADevice.active_dataroot)[`FPGADevice.active_fileset()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGADevice.active_fileset)[`FPGADevice.add()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGADevice.add)[`FPGADevice.add_define()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGADevice.add_define)[`FPGADevice.add_dep()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGADevice.add_dep)[`FPGADevice.add_depfileset()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGADevice.add_depfileset)[`FPGADevice.add_file()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGADevice.add_file)[`FPGADevice.add_idir()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGADevice.add_idir)[`FPGADevice.add_lib()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGADevice.add_lib)[`FPGADevice.add_libdir()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGADevice.add_libdir)[`FPGADevice.add_undefine()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGADevice.add_undefine)[`FPGADevice.allkeys()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGADevice.allkeys)[`FPGADevice.check_filepaths()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGADevice.check_filepaths)[`FPGADevice.copy()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGADevice.copy)[`FPGADevice.copy_fileset()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGADevice.copy_fileset)[`FPGADevice.define_tool_parameter()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGADevice.define_tool_parameter)[`FPGADevice.find_files()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGADevice.find_files)[`FPGADevice.from_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGADevice.from_manifest)[`FPGADevice.get()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGADevice.get)[`FPGADevice.get_dataroot()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGADevice.get_dataroot)[`FPGADevice.get_define()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGADevice.get_define)[`FPGADevice.get_dep()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGADevice.get_dep)[`FPGADevice.get_depfileset()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGADevice.get_depfileset)[`FPGADevice.get_file()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGADevice.get_file)[`FPGADevice.get_fileset()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGADevice.get_fileset)[`FPGADevice.get_idir()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGADevice.get_idir)[`FPGADevice.get_lib()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGADevice.get_lib)[`FPGADevice.get_libdir()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGADevice.get_libdir)[`FPGADevice.get_param()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGADevice.get_param)[`FPGADevice.get_topmodule()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGADevice.get_topmodule)[`FPGADevice.get_undefine()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGADevice.get_undefine)[`FPGADevice.getdict()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGADevice.getdict)[`FPGADevice.getkeys()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGADevice.getkeys)[`FPGADevice.has_dep()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGADevice.has_dep)[`FPGADevice.has_file()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGADevice.has_file)[`FPGADevice.has_fileset()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGADevice.has_fileset)[`FPGADevice.has_idir()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGADevice.has_idir)[`FPGADevice.has_libdir()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGADevice.has_libdir)[`FPGADevice.hash_files()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGADevice.hash_files)[`FPGADevice.name`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGADevice.name)[`FPGADevice.package`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGADevice.package)[`FPGADevice.read_fileset()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGADevice.read_fileset)[`FPGADevice.read_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGADevice.read_manifest)[`FPGADevice.remove()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGADevice.remove)[`FPGADevice.remove_dep()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGADevice.remove_dep)[`FPGADevice.set()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGADevice.set)[`FPGADevice.set_dataroot()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGADevice.set_dataroot)[`FPGADevice.set_lutsize()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGADevice.set_lutsize)[`FPGADevice.set_name()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGADevice.set_name)[`FPGADevice.set_param()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGADevice.set_param)[`FPGADevice.set_partname()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGADevice.set_partname)[`FPGADevice.set_topmodule()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGADevice.set_topmodule)[`FPGADevice.type()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGADevice.type)[`FPGADevice.unset()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGADevice.unset)[`FPGADevice.valid()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGADevice.valid)[`FPGADevice.write_depgraph()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGADevice.write_depgraph)[`FPGADevice.write_fileset()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGADevice.write_fileset)[`FPGADevice.write_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.FPGADevice.write_manifest)[`StdCellLibrary`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.StdCellLibrary)[`StdCellLibrary.active_dataroot()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.StdCellLibrary.active_dataroot)[`StdCellLibrary.active_fileset()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.StdCellLibrary.active_fileset)[`StdCellLibrary.add()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.StdCellLibrary.add)[`StdCellLibrary.add_asic_aprfileset()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.StdCellLibrary.add_asic_aprfileset)[`StdCellLibrary.add_asic_celllist()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.StdCellLibrary.add_asic_celllist)[`StdCellLibrary.add_asic_libcornerfileset()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.StdCellLibrary.add_asic_libcornerfileset)[`StdCellLibrary.add_asic_pdk()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.StdCellLibrary.add_asic_pdk)[`StdCellLibrary.add_asic_pexcornerfileset()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.StdCellLibrary.add_asic_pexcornerfileset)[`StdCellLibrary.add_asic_site()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.StdCellLibrary.add_asic_site)[`StdCellLibrary.add_asic_stackup()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.StdCellLibrary.add_asic_stackup)[`StdCellLibrary.add_define()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.StdCellLibrary.add_define)[`StdCellLibrary.add_dep()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.StdCellLibrary.add_dep)[`StdCellLibrary.add_depfileset()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.StdCellLibrary.add_depfileset)[`StdCellLibrary.add_file()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.StdCellLibrary.add_file)[`StdCellLibrary.add_idir()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.StdCellLibrary.add_idir)[`StdCellLibrary.add_lib()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.StdCellLibrary.add_lib)[`StdCellLibrary.add_libdir()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.StdCellLibrary.add_libdir)[`StdCellLibrary.add_undefine()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.StdCellLibrary.add_undefine)[`StdCellLibrary.allkeys()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.StdCellLibrary.allkeys)[`StdCellLibrary.check_filepaths()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.StdCellLibrary.check_filepaths)[`StdCellLibrary.copy()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.StdCellLibrary.copy)[`StdCellLibrary.copy_fileset()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.StdCellLibrary.copy_fileset)[`StdCellLibrary.define_tool_parameter()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.StdCellLibrary.define_tool_parameter)[`StdCellLibrary.find_files()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.StdCellLibrary.find_files)[`StdCellLibrary.from_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.StdCellLibrary.from_manifest)[`StdCellLibrary.get()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.StdCellLibrary.get)[`StdCellLibrary.get_dataroot()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.StdCellLibrary.get_dataroot)[`StdCellLibrary.get_define()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.StdCellLibrary.get_define)[`StdCellLibrary.get_dep()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.StdCellLibrary.get_dep)[`StdCellLibrary.get_depfileset()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.StdCellLibrary.get_depfileset)[`StdCellLibrary.get_file()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.StdCellLibrary.get_file)[`StdCellLibrary.get_fileset()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.StdCellLibrary.get_fileset)[`StdCellLibrary.get_idir()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.StdCellLibrary.get_idir)[`StdCellLibrary.get_lib()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.StdCellLibrary.get_lib)[`StdCellLibrary.get_libdir()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.StdCellLibrary.get_libdir)[`StdCellLibrary.get_param()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.StdCellLibrary.get_param)[`StdCellLibrary.get_topmodule()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.StdCellLibrary.get_topmodule)[`StdCellLibrary.get_undefine()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.StdCellLibrary.get_undefine)[`StdCellLibrary.getdict()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.StdCellLibrary.getdict)[`StdCellLibrary.getkeys()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.StdCellLibrary.getkeys)[`StdCellLibrary.has_dep()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.StdCellLibrary.has_dep)[`StdCellLibrary.has_file()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.StdCellLibrary.has_file)[`StdCellLibrary.has_fileset()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.StdCellLibrary.has_fileset)[`StdCellLibrary.has_idir()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.StdCellLibrary.has_idir)[`StdCellLibrary.has_libdir()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.StdCellLibrary.has_libdir)[`StdCellLibrary.hash_files()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.StdCellLibrary.hash_files)[`StdCellLibrary.name`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.StdCellLibrary.name)[`StdCellLibrary.package`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.StdCellLibrary.package)[`StdCellLibrary.read_fileset()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.StdCellLibrary.read_fileset)[`StdCellLibrary.read_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.StdCellLibrary.read_manifest)[`StdCellLibrary.remove()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.StdCellLibrary.remove)[`StdCellLibrary.remove_dep()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.StdCellLibrary.remove_dep)[`StdCellLibrary.set()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.StdCellLibrary.set)[`StdCellLibrary.set_dataroot()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.StdCellLibrary.set_dataroot)[`StdCellLibrary.set_name()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.StdCellLibrary.set_name)[`StdCellLibrary.set_param()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.StdCellLibrary.set_param)[`StdCellLibrary.set_topmodule()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.StdCellLibrary.set_topmodule)[`StdCellLibrary.type()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.StdCellLibrary.type)[`StdCellLibrary.unset()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.StdCellLibrary.unset)[`StdCellLibrary.valid()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.StdCellLibrary.valid)[`StdCellLibrary.write_depgraph()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.StdCellLibrary.write_depgraph)[`StdCellLibrary.write_fileset()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.StdCellLibrary.write_fileset)[`StdCellLibrary.write_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.StdCellLibrary.write_manifest)[Tool Extension Classes](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#tool-extension-classes)[StdCellLibrary mixins](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#stdcelllibrary-mixins)[`OpenROADStdCellLibrary`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.tools.openroad.OpenROADStdCellLibrary)[`KLayoutLibrary`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.tools.klayout.KLayoutLibrary)[`YosysStdCellLibrary`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.tools.yosys.YosysStdCellLibrary)[`BambuStdCellLibrary`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.tools.bambu.BambuStdCellLibrary)[PDK mixins](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#pdk-mixins)[`OpenROADPDK`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.tools.openroad.OpenROADPDK)[`KLayoutPDK`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.tools.klayout.KLayoutPDK)[FPGADevice mixins](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#fpgadevice-mixins)[`YosysFPGA`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.tools.yosys.YosysFPGA)[`VPRFPGA`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.tools.vpr.VPRFPGA)[`OpenSTAFPGA`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.tools.opensta.OpenSTAFPGA)[KLayout operations](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#klayout-operations)[`KLayoutOperation`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.tools.klayout.operations.KLayoutOperation)[`Merge`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.tools.klayout.operations.Merge)[`Add`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.tools.klayout.operations.Add)[`Rotate`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.tools.klayout.operations.Rotate)[`Flatten`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.tools.klayout.operations.Flatten)[`Outline`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.tools.klayout.operations.Outline)[`RenameTop`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.tools.klayout.operations.RenameTop)[`AddTop`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.tools.klayout.operations.AddTop)[`RenameCell`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.tools.klayout.operations.RenameCell)[`SwapCell`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.tools.klayout.operations.SwapCell)[`DeleteLayers`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.tools.klayout.operations.DeleteLayers)[`MergeShapes`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.tools.klayout.operations.MergeShapes)[`ConvertProperty`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.tools.klayout.operations.ConvertProperty)[`Write`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.tools.klayout.operations.Write)[ASIC Constraint Classes](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#asic-constraint-classes)[`ASICConstraint`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.asic.ASICConstraint)[`ASICConstraint.add()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.asic.ASICConstraint.add)[`ASICConstraint.allkeys()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.asic.ASICConstraint.allkeys)[`ASICConstraint.area`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.asic.ASICConstraint.area)[`ASICConstraint.component`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.asic.ASICConstraint.component)[`ASICConstraint.copy()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.asic.ASICConstraint.copy)[`ASICConstraint.from_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.asic.ASICConstraint.from_manifest)[`ASICConstraint.get()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.asic.ASICConstraint.get)[`ASICConstraint.getdict()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.asic.ASICConstraint.getdict)[`ASICConstraint.getkeys()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.asic.ASICConstraint.getkeys)[`ASICConstraint.pin`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.asic.ASICConstraint.pin)[`ASICConstraint.read_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.asic.ASICConstraint.read_manifest)[`ASICConstraint.remove()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.asic.ASICConstraint.remove)[`ASICConstraint.set()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.asic.ASICConstraint.set)[`ASICConstraint.timing`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.asic.ASICConstraint.timing)[`ASICConstraint.unset()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.asic.ASICConstraint.unset)[`ASICConstraint.valid()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.asic.ASICConstraint.valid)[`ASICConstraint.write_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.asic.ASICConstraint.write_manifest)[`ASICTimingConstraintSchema`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICTimingConstraintSchema)[`ASICTimingConstraintSchema.add()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICTimingConstraintSchema.add)[`ASICTimingConstraintSchema.add_mode()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICTimingConstraintSchema.add_mode)[`ASICTimingConstraintSchema.add_scenario()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICTimingConstraintSchema.add_scenario)[`ASICTimingConstraintSchema.allkeys()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICTimingConstraintSchema.allkeys)[`ASICTimingConstraintSchema.copy()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICTimingConstraintSchema.copy)[`ASICTimingConstraintSchema.copy_mode()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICTimingConstraintSchema.copy_mode)[`ASICTimingConstraintSchema.copy_scenario()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICTimingConstraintSchema.copy_scenario)[`ASICTimingConstraintSchema.from_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICTimingConstraintSchema.from_manifest)[`ASICTimingConstraintSchema.get()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICTimingConstraintSchema.get)[`ASICTimingConstraintSchema.get_mode()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICTimingConstraintSchema.get_mode)[`ASICTimingConstraintSchema.get_scenario()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICTimingConstraintSchema.get_scenario)[`ASICTimingConstraintSchema.getdict()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICTimingConstraintSchema.getdict)[`ASICTimingConstraintSchema.getkeys()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICTimingConstraintSchema.getkeys)[`ASICTimingConstraintSchema.make_mode()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICTimingConstraintSchema.make_mode)[`ASICTimingConstraintSchema.make_scenario()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICTimingConstraintSchema.make_scenario)[`ASICTimingConstraintSchema.read_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICTimingConstraintSchema.read_manifest)[`ASICTimingConstraintSchema.remove()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICTimingConstraintSchema.remove)[`ASICTimingConstraintSchema.remove_mode()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICTimingConstraintSchema.remove_mode)[`ASICTimingConstraintSchema.remove_scenario()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICTimingConstraintSchema.remove_scenario)[`ASICTimingConstraintSchema.set()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICTimingConstraintSchema.set)[`ASICTimingConstraintSchema.unset()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICTimingConstraintSchema.unset)[`ASICTimingConstraintSchema.valid()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICTimingConstraintSchema.valid)[`ASICTimingConstraintSchema.write_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICTimingConstraintSchema.write_manifest)[`ASICTimingScenarioSchema`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICTimingScenarioSchema)[`ASICTimingScenarioSchema.add()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICTimingScenarioSchema.add)[`ASICTimingScenarioSchema.add_check()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICTimingScenarioSchema.add_check)[`ASICTimingScenarioSchema.add_libcorner()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICTimingScenarioSchema.add_libcorner)[`ASICTimingScenarioSchema.add_sdcfileset()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICTimingScenarioSchema.add_sdcfileset)[`ASICTimingScenarioSchema.allkeys()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICTimingScenarioSchema.allkeys)[`ASICTimingScenarioSchema.copy()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICTimingScenarioSchema.copy)[`ASICTimingScenarioSchema.from_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICTimingScenarioSchema.from_manifest)[`ASICTimingScenarioSchema.get()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICTimingScenarioSchema.get)[`ASICTimingScenarioSchema.get_check()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICTimingScenarioSchema.get_check)[`ASICTimingScenarioSchema.get_libcorner()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICTimingScenarioSchema.get_libcorner)[`ASICTimingScenarioSchema.get_mode()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICTimingScenarioSchema.get_mode)[`ASICTimingScenarioSchema.get_opcond()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICTimingScenarioSchema.get_opcond)[`ASICTimingScenarioSchema.get_pexcorner()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICTimingScenarioSchema.get_pexcorner)[`ASICTimingScenarioSchema.get_pin_voltage()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICTimingScenarioSchema.get_pin_voltage)[`ASICTimingScenarioSchema.get_sdcfileset()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICTimingScenarioSchema.get_sdcfileset)[`ASICTimingScenarioSchema.get_temperature()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICTimingScenarioSchema.get_temperature)[`ASICTimingScenarioSchema.getdict()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICTimingScenarioSchema.getdict)[`ASICTimingScenarioSchema.getkeys()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICTimingScenarioSchema.getkeys)[`ASICTimingScenarioSchema.name`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICTimingScenarioSchema.name)[`ASICTimingScenarioSchema.read_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICTimingScenarioSchema.read_manifest)[`ASICTimingScenarioSchema.remove()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICTimingScenarioSchema.remove)[`ASICTimingScenarioSchema.remove_pin_voltage()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICTimingScenarioSchema.remove_pin_voltage)[`ASICTimingScenarioSchema.set()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICTimingScenarioSchema.set)[`ASICTimingScenarioSchema.set_mode()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICTimingScenarioSchema.set_mode)[`ASICTimingScenarioSchema.set_name()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICTimingScenarioSchema.set_name)[`ASICTimingScenarioSchema.set_opcond()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICTimingScenarioSchema.set_opcond)[`ASICTimingScenarioSchema.set_pexcorner()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICTimingScenarioSchema.set_pexcorner)[`ASICTimingScenarioSchema.set_pin_voltage()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICTimingScenarioSchema.set_pin_voltage)[`ASICTimingScenarioSchema.set_temperature()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICTimingScenarioSchema.set_temperature)[`ASICTimingScenarioSchema.type()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICTimingScenarioSchema.type)[`ASICTimingScenarioSchema.unset()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICTimingScenarioSchema.unset)[`ASICTimingScenarioSchema.valid()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICTimingScenarioSchema.valid)[`ASICTimingScenarioSchema.write_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICTimingScenarioSchema.write_manifest)[`ASICAreaConstraint`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICAreaConstraint)[`ASICAreaConstraint.add()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICAreaConstraint.add)[`ASICAreaConstraint.allkeys()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICAreaConstraint.allkeys)[`ASICAreaConstraint.calc_diearea()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICAreaConstraint.calc_diearea)[`ASICAreaConstraint.calc_floorplan_areas()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICAreaConstraint.calc_floorplan_areas)[`ASICAreaConstraint.copy()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICAreaConstraint.copy)[`ASICAreaConstraint.from_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICAreaConstraint.from_manifest)[`ASICAreaConstraint.get()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICAreaConstraint.get)[`ASICAreaConstraint.get_aspectratio()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICAreaConstraint.get_aspectratio)[`ASICAreaConstraint.get_corearea()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICAreaConstraint.get_corearea)[`ASICAreaConstraint.get_coreboundingbox()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICAreaConstraint.get_coreboundingbox)[`ASICAreaConstraint.get_coremargin()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICAreaConstraint.get_coremargin)[`ASICAreaConstraint.get_coresize()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICAreaConstraint.get_coresize)[`ASICAreaConstraint.get_density()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICAreaConstraint.get_density)[`ASICAreaConstraint.get_diearea()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICAreaConstraint.get_diearea)[`ASICAreaConstraint.get_dieboundingbox()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICAreaConstraint.get_dieboundingbox)[`ASICAreaConstraint.get_diesize()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICAreaConstraint.get_diesize)[`ASICAreaConstraint.getdict()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICAreaConstraint.getdict)[`ASICAreaConstraint.getkeys()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICAreaConstraint.getkeys)[`ASICAreaConstraint.read_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICAreaConstraint.read_manifest)[`ASICAreaConstraint.remove()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICAreaConstraint.remove)[`ASICAreaConstraint.set()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICAreaConstraint.set)[`ASICAreaConstraint.set_aspectratio()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICAreaConstraint.set_aspectratio)[`ASICAreaConstraint.set_corearea()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICAreaConstraint.set_corearea)[`ASICAreaConstraint.set_corearea_rectangle()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICAreaConstraint.set_corearea_rectangle)[`ASICAreaConstraint.set_coremargin()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICAreaConstraint.set_coremargin)[`ASICAreaConstraint.set_coreoutline()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICAreaConstraint.set_coreoutline)[`ASICAreaConstraint.set_density()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICAreaConstraint.set_density)[`ASICAreaConstraint.set_diearea()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICAreaConstraint.set_diearea)[`ASICAreaConstraint.set_diearea_rectangle()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICAreaConstraint.set_diearea_rectangle)[`ASICAreaConstraint.set_dieoutline()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICAreaConstraint.set_dieoutline)[`ASICAreaConstraint.unset()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICAreaConstraint.unset)[`ASICAreaConstraint.valid()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICAreaConstraint.valid)[`ASICAreaConstraint.write_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICAreaConstraint.write_manifest)[`ASICPinConstraints`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICPinConstraints)[`ASICPinConstraints.add()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICPinConstraints.add)[`ASICPinConstraints.add_pinconstraint()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICPinConstraints.add_pinconstraint)[`ASICPinConstraints.allkeys()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICPinConstraints.allkeys)[`ASICPinConstraints.copy()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICPinConstraints.copy)[`ASICPinConstraints.copy_pinconstraint()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICPinConstraints.copy_pinconstraint)[`ASICPinConstraints.from_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICPinConstraints.from_manifest)[`ASICPinConstraints.get()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICPinConstraints.get)[`ASICPinConstraints.get_pinconstraint()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICPinConstraints.get_pinconstraint)[`ASICPinConstraints.getdict()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICPinConstraints.getdict)[`ASICPinConstraints.getkeys()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICPinConstraints.getkeys)[`ASICPinConstraints.make_buspinconstraints()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICPinConstraints.make_buspinconstraints)[`ASICPinConstraints.make_pinconstraint()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICPinConstraints.make_pinconstraint)[`ASICPinConstraints.read_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICPinConstraints.read_manifest)[`ASICPinConstraints.remove()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICPinConstraints.remove)[`ASICPinConstraints.remove_pinconstraint()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICPinConstraints.remove_pinconstraint)[`ASICPinConstraints.set()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICPinConstraints.set)[`ASICPinConstraints.unset()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICPinConstraints.unset)[`ASICPinConstraints.valid()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICPinConstraints.valid)[`ASICPinConstraints.write_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICPinConstraints.write_manifest)[`ASICPinConstraint`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICPinConstraint)[`ASICPinConstraint.add()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICPinConstraint.add)[`ASICPinConstraint.allkeys()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICPinConstraint.allkeys)[`ASICPinConstraint.copy()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICPinConstraint.copy)[`ASICPinConstraint.from_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICPinConstraint.from_manifest)[`ASICPinConstraint.get()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICPinConstraint.get)[`ASICPinConstraint.get_layer()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICPinConstraint.get_layer)[`ASICPinConstraint.get_length()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICPinConstraint.get_length)[`ASICPinConstraint.get_order()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICPinConstraint.get_order)[`ASICPinConstraint.get_placement()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICPinConstraint.get_placement)[`ASICPinConstraint.get_shape()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICPinConstraint.get_shape)[`ASICPinConstraint.get_side()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICPinConstraint.get_side)[`ASICPinConstraint.get_width()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICPinConstraint.get_width)[`ASICPinConstraint.getdict()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICPinConstraint.getdict)[`ASICPinConstraint.getkeys()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICPinConstraint.getkeys)[`ASICPinConstraint.name`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICPinConstraint.name)[`ASICPinConstraint.read_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICPinConstraint.read_manifest)[`ASICPinConstraint.remove()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICPinConstraint.remove)[`ASICPinConstraint.set()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICPinConstraint.set)[`ASICPinConstraint.set_layer()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICPinConstraint.set_layer)[`ASICPinConstraint.set_length()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICPinConstraint.set_length)[`ASICPinConstraint.set_name()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICPinConstraint.set_name)[`ASICPinConstraint.set_order()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICPinConstraint.set_order)[`ASICPinConstraint.set_placement()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICPinConstraint.set_placement)[`ASICPinConstraint.set_shape()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICPinConstraint.set_shape)[`ASICPinConstraint.set_side()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICPinConstraint.set_side)[`ASICPinConstraint.set_width()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICPinConstraint.set_width)[`ASICPinConstraint.type()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICPinConstraint.type)[`ASICPinConstraint.unset()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICPinConstraint.unset)[`ASICPinConstraint.valid()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICPinConstraint.valid)[`ASICPinConstraint.write_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICPinConstraint.write_manifest)[`ASICComponentConstraints`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICComponentConstraints)[`ASICComponentConstraints.add()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICComponentConstraints.add)[`ASICComponentConstraints.add_component()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICComponentConstraints.add_component)[`ASICComponentConstraints.allkeys()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICComponentConstraints.allkeys)[`ASICComponentConstraints.copy()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICComponentConstraints.copy)[`ASICComponentConstraints.copy_component()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICComponentConstraints.copy_component)[`ASICComponentConstraints.from_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICComponentConstraints.from_manifest)[`ASICComponentConstraints.get()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICComponentConstraints.get)[`ASICComponentConstraints.get_component()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICComponentConstraints.get_component)[`ASICComponentConstraints.getdict()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICComponentConstraints.getdict)[`ASICComponentConstraints.getkeys()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICComponentConstraints.getkeys)[`ASICComponentConstraints.make_component()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICComponentConstraints.make_component)[`ASICComponentConstraints.read_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICComponentConstraints.read_manifest)[`ASICComponentConstraints.remove()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICComponentConstraints.remove)[`ASICComponentConstraints.remove_component()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICComponentConstraints.remove_component)[`ASICComponentConstraints.set()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICComponentConstraints.set)[`ASICComponentConstraints.unset()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICComponentConstraints.unset)[`ASICComponentConstraints.valid()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICComponentConstraints.valid)[`ASICComponentConstraints.write_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICComponentConstraints.write_manifest)[`ASICComponentConstraint`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICComponentConstraint)[`ASICComponentConstraint.add()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICComponentConstraint.add)[`ASICComponentConstraint.allkeys()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICComponentConstraint.allkeys)[`ASICComponentConstraint.copy()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICComponentConstraint.copy)[`ASICComponentConstraint.from_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICComponentConstraint.from_manifest)[`ASICComponentConstraint.get()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICComponentConstraint.get)[`ASICComponentConstraint.get_halo()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICComponentConstraint.get_halo)[`ASICComponentConstraint.get_partname()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICComponentConstraint.get_partname)[`ASICComponentConstraint.get_placement()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICComponentConstraint.get_placement)[`ASICComponentConstraint.get_rotation()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICComponentConstraint.get_rotation)[`ASICComponentConstraint.getdict()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICComponentConstraint.getdict)[`ASICComponentConstraint.getkeys()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICComponentConstraint.getkeys)[`ASICComponentConstraint.name`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICComponentConstraint.name)[`ASICComponentConstraint.read_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICComponentConstraint.read_manifest)[`ASICComponentConstraint.remove()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICComponentConstraint.remove)[`ASICComponentConstraint.set()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICComponentConstraint.set)[`ASICComponentConstraint.set_halo()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICComponentConstraint.set_halo)[`ASICComponentConstraint.set_name()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICComponentConstraint.set_name)[`ASICComponentConstraint.set_partname()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICComponentConstraint.set_partname)[`ASICComponentConstraint.set_placement()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICComponentConstraint.set_placement)[`ASICComponentConstraint.set_rotation()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICComponentConstraint.set_rotation)[`ASICComponentConstraint.type()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICComponentConstraint.type)[`ASICComponentConstraint.unset()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICComponentConstraint.unset)[`ASICComponentConstraint.valid()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICComponentConstraint.valid)[`ASICComponentConstraint.write_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.ASICComponentConstraint.write_manifest)[FPGA Constraint Classes](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#fpga-constraint-classes)[`FPGAConstraint`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.fpga.FPGAConstraint)[`FPGAConstraint.add()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.fpga.FPGAConstraint.add)[`FPGAConstraint.allkeys()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.fpga.FPGAConstraint.allkeys)[`FPGAConstraint.component`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.fpga.FPGAConstraint.component)[`FPGAConstraint.copy()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.fpga.FPGAConstraint.copy)[`FPGAConstraint.from_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.fpga.FPGAConstraint.from_manifest)[`FPGAConstraint.get()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.fpga.FPGAConstraint.get)[`FPGAConstraint.getdict()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.fpga.FPGAConstraint.getdict)[`FPGAConstraint.getkeys()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.fpga.FPGAConstraint.getkeys)[`FPGAConstraint.pin`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.fpga.FPGAConstraint.pin)[`FPGAConstraint.read_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.fpga.FPGAConstraint.read_manifest)[`FPGAConstraint.remove()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.fpga.FPGAConstraint.remove)[`FPGAConstraint.set()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.fpga.FPGAConstraint.set)[`FPGAConstraint.timing`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.fpga.FPGAConstraint.timing)[`FPGAConstraint.unset()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.fpga.FPGAConstraint.unset)[`FPGAConstraint.valid()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.fpga.FPGAConstraint.valid)[`FPGAConstraint.write_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.fpga.FPGAConstraint.write_manifest)[`FPGATimingConstraintSchema`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.FPGATimingConstraintSchema)[`FPGATimingConstraintSchema.add()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.FPGATimingConstraintSchema.add)[`FPGATimingConstraintSchema.add_mode()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.FPGATimingConstraintSchema.add_mode)[`FPGATimingConstraintSchema.add_scenario()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.FPGATimingConstraintSchema.add_scenario)[`FPGATimingConstraintSchema.allkeys()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.FPGATimingConstraintSchema.allkeys)[`FPGATimingConstraintSchema.copy()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.FPGATimingConstraintSchema.copy)[`FPGATimingConstraintSchema.copy_mode()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.FPGATimingConstraintSchema.copy_mode)[`FPGATimingConstraintSchema.copy_scenario()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.FPGATimingConstraintSchema.copy_scenario)[`FPGATimingConstraintSchema.from_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.FPGATimingConstraintSchema.from_manifest)[`FPGATimingConstraintSchema.get()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.FPGATimingConstraintSchema.get)[`FPGATimingConstraintSchema.get_mode()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.FPGATimingConstraintSchema.get_mode)[`FPGATimingConstraintSchema.get_scenario()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.FPGATimingConstraintSchema.get_scenario)[`FPGATimingConstraintSchema.getdict()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.FPGATimingConstraintSchema.getdict)[`FPGATimingConstraintSchema.getkeys()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.FPGATimingConstraintSchema.getkeys)[`FPGATimingConstraintSchema.make_mode()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.FPGATimingConstraintSchema.make_mode)[`FPGATimingConstraintSchema.make_scenario()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.FPGATimingConstraintSchema.make_scenario)[`FPGATimingConstraintSchema.read_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.FPGATimingConstraintSchema.read_manifest)[`FPGATimingConstraintSchema.remove()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.FPGATimingConstraintSchema.remove)[`FPGATimingConstraintSchema.remove_mode()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.FPGATimingConstraintSchema.remove_mode)[`FPGATimingConstraintSchema.remove_scenario()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.FPGATimingConstraintSchema.remove_scenario)[`FPGATimingConstraintSchema.set()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.FPGATimingConstraintSchema.set)[`FPGATimingConstraintSchema.unset()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.FPGATimingConstraintSchema.unset)[`FPGATimingConstraintSchema.valid()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.FPGATimingConstraintSchema.valid)[`FPGATimingConstraintSchema.write_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.FPGATimingConstraintSchema.write_manifest)[`FPGATimingScenarioSchema`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.FPGATimingScenarioSchema)[`FPGATimingScenarioSchema.add()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.FPGATimingScenarioSchema.add)[`FPGATimingScenarioSchema.allkeys()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.FPGATimingScenarioSchema.allkeys)[`FPGATimingScenarioSchema.copy()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.FPGATimingScenarioSchema.copy)[`FPGATimingScenarioSchema.from_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.FPGATimingScenarioSchema.from_manifest)[`FPGATimingScenarioSchema.get()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.FPGATimingScenarioSchema.get)[`FPGATimingScenarioSchema.get_mode()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.FPGATimingScenarioSchema.get_mode)[`FPGATimingScenarioSchema.getdict()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.FPGATimingScenarioSchema.getdict)[`FPGATimingScenarioSchema.getkeys()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.FPGATimingScenarioSchema.getkeys)[`FPGATimingScenarioSchema.name`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.FPGATimingScenarioSchema.name)[`FPGATimingScenarioSchema.read_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.FPGATimingScenarioSchema.read_manifest)[`FPGATimingScenarioSchema.remove()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.FPGATimingScenarioSchema.remove)[`FPGATimingScenarioSchema.set()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.FPGATimingScenarioSchema.set)[`FPGATimingScenarioSchema.set_mode()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.FPGATimingScenarioSchema.set_mode)[`FPGATimingScenarioSchema.set_name()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.FPGATimingScenarioSchema.set_name)[`FPGATimingScenarioSchema.type()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.FPGATimingScenarioSchema.type)[`FPGATimingScenarioSchema.unset()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.FPGATimingScenarioSchema.unset)[`FPGATimingScenarioSchema.valid()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.FPGATimingScenarioSchema.valid)[`FPGATimingScenarioSchema.write_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.FPGATimingScenarioSchema.write_manifest)[`FPGAComponentConstraints`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.FPGAComponentConstraints)[`FPGAComponentConstraints.add()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.FPGAComponentConstraints.add)[`FPGAComponentConstraints.allkeys()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.FPGAComponentConstraints.allkeys)[`FPGAComponentConstraints.copy()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.FPGAComponentConstraints.copy)[`FPGAComponentConstraints.from_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.FPGAComponentConstraints.from_manifest)[`FPGAComponentConstraints.get()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.FPGAComponentConstraints.get)[`FPGAComponentConstraints.getdict()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.FPGAComponentConstraints.getdict)[`FPGAComponentConstraints.getkeys()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.FPGAComponentConstraints.getkeys)[`FPGAComponentConstraints.read_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.FPGAComponentConstraints.read_manifest)[`FPGAComponentConstraints.remove()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.FPGAComponentConstraints.remove)[`FPGAComponentConstraints.set()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.FPGAComponentConstraints.set)[`FPGAComponentConstraints.unset()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.FPGAComponentConstraints.unset)[`FPGAComponentConstraints.valid()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.FPGAComponentConstraints.valid)[`FPGAComponentConstraints.write_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.FPGAComponentConstraints.write_manifest)[`FPGAPinConstraints`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.FPGAPinConstraints)[`FPGAPinConstraints.add()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.FPGAPinConstraints.add)[`FPGAPinConstraints.allkeys()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.FPGAPinConstraints.allkeys)[`FPGAPinConstraints.copy()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.FPGAPinConstraints.copy)[`FPGAPinConstraints.from_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.FPGAPinConstraints.from_manifest)[`FPGAPinConstraints.get()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.FPGAPinConstraints.get)[`FPGAPinConstraints.getdict()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.FPGAPinConstraints.getdict)[`FPGAPinConstraints.getkeys()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.FPGAPinConstraints.getkeys)[`FPGAPinConstraints.read_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.FPGAPinConstraints.read_manifest)[`FPGAPinConstraints.remove()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.FPGAPinConstraints.remove)[`FPGAPinConstraints.set()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.FPGAPinConstraints.set)[`FPGAPinConstraints.unset()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.FPGAPinConstraints.unset)[`FPGAPinConstraints.valid()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.FPGAPinConstraints.valid)[`FPGAPinConstraints.write_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.FPGAPinConstraints.write_manifest)[Core Schema Classes](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#core-schema-classes)[`BaseSchema`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.BaseSchema)[`BaseSchema._from_dict()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.BaseSchema._from_dict)[`BaseSchema._parent()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.BaseSchema._parent)[`BaseSchema.add()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.BaseSchema.add)[`BaseSchema.allkeys()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.BaseSchema.allkeys)[`BaseSchema.copy()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.BaseSchema.copy)[`BaseSchema.from_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.BaseSchema.from_manifest)[`BaseSchema.get()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.BaseSchema.get)[`BaseSchema.getdict()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.BaseSchema.getdict)[`BaseSchema.getkeys()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.BaseSchema.getkeys)[`BaseSchema.read_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.BaseSchema.read_manifest)[`BaseSchema.remove()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.BaseSchema.remove)[`BaseSchema.set()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.BaseSchema.set)[`BaseSchema.unset()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.BaseSchema.unset)[`BaseSchema.valid()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.BaseSchema.valid)[`BaseSchema.write_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.BaseSchema.write_manifest)[`EditableSchema`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.EditableSchema)[`EditableSchema.copy()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.EditableSchema.copy)[`EditableSchema.insert()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.EditableSchema.insert)[`EditableSchema.remove()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.EditableSchema.remove)[`EditableSchema.remove_parent()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.EditableSchema.remove_parent)[`EditableSchema.rename()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.EditableSchema.rename)[`EditableSchema.search()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.EditableSchema.search)[`SafeSchema`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.SafeSchema)[`SafeSchema.add()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.SafeSchema.add)[`SafeSchema.allkeys()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.SafeSchema.allkeys)[`SafeSchema.copy()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.SafeSchema.copy)[`SafeSchema.from_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.SafeSchema.from_manifest)[`SafeSchema.get()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.SafeSchema.get)[`SafeSchema.getdict()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.SafeSchema.getdict)[`SafeSchema.getkeys()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.SafeSchema.getkeys)[`SafeSchema.read_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.SafeSchema.read_manifest)[`SafeSchema.remove()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.SafeSchema.remove)[`SafeSchema.set()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.SafeSchema.set)[`SafeSchema.unset()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.SafeSchema.unset)[`SafeSchema.valid()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.SafeSchema.valid)[`SafeSchema.write_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.SafeSchema.write_manifest)[`Journal`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.Journal)[`Journal.access()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.Journal.access)[`Journal.add_type()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.Journal.add_type)[`Journal.from_dict()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.Journal.from_dict)[`Journal.get()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.Journal.get)[`Journal.get_child()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.Journal.get_child)[`Journal.get_types()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.Journal.get_types)[`Journal.has_journaling()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.Journal.has_journaling)[`Journal.is_journaling()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.Journal.is_journaling)[`Journal.keypath`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.Journal.keypath)[`Journal.record()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.Journal.record)[`Journal.remove_type()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.Journal.remove_type)[`Journal.replay()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.Journal.replay)[`Journal.replay_file()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.Journal.replay_file)[`Journal.start()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.Journal.start)[`Journal.stop()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.Journal.stop)[`NamedSchema`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.NamedSchema)[`NamedSchema.add()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.NamedSchema.add)[`NamedSchema.allkeys()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.NamedSchema.allkeys)[`NamedSchema.copy()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.NamedSchema.copy)[`NamedSchema.from_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.NamedSchema.from_manifest)[`NamedSchema.get()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.NamedSchema.get)[`NamedSchema.getdict()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.NamedSchema.getdict)[`NamedSchema.getkeys()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.NamedSchema.getkeys)[`NamedSchema.name`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.NamedSchema.name)[`NamedSchema.read_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.NamedSchema.read_manifest)[`NamedSchema.remove()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.NamedSchema.remove)[`NamedSchema.set()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.NamedSchema.set)[`NamedSchema.set_name()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.NamedSchema.set_name)[`NamedSchema.type()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.NamedSchema.type)[`NamedSchema.unset()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.NamedSchema.unset)[`NamedSchema.valid()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.NamedSchema.valid)[`NamedSchema.write_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.NamedSchema.write_manifest)[`Parameter`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.Parameter)[`Parameter.add()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.Parameter.add)[`Parameter.add_commandline_arguments()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.Parameter.add_commandline_arguments)[`Parameter.basetype()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.Parameter.basetype)[`Parameter.copy()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.Parameter.copy)[`Parameter.default`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.Parameter.default)[`Parameter.from_dict()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.Parameter.from_dict)[`Parameter.get()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.Parameter.get)[`Parameter.getdict()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.Parameter.getdict)[`Parameter.gettcl()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.Parameter.gettcl)[`Parameter.getvalues()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.Parameter.getvalues)[`Parameter.has_value()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.Parameter.has_value)[`Parameter.is_directory`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.Parameter.is_directory)[`Parameter.is_empty()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.Parameter.is_empty)[`Parameter.is_file`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.Parameter.is_file)[`Parameter.is_list()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.Parameter.is_list)[`Parameter.is_path`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.Parameter.is_path)[`Parameter.is_set()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.Parameter.is_set)[`Parameter.istype()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.Parameter.istype)[`Parameter.parse_commandline_arguments()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.Parameter.parse_commandline_arguments)[`Parameter.reset()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.Parameter.reset)[`Parameter.set()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.Parameter.set)[`Parameter.unset()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.Parameter.unset)[`NodeListValue`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametervalue.NodeListValue)[`NodeListValue.add()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametervalue.NodeListValue.add)[`NodeListValue.copy()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametervalue.NodeListValue.copy)[`NodeListValue.fields`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametervalue.NodeListValue.fields)[`NodeListValue.get()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametervalue.NodeListValue.get)[`NodeListValue.getdict()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametervalue.NodeListValue.getdict)[`NodeListValue.gettcl()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametervalue.NodeListValue.gettcl)[`NodeListValue.has_value`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametervalue.NodeListValue.has_value)[`NodeListValue.set()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametervalue.NodeListValue.set)[`NodeListValue.type`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametervalue.NodeListValue.type)[`NodeListValue.values`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametervalue.NodeListValue.values)[`NodeSetValue`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametervalue.NodeSetValue)[`NodeSetValue.add()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametervalue.NodeSetValue.add)[`NodeSetValue.copy()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametervalue.NodeSetValue.copy)[`NodeSetValue.fields`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametervalue.NodeSetValue.fields)[`NodeSetValue.get()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametervalue.NodeSetValue.get)[`NodeSetValue.getdict()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametervalue.NodeSetValue.getdict)[`NodeSetValue.gettcl()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametervalue.NodeSetValue.gettcl)[`NodeSetValue.has_value`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametervalue.NodeSetValue.has_value)[`NodeSetValue.type`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametervalue.NodeSetValue.type)[`NodeSetValue.values`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametervalue.NodeSetValue.values)[`NodeValue`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametervalue.NodeValue)[`NodeValue.add()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametervalue.NodeValue.add)[`NodeValue.copy()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametervalue.NodeValue.copy)[`NodeValue.fields`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametervalue.NodeValue.fields)[`NodeValue.from_dict()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametervalue.NodeValue.from_dict)[`NodeValue.get()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametervalue.NodeValue.get)[`NodeValue.getdict()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametervalue.NodeValue.getdict)[`NodeValue.gettcl()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametervalue.NodeValue.gettcl)[`NodeValue.has_value`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametervalue.NodeValue.has_value)[`NodeValue.set()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametervalue.NodeValue.set)[`NodeValue.sign()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametervalue.NodeValue.sign)[`NodeValue.type`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametervalue.NodeValue.type)[`NodeValue.verify_signature()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametervalue.NodeValue.verify_signature)[`PathNodeValue`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametervalue.PathNodeValue)[`PathNodeValue.add()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametervalue.PathNodeValue.add)[`PathNodeValue.copy()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametervalue.PathNodeValue.copy)[`PathNodeValue.fields`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametervalue.PathNodeValue.fields)[`PathNodeValue.from_dict()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametervalue.PathNodeValue.from_dict)[`PathNodeValue.generate_hashed_collection_path()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametervalue.PathNodeValue.generate_hashed_collection_path)[`PathNodeValue.get()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametervalue.PathNodeValue.get)[`PathNodeValue.getdict()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametervalue.PathNodeValue.getdict)[`PathNodeValue.gettcl()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametervalue.PathNodeValue.gettcl)[`PathNodeValue.has_value`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametervalue.PathNodeValue.has_value)[`PathNodeValue.hash()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametervalue.PathNodeValue.hash)[`PathNodeValue.hash_directory()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametervalue.PathNodeValue.hash_directory)[`PathNodeValue.hash_file()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametervalue.PathNodeValue.hash_file)[`PathNodeValue.resolve_path()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametervalue.PathNodeValue.resolve_path)[`PathNodeValue.set()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametervalue.PathNodeValue.set)[`PathNodeValue.sign()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametervalue.PathNodeValue.sign)[`PathNodeValue.type`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametervalue.PathNodeValue.type)[`PathNodeValue.verify_signature()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametervalue.PathNodeValue.verify_signature)[`DirectoryNodeValue`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametervalue.DirectoryNodeValue)[`DirectoryNodeValue.add()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametervalue.DirectoryNodeValue.add)[`DirectoryNodeValue.copy()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametervalue.DirectoryNodeValue.copy)[`DirectoryNodeValue.fields`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametervalue.DirectoryNodeValue.fields)[`DirectoryNodeValue.from_dict()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametervalue.DirectoryNodeValue.from_dict)[`DirectoryNodeValue.generate_hashed_collection_path()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametervalue.DirectoryNodeValue.generate_hashed_collection_path)[`DirectoryNodeValue.get()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametervalue.DirectoryNodeValue.get)[`DirectoryNodeValue.getdict()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametervalue.DirectoryNodeValue.getdict)[`DirectoryNodeValue.gettcl()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametervalue.DirectoryNodeValue.gettcl)[`DirectoryNodeValue.has_value`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametervalue.DirectoryNodeValue.has_value)[`DirectoryNodeValue.hash()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametervalue.DirectoryNodeValue.hash)[`DirectoryNodeValue.hash_directory()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametervalue.DirectoryNodeValue.hash_directory)[`DirectoryNodeValue.hash_file()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametervalue.DirectoryNodeValue.hash_file)[`DirectoryNodeValue.resolve_path()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametervalue.DirectoryNodeValue.resolve_path)[`DirectoryNodeValue.set()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametervalue.DirectoryNodeValue.set)[`DirectoryNodeValue.sign()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametervalue.DirectoryNodeValue.sign)[`DirectoryNodeValue.type`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametervalue.DirectoryNodeValue.type)[`DirectoryNodeValue.verify_signature()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametervalue.DirectoryNodeValue.verify_signature)[`FileNodeValue`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametervalue.FileNodeValue)[`FileNodeValue.add()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametervalue.FileNodeValue.add)[`FileNodeValue.copy()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametervalue.FileNodeValue.copy)[`FileNodeValue.fields`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametervalue.FileNodeValue.fields)[`FileNodeValue.from_dict()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametervalue.FileNodeValue.from_dict)[`FileNodeValue.generate_hashed_collection_path()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametervalue.FileNodeValue.generate_hashed_collection_path)[`FileNodeValue.get()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametervalue.FileNodeValue.get)[`FileNodeValue.getdict()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametervalue.FileNodeValue.getdict)[`FileNodeValue.gettcl()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametervalue.FileNodeValue.gettcl)[`FileNodeValue.has_value`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametervalue.FileNodeValue.has_value)[`FileNodeValue.hash()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametervalue.FileNodeValue.hash)[`FileNodeValue.hash_directory()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametervalue.FileNodeValue.hash_directory)[`FileNodeValue.hash_file()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametervalue.FileNodeValue.hash_file)[`FileNodeValue.resolve_path()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametervalue.FileNodeValue.resolve_path)[`FileNodeValue.set()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametervalue.FileNodeValue.set)[`FileNodeValue.sign()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametervalue.FileNodeValue.sign)[`FileNodeValue.type`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametervalue.FileNodeValue.type)[`FileNodeValue.verify_signature()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametervalue.FileNodeValue.verify_signature)[`NodeType`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametertype.NodeType)[`NodeType.astype()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametertype.NodeType.astype)[`NodeType.basetype()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametertype.NodeType.basetype)[`NodeType.check_path_containers()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametertype.NodeType.check_path_containers)[`NodeType.contains()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametertype.NodeType.contains)[`NodeType.encode()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametertype.NodeType.encode)[`NodeType.istype()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametertype.NodeType.istype)[`NodeType.normalize()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametertype.NodeType.normalize)[`NodeType.parse()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametertype.NodeType.parse)[`NodeType.to_tcl()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametertype.NodeType.to_tcl)[`NodeEnumType`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametertype.NodeEnumType)[`NodeEnumType.values`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametertype.NodeEnumType.values)[`NodeRangeType`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametertype.NodeRangeType)[`NodeRangeType.base`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametertype.NodeRangeType.base)[`NodeRangeType.values`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parametertype.NodeRangeType.values)[`LazyLoad`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.baseschema.LazyLoad)[`LazyLoad.FORWARD`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.baseschema.LazyLoad.FORWARD)[`LazyLoad.OFF`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.baseschema.LazyLoad.OFF)[`LazyLoad.ON`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.baseschema.LazyLoad.ON)[`LazyLoad.is_enforced`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.baseschema.LazyLoad.is_enforced)[`LazyLoad.next`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.baseschema.LazyLoad.next)[`Scope`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parameter.Scope)[`Scope.GLOBAL`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parameter.Scope.GLOBAL)[`Scope.JOB`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parameter.Scope.JOB)[`Scope.SCRATCH`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parameter.Scope.SCRATCH)[`PerNode`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parameter.PerNode)[`PerNode.NEVER`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parameter.PerNode.NEVER)[`PerNode.OPTIONAL`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parameter.PerNode.OPTIONAL)[`PerNode.REQUIRED`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parameter.PerNode.REQUIRED)[`PerNode.is_never()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.parameter.PerNode.is_never)[`DocsSchema`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.DocsSchema)[`DocsSchema.make_docs()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema.DocsSchema.make_docs)[Supporting Classes](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#supporting-classes)[`DependencySchema`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.dependencyschema.DependencySchema)[`DependencySchema.add()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.dependencyschema.DependencySchema.add)[`DependencySchema.add_dep()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.dependencyschema.DependencySchema.add_dep)[`DependencySchema.allkeys()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.dependencyschema.DependencySchema.allkeys)[`DependencySchema.check_filepaths()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.dependencyschema.DependencySchema.check_filepaths)[`DependencySchema.copy()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.dependencyschema.DependencySchema.copy)[`DependencySchema.from_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.dependencyschema.DependencySchema.from_manifest)[`DependencySchema.get()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.dependencyschema.DependencySchema.get)[`DependencySchema.get_dep()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.dependencyschema.DependencySchema.get_dep)[`DependencySchema.getdict()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.dependencyschema.DependencySchema.getdict)[`DependencySchema.getkeys()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.dependencyschema.DependencySchema.getkeys)[`DependencySchema.has_dep()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.dependencyschema.DependencySchema.has_dep)[`DependencySchema.read_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.dependencyschema.DependencySchema.read_manifest)[`DependencySchema.remove()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.dependencyschema.DependencySchema.remove)[`DependencySchema.remove_dep()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.dependencyschema.DependencySchema.remove_dep)[`DependencySchema.set()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.dependencyschema.DependencySchema.set)[`DependencySchema.unset()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.dependencyschema.DependencySchema.unset)[`DependencySchema.valid()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.dependencyschema.DependencySchema.valid)[`DependencySchema.write_depgraph()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.dependencyschema.DependencySchema.write_depgraph)[`DependencySchema.write_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.dependencyschema.DependencySchema.write_manifest)[`OptionSchema`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.option.OptionSchema)[`OptionSchema.add_alias()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.option.OptionSchema.add_alias)[`OptionSchema.add_fileset()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.option.OptionSchema.add_fileset)[`OptionSchema.add_from()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.option.OptionSchema.add_from)[`OptionSchema.add_prune()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.option.OptionSchema.add_prune)[`OptionSchema.add_to()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.option.OptionSchema.add_to)[`OptionSchema.get_alias()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.option.OptionSchema.get_alias)[`OptionSchema.get_autoissue()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.option.OptionSchema.get_autoissue)[`OptionSchema.get_breakpoint()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.option.OptionSchema.get_breakpoint)[`OptionSchema.get_builddir()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.option.OptionSchema.get_builddir)[`OptionSchema.get_cachedir()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.option.OptionSchema.get_cachedir)[`OptionSchema.get_clean()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.option.OptionSchema.get_clean)[`OptionSchema.get_continue()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.option.OptionSchema.get_continue)[`OptionSchema.get_credentials()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.option.OptionSchema.get_credentials)[`OptionSchema.get_design()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.option.OptionSchema.get_design)[`OptionSchema.get_env()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.option.OptionSchema.get_env)[`OptionSchema.get_fileset()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.option.OptionSchema.get_fileset)[`OptionSchema.get_flow()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.option.OptionSchema.get_flow)[`OptionSchema.get_from()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.option.OptionSchema.get_from)[`OptionSchema.get_hash()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.option.OptionSchema.get_hash)[`OptionSchema.get_jobincr()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.option.OptionSchema.get_jobincr)[`OptionSchema.get_jobname()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.option.OptionSchema.get_jobname)[`OptionSchema.get_nice()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.option.OptionSchema.get_nice)[`OptionSchema.get_nodashboard()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.option.OptionSchema.get_nodashboard)[`OptionSchema.get_nodisplay()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.option.OptionSchema.get_nodisplay)[`OptionSchema.get_novercheck()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.option.OptionSchema.get_novercheck)[`OptionSchema.get_optmode()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.option.OptionSchema.get_optmode)[`OptionSchema.get_prune()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.option.OptionSchema.get_prune)[`OptionSchema.get_quiet()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.option.OptionSchema.get_quiet)[`OptionSchema.get_remote()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.option.OptionSchema.get_remote)[`OptionSchema.get_timeout()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.option.OptionSchema.get_timeout)[`OptionSchema.get_to()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.option.OptionSchema.get_to)[`OptionSchema.get_track()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.option.OptionSchema.get_track)[`OptionSchema.scheduler`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.option.OptionSchema.scheduler)[`OptionSchema.set()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.option.OptionSchema.set)[`OptionSchema.set_autoissue()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.option.OptionSchema.set_autoissue)[`OptionSchema.set_breakpoint()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.option.OptionSchema.set_breakpoint)[`OptionSchema.set_builddir()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.option.OptionSchema.set_builddir)[`OptionSchema.set_cachedir()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.option.OptionSchema.set_cachedir)[`OptionSchema.set_clean()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.option.OptionSchema.set_clean)[`OptionSchema.set_continue()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.option.OptionSchema.set_continue)[`OptionSchema.set_credentials()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.option.OptionSchema.set_credentials)[`OptionSchema.set_design()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.option.OptionSchema.set_design)[`OptionSchema.set_env()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.option.OptionSchema.set_env)[`OptionSchema.set_flow()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.option.OptionSchema.set_flow)[`OptionSchema.set_hash()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.option.OptionSchema.set_hash)[`OptionSchema.set_jobincr()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.option.OptionSchema.set_jobincr)[`OptionSchema.set_jobname()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.option.OptionSchema.set_jobname)[`OptionSchema.set_nice()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.option.OptionSchema.set_nice)[`OptionSchema.set_nodashboard()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.option.OptionSchema.set_nodashboard)[`OptionSchema.set_nodisplay()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.option.OptionSchema.set_nodisplay)[`OptionSchema.set_novercheck()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.option.OptionSchema.set_novercheck)[`OptionSchema.set_optmode()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.option.OptionSchema.set_optmode)[`OptionSchema.set_quiet()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.option.OptionSchema.set_quiet)[`OptionSchema.set_remote()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.option.OptionSchema.set_remote)[`OptionSchema.set_timeout()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.option.OptionSchema.set_timeout)[`OptionSchema.set_track()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.option.OptionSchema.set_track)[`OptionSchema.write_defaults()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.option.OptionSchema.write_defaults)[`SchedulerSchema`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.option.SchedulerSchema)[`SchedulerSchema.add_msgcontact()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.option.SchedulerSchema.add_msgcontact)[`SchedulerSchema.add_msgevent()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.option.SchedulerSchema.add_msgevent)[`SchedulerSchema.add_options()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.option.SchedulerSchema.add_options)[`SchedulerSchema.get_cores()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.option.SchedulerSchema.get_cores)[`SchedulerSchema.get_defer()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.option.SchedulerSchema.get_defer)[`SchedulerSchema.get_maxnodes()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.option.SchedulerSchema.get_maxnodes)[`SchedulerSchema.get_maxthreads()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.option.SchedulerSchema.get_maxthreads)[`SchedulerSchema.get_memory()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcomp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piler.schema_support.filesetschema.FileSetSchema.add_libdir)[`FileSetSchema.add_undefine()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.filesetschema.FileSetSchema.add_undefine)[`FileSetSchema.allkeys()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.filesetschema.FileSetSchema.allkeys)[`FileSetSchema.check_filepaths()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.filesetschema.FileSetSchema.check_filepaths)[`FileSetSchema.copy()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.filesetschema.FileSetSchema.copy)[`FileSetSchema.find_files()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.filesetschema.FileSetSchema.find_files)[`FileSetSchema.from_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.filesetschema.FileSetSchema.from_manifest)[`FileSetSchema.get()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.filesetschema.FileSetSchema.get)[`FileSetSchema.get_define()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.filesetschema.FileSetSchema.get_define)[`FileSetSchema.get_depfileset()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.filesetschema.FileSetSchema.get_depfileset)[`FileSetSchema.get_file()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.filesetschema.FileSetSchema.get_file)[`FileSetSchema.get_idir()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.filesetschema.FileSetSchema.get_idir)[`FileSetSchema.get_lib()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.filesetschema.FileSetSchema.get_lib)[`FileSetSchema.get_libdir()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.filesetschema.FileSetSchema.get_libdir)[`FileSetSchema.get_param()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.filesetschema.FileSetSchema.get_param)[`FileSetSchema.get_topmodule()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.filesetschema.FileSetSchema.get_topmodule)[`FileSetSchema.get_undefine()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.filesetschema.FileSetSchema.get_undefine)[`FileSetSchema.getdict()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.filesetschema.FileSetSchema.getdict)[`FileSetSchema.getkeys()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.filesetschema.FileSetSchema.getkeys)[`FileSetSchema.has_file()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.filesetschema.FileSetSchema.has_file)[`FileSetSchema.has_idir()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.filesetschema.FileSetSchema.has_idir)[`FileSetSchema.has_libdir()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.filesetschema.FileSetSchema.has_libdir)[`FileSetSchema.hash_files()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.filesetschema.FileSetSchema.hash_files)[`FileSetSchema.name`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.filesetschema.FileSetSchema.name)[`FileSetSchema.read_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.filesetschema.FileSetSchema.read_manifest)[`FileSetSchema.remove()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.filesetschema.FileSetSchema.remove)[`FileSetSchema.set()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.filesetschema.FileSetSchema.set)[`FileSetSchema.set_name()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.filesetschema.FileSetSchema.set_name)[`FileSetSchema.set_param()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.filesetschema.FileSetSchema.set_param)[`FileSetSchema.set_topmodule()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.filesetschema.FileSetSchema.set_topmodule)[`FileSetSchema.type()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.filesetschema.FileSetSchema.type)[`FileSetSchema.unset()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.filesetschema.FileSetSchema.unset)[`FileSetSchema.valid()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.filesetschema.FileSetSchema.valid)[`FileSetSchema.write_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.filesetschema.FileSetSchema.write_manifest)[`FlowgraphNodeSchema`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.flowgraph.FlowgraphNodeSchema)[`FlowgraphNodeSchema.add_args()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.flowgraph.FlowgraphNodeSchema.add_args)[`FlowgraphNodeSchema.add_goal()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.flowgraph.FlowgraphNodeSchema.add_goal)[`FlowgraphNodeSchema.add_weight()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.flowgraph.FlowgraphNodeSchema.add_weight)[`FlowgraphNodeSchema.get_args()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.flowgraph.FlowgraphNodeSchema.get_args)[`FlowgraphNodeSchema.get_goal()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.flowgraph.FlowgraphNodeSchema.get_goal)[`FlowgraphNodeSchema.get_input()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.flowgraph.FlowgraphNodeSchema.get_input)[`FlowgraphNodeSchema.get_task()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.flowgraph.FlowgraphNodeSchema.get_task)[`FlowgraphNodeSchema.get_taskmodule()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.flowgraph.FlowgraphNodeSchema.get_taskmodule)[`FlowgraphNodeSchema.get_tool()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.flowgraph.FlowgraphNodeSchema.get_tool)[`FlowgraphNodeSchema.get_weight()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.flowgraph.FlowgraphNodeSchema.get_weight)[`FlowgraphNodeSchema.has_input()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.flowgraph.FlowgraphNodeSchema.has_input)[`RuntimeFlowgraph`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.flowgraph.RuntimeFlowgraph)[`RuntimeFlowgraph.from_project()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.flowgraph.RuntimeFlowgraph.from_project)[`RuntimeFlowgraph.get_completed_nodes()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.flowgraph.RuntimeFlowgraph.get_completed_nodes)[`RuntimeFlowgraph.get_entry_nodes()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.flowgraph.RuntimeFlowgraph.get_entry_nodes)[`RuntimeFlowgraph.get_execution_order()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.flowgraph.RuntimeFlowgraph.get_execution_order)[`RuntimeFlowgraph.get_exit_nodes()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.flowgraph.RuntimeFlowgraph.get_exit_nodes)[`RuntimeFlowgraph.get_node_inputs()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.flowgraph.RuntimeFlowgraph.get_node_inputs)[`RuntimeFlowgraph.get_nodes()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.flowgraph.RuntimeFlowgraph.get_nodes)[`RuntimeFlowgraph.get_nodes_starting_at()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.flowgraph.RuntimeFlowgraph.get_nodes_starting_at)[`RuntimeFlowgraph.validate()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.flowgraph.RuntimeFlowgraph.validate)[`TaskError`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.tool.TaskError)[`TaskError.add_note()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.tool.TaskError.add_note)[`TaskError.with_traceback()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.tool.TaskError.with_traceback)[`TaskTimeout`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.tool.TaskTimeout)[`TaskTimeout.add_note()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.tool.TaskTimeout.add_note)[`TaskTimeout.with_traceback()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.tool.TaskTimeout.with_traceback)[`TaskExecutableNotFound`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.tool.TaskExecutableNotFound)[`TaskExecutableNotFound.add_note()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.tool.TaskExecutableNotFound.add_note)[`TaskExecutableNotFound.with_traceback()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.tool.TaskExecutableNotFound.with_traceback)[`PackageSchema`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.packageschema.PackageSchema)[`PackageSchema.add_author()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.packageschema.PackageSchema.add_author)[`PackageSchema.add_doc()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.packageschema.PackageSchema.add_doc)[`PackageSchema.add_license()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.packageschema.PackageSchema.add_license)[`PackageSchema.add_licensefile()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.packageschema.PackageSchema.add_licensefile)[`PackageSchema.get_author()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.packageschema.PackageSchema.get_author)[`PackageSchema.get_description()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.packageschema.PackageSchema.get_description)[`PackageSchema.get_doc()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.packageschema.PackageSchema.get_doc)[`PackageSchema.get_license()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.packageschema.PackageSchema.get_license)[`PackageSchema.get_licensefile()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.packageschema.PackageSchema.get_licensefile)[`PackageSchema.get_vendor()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.packageschema.PackageSchema.get_vendor)[`PackageSchema.get_version()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.packageschema.PackageSchema.get_version)[`PackageSchema.set_description()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.packageschema.PackageSchema.set_description)[`PackageSchema.set_vendor()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.packageschema.PackageSchema.set_vendor)[`PackageSchema.set_version()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.packageschema.PackageSchema.set_version)[`Criteria`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.checklist.Criteria)[`Criteria.add_criteria()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.checklist.Criteria.add_criteria)[`Criteria.add_rationale()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.checklist.Criteria.add_rationale)[`Criteria.add_report()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.checklist.Criteria.add_report)[`Criteria.add_task()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.checklist.Criteria.add_task)[`Criteria.add_waiver()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.checklist.Criteria.add_waiver)[`Criteria.get_criteria()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.checklist.Criteria.get_criteria)[`Criteria.get_dataformat()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.checklist.Criteria.get_dataformat)[`Criteria.get_description()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.checklist.Criteria.get_description)[`Criteria.get_ok()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.checklist.Criteria.get_ok)[`Criteria.get_rationale()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.checklist.Criteria.get_rationale)[`Criteria.get_report()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.checklist.Criteria.get_report)[`Criteria.get_requirement()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.checklist.Criteria.get_requirement)[`Criteria.get_task()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.checklist.Criteria.get_task)[`Criteria.get_waiver()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.checklist.Criteria.get_waiver)[`Criteria.set_dataformat()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.checklist.Criteria.set_dataformat)[`Criteria.set_description()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.checklist.Criteria.set_description)[`Criteria.set_ok()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.checklist.Criteria.set_ok)[`Criteria.set_requirement()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.checklist.Criteria.set_requirement)[`ToolLibrarySchema`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.library.ToolLibrarySchema)[`ToolLibrarySchema.define_tool_parameter()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.library.ToolLibrarySchema.define_tool_parameter)[`RecordSchema`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.record.RecordSchema)[`RecordSchema.clear()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.record.RecordSchema.clear)[`RecordSchema.get_cloud_information()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.record.RecordSchema.get_cloud_information)[`RecordSchema.get_earliest_time()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.record.RecordSchema.get_earliest_time)[`RecordSchema.get_ip_information()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.record.RecordSchema.get_ip_information)[`RecordSchema.get_latest_time()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.record.RecordSchema.get_latest_time)[`RecordSchema.get_machine_information()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.record.RecordSchema.get_machine_information)[`RecordSchema.get_recorded_time()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.record.RecordSchema.get_recorded_time)[`RecordSchema.get_user_information()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.record.RecordSchema.get_user_information)[`RecordSchema.record_python_packages()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.record.RecordSchema.record_python_packages)[`RecordSchema.record_time()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.record.RecordSchema.record_time)[`RecordSchema.record_tool()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.record.RecordSchema.record_tool)[`RecordSchema.record_userinformation()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.record.RecordSchema.record_userinformation)[`RecordSchema.record_version()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.record.RecordSchema.record_version)[`RecordTime`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.record.RecordTime)[`RecordTime.END`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.record.RecordTime.END)[`RecordTime.START`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.record.RecordTime.START)[`RecordTool`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.record.RecordTool)[`RecordTool.ARGS`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.record.RecordTool.ARGS)[`RecordTool.EXITCODE`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.record.RecordTool.EXITCODE)[`RecordTool.PATH`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.record.RecordTool.PATH)[`RecordTool.VERSION`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.record.RecordTool.VERSION)[`MetricSchema`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.metric.MetricSchema)[`MetricSchema.clear()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.metric.MetricSchema.clear)[`MetricSchema.get_formatted_metric()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.metric.MetricSchema.get_formatted_metric)[`MetricSchema.record()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.metric.MetricSchema.record)[`MetricSchema.record_tasktime()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.metric.MetricSchema.record_tasktime)[`MetricSchema.record_totaltime()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.metric.MetricSchema.record_totaltime)[`MetricSchema.summary()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.metric.MetricSchema.summary)[`MetricSchema.summary_table()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.schema_support.metric.MetricSchema.summary_table)[`ASICMetricsSchema`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.metrics.asic.ASICMetricsSchema)[`FPGAMetricsSchema`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.metrics.fpga.FPGAMetricsSchema)[`TimingModeSchema`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.timing_mode.TimingModeSchema)[`TimingModeSchema.add_sdcfileset()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.timing_mode.TimingModeSchema.add_sdcfileset)[`TimingModeSchema.get_sdcfileset()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.constraints.timing_mode.TimingModeSchema.get_sdcfileset)[Execution and settings](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#execution-and-settings)[`SchedulerNode`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.scheduler.schedulernode.SchedulerNode)[`SchedulerNode.archive()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.scheduler.schedulernode.SchedulerNode.archive)[`SchedulerNode.cancel()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.scheduler.schedulernode.SchedulerNode.cancel)[`SchedulerNode.check_files_changed()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.scheduler.schedulernode.SchedulerNode.check_files_changed)[`SchedulerNode.check_logfile()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.scheduler.schedulernode.SchedulerNode.check_logfile)[`SchedulerNode.check_previous_run_status()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.scheduler.schedulernode.SchedulerNode.check_previous_run_status)[`SchedulerNode.check_values_changed()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.scheduler.schedulernode.SchedulerNode.check_values_changed)[`SchedulerNode.check_version()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.scheduler.schedulernode.SchedulerNode.check_version)[`SchedulerNode.clean_directory()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.scheduler.schedulernode.SchedulerNode.clean_directory)[`SchedulerNode.collect_keys()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.scheduler.schedulernode.SchedulerNode.collect_keys)[`SchedulerNode.collection_dir`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.scheduler.schedulernode.SchedulerNode.collection_dir)[`SchedulerNode.copy_from()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.scheduler.schedulernode.SchedulerNode.copy_from)[`SchedulerNode.execute()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.scheduler.schedulernode.SchedulerNode.execute)[`SchedulerNode.get_check_changed_keys()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.scheduler.schedulernode.SchedulerNode.get_check_changed_keys)[`SchedulerNode.get_exe_path()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.scheduler.schedulernode.SchedulerNode.get_exe_path)[`SchedulerNode.get_log()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.scheduler.schedulernode.SchedulerNode.get_log)[`SchedulerNode.get_manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.scheduler.schedulernode.SchedulerNode.get_manifest)[`SchedulerNode.get_required_keys()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.scheduler.schedulernode.SchedulerNode.get_required_keys)[`SchedulerNode.get_required_path_keys()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.scheduler.schedulernode.SchedulerNode.get_required_path_keys)[`SchedulerNode.halt()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.scheduler.schedulernode.SchedulerNode.halt)[`SchedulerNode.has_error`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.scheduler.schedulernode.SchedulerNode.has_error)[`SchedulerNode.index`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.scheduler.schedulernode.SchedulerNode.index)[`SchedulerNode.init()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.scheduler.schedulernode.SchedulerNode.init)[`SchedulerNode.is_builtin`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.scheduler.schedulernode.SchedulerNode.is_builtin)[`SchedulerNode.is_local`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.scheduler.schedulernode.SchedulerNode.is_local)[`SchedulerNode.is_replay`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.scheduler.schedulernode.SchedulerNode.is_replay)[`SchedulerNode.jobname`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.scheduler.schedulernode.SchedulerNode.jobname)[`SchedulerNode.jobworkdir`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.scheduler.schedulernode.SchedulerNode.jobworkdir)[`SchedulerNode.logger`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.scheduler.schedulernode.SchedulerNode.logger)[`SchedulerNode.name`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.scheduler.schedulernode.SchedulerNode.name)[`SchedulerNode.project`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.scheduler.schedulernode.SchedulerNode.project)[`SchedulerNode.project_cwd`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.scheduler.schedulernode.SchedulerNode.project_cwd)[`SchedulerNode.replay_script`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.scheduler.schedulernode.SchedulerNode.replay_script)[`SchedulerNode.requires_run()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.scheduler.schedulernode.SchedulerNode.requires_run)[`SchedulerNode.run()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.scheduler.schedulernode.SchedulerNode.run)[`SchedulerNode.run_process()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.scheduler.schedulernode.SchedulerNode.run_process)[`SchedulerNode.runtime()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.scheduler.schedulernode.SchedulerNode.runtime)[`SchedulerNode.set_builtin()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.scheduler.schedulernode.SchedulerNode.set_builtin)[`SchedulerNode.set_queue()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.scheduler.schedulernode.SchedulerNode.set_queue)[`SchedulerNode.setup()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.scheduler.schedulernode.SchedulerNode.setup)[`SchedulerNode.setup_input_directory()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.scheduler.schedulernode.SchedulerNode.setup_input_directory)[`SchedulerNode.step`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.scheduler.schedulernode.SchedulerNode.step)[`SchedulerNode.summarize()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.scheduler.schedulernode.SchedulerNode.summarize)[`SchedulerNode.switch_node()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.scheduler.schedulernode.SchedulerNode.switch_node)[`SchedulerNode.task`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.scheduler.schedulernode.SchedulerNode.task)[`SchedulerNode.threads`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.scheduler.schedulernode.SchedulerNode.threads)[`SchedulerNode.topmodule`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.scheduler.schedulernode.SchedulerNode.topmodule)[`SchedulerNode.validate()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.scheduler.schedulernode.SchedulerNode.validate)[`SchedulerNode.workdir`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.scheduler.schedulernode.SchedulerNode.workdir)[`SlurmSchedulerNode`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.scheduler.slurm.SlurmSchedulerNode)[`SlurmSchedulerNode.assert_slurm()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.scheduler.slurm.SlurmSchedulerNode.assert_slurm)[`SlurmSchedulerNode.cancel()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.scheduler.slurm.SlurmSchedulerNode.cancel)[`SlurmSchedulerNode.cancel_nodes()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.scheduler.slurm.SlurmSchedulerNode.cancel_nodes)[`SlurmSchedulerNode.collect_keys()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.scheduler.slurm.SlurmSchedulerNode.collect_keys)[`SlurmSchedulerNode.get_configuration_directory()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.scheduler.slurm.SlurmSchedulerNode.get_configuration_directory)[`SlurmSchedulerNode.get_job_name()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.scheduler.slurm.SlurmSchedulerNode.get_job_name)[`SlurmSchedulerNode.get_runtime_file_name()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.scheduler.slurm.SlurmSchedulerNode.get_runtime_file_name)[`SlurmSchedulerNode.get_slurm_partition()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.scheduler.slurm.SlurmSchedulerNode.get_slurm_partition)[`SlurmSchedulerNode.init()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.scheduler.slurm.SlurmSchedulerNode.init)[`SlurmSchedulerNode.is_local`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.scheduler.slurm.SlurmSchedulerNode.is_local)[`SlurmSchedulerNode.jobhash`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.scheduler.slurm.SlurmSchedulerNode.jobhash)[`SlurmSchedulerNode.run()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.scheduler.slurm.SlurmSchedulerNode.run)[`RunListener`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.scheduler.listener.RunListener)[`RunListener.flow_finished()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.scheduler.listener.RunListener.flow_finished)[`RunListener.flow_started()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.scheduler.listener.RunListener.flow_started)[`RunListener.node_finished()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.scheduler.listener.RunListener.node_finished)[`RunListener.node_started()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.scheduler.listener.RunListener.node_started)[`RunListener.run_finished()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.scheduler.listener.RunListener.run_finished)[`RunListener.run_started()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.scheduler.listener.RunListener.run_started)[`Scheduler.add_listener()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.scheduler.Scheduler.add_listener)[`Scheduler.remove_listener()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.scheduler.Scheduler.remove_listener)[`SettingsManager`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.utils.settings.SettingsManager)[`SettingsManager.categories()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.utils.settings.SettingsManager.categories)[`SettingsManager.delete()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.utils.settings.SettingsManager.delete)[`SettingsManager.get()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.utils.settings.SettingsManager.get)[`SettingsManager.get_category()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.utils.settings.SettingsManager.get_category)[`SettingsManager.lock_category()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.utils.settings.SettingsManager.lock_category)[`SettingsManager.save()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.utils.settings.SettingsManager.save)[`SettingsManager.set()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.utils.settings.SettingsManager.set)[`SettingsManager.transaction()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.utils.settings.SettingsManager.transaction)[`Setting`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.utils.settings.Setting)[`Setting.add()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.utils.settings.Setting.add)[`Setting.get()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.utils.settings.Setting.get)[`Setting.is_list`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.utils.settings.Setting.is_list)[`Setting.normalize()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.utils.settings.Setting.normalize)[`Setting.remove()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.utils.settings.Setting.remove)[`Setting.set()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.utils.settings.Setting.set)[`Setting.unset()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.utils.settings.Setting.unset)[`SettingsCategory`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.utils.settings.SettingsCategory)[`SettingsCategory.setting()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.utils.settings.SettingsCategory.setting)[`KeyedSettingsCategory`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.utils.settings.KeyedSettingsCategory)[`KeyedSettingsCategory.setting()`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#siliconcompiler.utils.settings.KeyedSettingsCategory.setting)[Inheritance](https://docs.siliconcompiler.com/en/latest/reference_manual/schema_api.html#inheritance)[CLI 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paths](https://docs.siliconcompiler.com/en/latest/reference_manual/apps.html#app-sc-config-paths)[sc-install](https://docs.siliconcompiler.com/en/latest/reference_manual/apps.html#app-sc-install)[sc-issue](https://docs.siliconcompiler.com/en/latest/reference_manual/apps.html#app-sc-issue)[sc-remote](https://docs.siliconcompiler.com/en/latest/reference_manual/apps.html#app-sc-remote)[sc-server](https://docs.siliconcompiler.com/en/latest/reference_manual/apps.html#app-sc-server)[sc-show](https://docs.siliconcompiler.com/en/latest/reference_manual/apps.html#app-sc-show)[smake](https://docs.siliconcompiler.com/en/latest/reference_manual/apps.html#app-smake)[Support apps](https://docs.siliconcompiler.com/en/latest/reference_manual/apps.html#support-apps)[dashboard](https://docs.siliconcompiler.com/en/latest/reference_manual/apps.html#app-dashboard)[summarize](https://docs.siliconcompiler.com/en/latest/reference_manual/apps.html#app-summarize)[replay](https://docs.siliconcompiler.com/en/latest/reference_manual/apps.html#app-replay)[OpenROAD OpenRCX Merge Utility](https://docs.siliconcompiler.com/en/latest/reference_manual/apps.html#app-openroad-openrcx-merge-utility)[OpenROAD PEX Estimate Calibration Utility](https://docs.siliconcompiler.com/en/latest/reference_manual/apps.html#app-openroad-pex-estimate-calibration-utility)[Server API](https://docs.siliconcompiler.com/en/latest/reference_manual/server_api.html)[check_progress](https://docs.siliconcompiler.com/en/latest/reference_manual/server_api.html#check-progress)[Request](https://docs.siliconcompiler.com/en/latest/reference_manual/server_api.html#check-progress-request)[Response](https://docs.siliconcompiler.com/en/latest/reference_manual/server_api.html#check-progress-response)[remote_run](https://docs.siliconcompiler.com/en/latest/reference_manual/server_api.html#remote-run)[Request](https://docs.siliconcompiler.com/en/latest/reference_manual/server_api.html#remote-run-request)[Response](https://docs.siliconcompiler.com/en/latest/reference_manual/server_api.html#remote-run-response)[get_results/{job_hash}.tar.gz](https://docs.siliconcompiler.com/en/latest/reference_manual/server_api.html#get-results-job-hash-tar-gz)[Request](https://docs.siliconcompiler.com/en/latest/reference_manual/server_api.html#get-results-job-hash-tar-gz-request)[Response](https://docs.siliconcompiler.com/en/latest/reference_manual/server_api.html#get-results-job-hash-tar-gz-response)[cancel_job](https://docs.siliconcompiler.com/en/latest/reference_manual/server_api.html#cancel-job)[Request](https://docs.siliconcompiler.com/en/latest/reference_manual/server_api.html#cancel-job-request)[Response](https://docs.siliconcompiler.com/en/latest/reference_manual/server_api.html#cancel-job-response)[delete_job](https://docs.siliconcompiler.com/en/latest/reference_manual/server_api.html#delete-job)[Request](https://docs.siliconcompiler.com/en/latest/reference_manual/server_api.html#delete-job-request)[Response](https://docs.siliconcompiler.com/en/latest/reference_manual/server_api.html#delete-job-response)[check_server](https://docs.siliconcompiler.com/en/latest/reference_manual/server_api.html#check-server)[Request](https://docs.siliconcompiler.com/en/latest/reference_manual/server_api.html#check-server-request)[Response](https://docs.siliconcompiler.com/en/latest/reference_manual/server_api.html#check-server-response)[Leflib API](https://docs.siliconcompiler.com/en/latest/reference_manual/leflib_api.html)[`parse()`](https://docs.siliconcompiler.com/en/latest/reference_manual/leflib_api.html#sc_leflib.parse)[Uniquify API](https://docs.siliconcompiler.com/en/latest/reference_manual/uniquify_api.html)[Uniquified](https://docs.siliconcompiler.com/en/latest/reference_manual/uniquify_api.html#uniquified)[`Uniquified`](https://docs.siliconcompiler.com/en/latest/reference_manual/uniquify_api.html#siliconcompiler.tools.slang.utils.macro.Uniquified)[`Uniquified.__init__()`](https://docs.siliconcompiler.com/en/latest/reference_manual/uniquify_api.html#siliconcompiler.tools.slang.utils.macro.Uniquified.__init__)[`Uniquified.build()`](https://docs.siliconcompiler.com/en/latest/reference_manual/uniquify_api.html#siliconcompiler.tools.slang.utils.macro.Uniquified.build)[`Uniquified.design`](https://docs.siliconcompiler.com/en/latest/reference_manual/uniquify_api.html#siliconcompiler.tools.slang.utils.macro.Uniquified.design)[`Uniquified.hardened_filesets`](https://docs.siliconcompiler.com/en/latest/reference_manual/uniquify_api.html#siliconcompiler.tools.slang.utils.macro.Uniquified.hardened_filesets)[`Uniquified.instance_path()`](https://docs.siliconcompiler.com/en/latest/reference_manual/uniquify_api.html#siliconcompiler.tools.slang.utils.macro.Uniquified.instance_path)[`Uniquified.libdir`](https://docs.siliconcompiler.com/en/latest/reference_manual/uniquify_api.html#siliconcompiler.tools.slang.utils.macro.Uniquified.libdir)[`Uniquified.load_macros()`](https://docs.siliconcompiler.com/en/latest/reference_manual/uniquify_api.html#siliconcompiler.tools.slang.utils.macro.Uniquified.load_macros)[`Uniquified.macros`](https://docs.siliconcompiler.com/en/latest/reference_manual/uniquify_api.html#siliconcompiler.tools.slang.utils.macro.Uniquified.macros)[`Uniquified.manifest()`](https://docs.siliconcompiler.com/en/latest/reference_manual/uniquify_api.html#siliconcompiler.tools.slang.utils.macro.Uniquified.manifest)[`Uniquified.modules`](https://docs.siliconcompiler.com/en/latest/reference_manual/uniquify_api.html#siliconcompiler.tools.slang.utils.macro.Uniquified.modules)[`Uniquified.outdir`](https://docs.siliconcompiler.com/en/latest/reference_manual/uniquify_api.html#siliconcompiler.tools.slang.utils.macro.Uniquified.outdir)[`Uniquified.variant_names`](https://docs.siliconcompiler.com/en/latest/reference_manual/uniquify_api.html#siliconcompiler.tools.slang.utils.macro.Uniquified.variant_names)[`Uniquified.variants`](https://docs.siliconcompiler.com/en/latest/reference_manual/uniquify_api.html#siliconcompiler.tools.slang.utils.macro.Uniquified.variants)[`Uniquified.wireup()`](https://docs.siliconcompiler.com/en/latest/reference_manual/uniquify_api.html#siliconcompiler.tools.slang.utils.macro.Uniquified.wireup)[`Uniquified.wrapper_filesets`](https://docs.siliconcompiler.com/en/latest/reference_manual/uniquify_api.html#siliconcompiler.tools.slang.utils.macro.Uniquified.wrapper_filesets)[`Uniquified.write()`](https://docs.siliconcompiler.com/en/latest/reference_manual/uniquify_api.html#siliconcompiler.tools.slang.utils.macro.Uniquified.write)[Packaging a macro](https://docs.siliconcompiler.com/en/latest/reference_manual/uniquify_api.html#packaging-a-macro)[`build_macro()`](https://docs.siliconcompiler.com/en/latest/reference_manual/uniquify_api.html#siliconcompiler.tools.slang.utils.macro.build_macro)[Exceptions](https://docs.siliconcompiler.com/en/latest/reference_manual/uniquify_api.html#exceptions)[`UniquifyError`](https://docs.siliconcompiler.com/en/latest/reference_manual/uniquify_api.html#siliconcompiler.tools.slang.utils.uniquify.UniquifyError)

Appendix[Design Glossary](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/design_resources.html)[Architecture](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/design_resources.html#architecture)[Design](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/design_resources.html#design)[Manufacturing](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/design_resources.html#manufacturing)[Packaging](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/design_resources.html#packaging)[Test](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/design_resources.html#test)[Slurm setup](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/slurmsetup.html)[Initial Slurm Configuration](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/slurmsetup.html#initial-slurm-configuration)[User and Group Configuration](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/slurmsetup.html#user-and-group-configuration)[Slurm Daemon Installation](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/slurmsetup.html#slurm-daemon-installation)[Slurm Configuration Files](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/slurmsetup.html#slurm-configuration-files)[Slurm Startup](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/slurmsetup.html#slurm-startup)[Running SiliconCompiler on a Cluster](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/slurmsetup.html#running-siliconcompiler-on-a-cluster)[Licenses](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/licenses.html)[Software License](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/licenses.html#software-license)[Documentation License](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/licenses.html#documentation-license)[Dependency Licenses](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/licenses.html#dependency-licenses)[Revision History and Change Log](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html)[SiliconCompiler 0.38.11 (2026-10-15)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-38-11-2026-10-15)[SiliconCompiler 0.38.10 (2026-10-06)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-38-10-2026-10-06)[SiliconCompiler 0.38.9 (2026-09-21)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-38-9-2026-09-21)[SiliconCompiler 0.38.8 (2026-09-14)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-38-8-2026-09-14)[SiliconCompiler 0.38.7 (2026-09-03)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-38-7-2026-09-03)[SiliconCompiler 0.38.6 (2026-09-02)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-38-6-2026-09-02)[SiliconCompiler 0.38.5 (2026-08-18)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-38-5-2026-08-18)[SiliconCompiler 0.38.4 (2026-08-13)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-38-4-2026-08-13)[SiliconCompiler 0.38.3 (2026-08-10)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-38-3-2026-08-10)[SiliconCompiler 0.38.2 (2026-07-15)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-38-2-2026-07-15)[SiliconCompiler 0.38.1 (2026-07-09)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-38-1-2026-07-09)[SiliconCompiler 0.38.0 (2026-07-08)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-38-0-2026-07-08)[SiliconCompiler 0.37.12 (2026-06-09)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-37-12-2026-06-09)[SiliconCompiler 0.37.11 (2026-05-20)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-37-11-2026-05-20)[SiliconCompiler 0.37.10 (2026-05-11)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-37-10-2026-05-11)[SiliconCompiler 0.37.9 (2026-05-08)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-37-9-2026-05-08)[SiliconCompiler 0.37.8 (2026-05-04)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-37-8-2026-05-04)[SiliconCompiler 0.37.7 (2026-04-21)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-37-7-2026-04-21)[SiliconCompiler 0.37.6 (2026-04-15)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-37-6-2026-04-15)[SiliconCompiler 0.37.5 (2026-04-08)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-37-5-2026-04-08)[SiliconCompiler 0.37.4 (2026-03-25)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-37-4-2026-03-25)[SiliconCompiler 0.37.3 (2026-03-22)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-37-3-2026-03-22)[SiliconCompiler 0.37.2 (2026-03-09)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-37-2-2026-03-09)[SiliconCompiler 0.37.1 (2026-02-26)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-37-1-2026-02-26)[SiliconCompiler 0.37.0 (2026-02-24)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-37-0-2026-02-24)[SiliconCompiler 0.36.5 (2026-02-02)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-36-5-2026-02-02)[SiliconCompiler 0.36.4 (2026-01-31)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-36-4-2026-01-31)[SiliconCompiler 0.36.3 (2026-01-21)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-36-3-2026-01-21)[SiliconCompiler 0.36.2 (2026-01-16)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-36-2-2026-01-16)[SiliconCompiler 0.36.1 (2026-01-10)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-36-1-2026-01-10)[SiliconCompiler 0.36.0 (2026-01-06)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-36-0-2026-01-06)[SiliconCompiler 0.35.4 (2025-12-08)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-35-4-2025-12-08)[SiliconCompiler 0.35.3 (2025-11-10)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-35-3-2025-11-10)[SiliconCompiler 0.35.2 (2025-10-28)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-35-2-2025-10-28)[SiliconCompiler 0.35.1 (2025-10-17)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-35-1-2025-10-17)[SiliconCompiler 0.35.0 (2025-10-08)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-35-0-2025-10-08)[SiliconCompiler 0.34.3 (2025-08-11)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-34-3-2025-08-11)[SiliconCompiler 0.34.2 (2025-07-21)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-34-2-2025-07-21)[SiliconCompiler 0.34.1 (2025-07-07)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-34-1-2025-07-07)[SiliconCompiler 0.34.0 (2025-06-16)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-34-0-2025-06-16)[SiliconCompiler 0.33.2 (2025-06-03)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-33-2-2025-06-03)[SiliconCompiler 0.33.1 (2025-05-23)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-33-1-2025-05-23)[SiliconCompiler 0.33.0 (2025-05-19)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-33-0-2025-05-19)[SiliconCompiler 0.32.3 (2025-04-11)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-32-3-2025-04-11)[SiliconCompiler 0.32.2 (2025-03-31)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-32-2-2025-03-31)[SiliconCompiler 0.32.1 (2025-03-13)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-32-1-2025-03-13)[SiliconCompiler 0.32.0 (2025-03-11)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-32-0-2025-03-11)[SiliconCompiler 0.31.1 (2025-03-06)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-31-1-2025-03-06)[SiliconCompiler 0.31.0 (2025-03-03)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-31-0-2025-03-03)[SiliconCompiler 0.30.0 (2025-02-18)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-30-0-2025-02-18)[SiliconCompiler 0.29.4 (2025-02-06)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-29-4-2025-02-06)[SiliconCompiler 0.29.3 (2025-01-28)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-29-3-2025-01-28)[SiliconCompiler 0.29.2 (2025-01-16)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-29-2-2025-01-16)[SiliconCompiler 0.29.1 (2025-01-09)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-29-1-2025-01-09)[SiliconCompiler 0.29.0 (2024-12-12)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-29-0-2024-12-12)[SiliconCompiler 0.28.9 (2024-11-27)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-28-9-2024-11-27)[SiliconCompiler 0.28.8 (2024-11-20)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-28-8-2024-11-20)[SiliconCompiler 0.28.7 (2024-11-12)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-28-7-2024-11-12)[SiliconCompiler 0.28.6 (2024-11-12)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-28-6-2024-11-12)[SiliconCompiler 0.28.5 (2024-11-06)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-28-5-2024-11-06)[SiliconCompiler 0.28.4 (2024-10-28)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-28-4-2024-10-28)[SiliconCompiler 0.28.3 (2024-10-14)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-28-3-2024-10-14)[SiliconCompiler 0.28.2 (2024-10-02)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-28-2-2024-10-02)[SiliconCompiler 0.28.1 (2024-09-20)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-28-1-2024-09-20)[SiliconCompiler 0.28.0 (2024-09-18)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-28-0-2024-09-18)[SiliconCompiler 0.27.1 (2024-08-28)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-27-1-2024-08-28)[SiliconCompiler 0.27.0 (2024-08-28)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-27-0-2024-08-28)[SiliconCompiler 0.26.5 (2024-08-26)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-26-5-2024-08-26)[SiliconCompiler 0.26.4 (2024-08-22)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-26-4-2024-08-22)[SiliconCompiler 0.26.3 (2024-08-20)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-26-3-2024-08-20)[SiliconCompiler 0.26.2 (2024-08-15)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-26-2-2024-08-15)[SiliconCompiler 0.26.1 (2024-08-02)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-26-1-2024-08-02)[SiliconCompiler 0.26.0 (2024-07-30)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-26-0-2024-07-30)[SiliconCompiler 0.25.0 (2024-07-26)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-25-0-2024-07-26)[SiliconCompiler 0.24.1 (2024-07-11)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-24-1-2024-07-11)[SiliconCompiler 0.24.0 (2024-07-09)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-24-0-2024-07-09)[SiliconCompiler 0.23.4 (2024-07-02)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-23-4-2024-07-02)[SiliconCompiler 0.23.3 (2024-06-25)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-23-3-2024-06-25)[SiliconCompiler 0.23.2 (2024-06-20)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-23-2-2024-06-20)[SiliconCompiler 0.23.1 (2024-06-18)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-23-1-2024-06-18)[SiliconCompiler 0.23.0 (2024-06-13)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-23-0-2024-06-13)[SiliconCompiler 0.22.0 (2024-05-23)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-22-0-2024-05-23)[SiliconCompiler 0.21.13 (2024-05-15)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-21-13-2024-05-15)[SiliconCompiler 0.21.12 (2024-05-13)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-21-12-2024-05-13)[SiliconCompiler 0.21.11 (2024-04-26)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-21-11-2024-04-26)[SiliconCompiler 0.21.10 (2024-04-22)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-21-10-2024-04-22)[SiliconCompiler 0.21.9 (2024-04-12)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-21-9-2024-04-12)[SiliconCompiler 0.21.8 (2024-04-11)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-21-8-2024-04-11)[SiliconCompiler 0.21.7 (2024-04-02)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-21-7-2024-04-02)[SiliconCompiler 0.21.6 (2024-03-28)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-21-6-2024-03-28)[SiliconCompiler 0.21.5 (2024-03-21)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-21-5-2024-03-21)[SiliconCompiler 0.21.4 (2024-03-15)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-21-4-2024-03-15)[SiliconCompiler 0.21.3 (2024-03-13)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-21-3-2024-03-13)[SiliconCompiler 0.21.2 (2024-03-08)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-21-2-2024-03-08)[SiliconCompiler 0.21.1 (2024-03-07)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-21-1-2024-03-07)[SiliconCompiler 0.21.0 (2024-03-07)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-21-0-2024-03-07)[SiliconCompiler 0.20.3 (2024-03-06)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-20-3-2024-03-06)[SiliconCompiler 0.20.2 (2024-02-20)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-20-2-2024-02-20)[SiliconCompiler 0.20.1 (2024-02-12)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-20-1-2024-02-12)[SiliconCompiler 0.20.0 (2024-02-01)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-20-0-2024-02-01)[SiliconCompiler 0.19.1 (2024-01-24)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-19-1-2024-01-24)[SiliconCompiler 0.19.0 (2024-01-05)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-19-0-2024-01-05)[SiliconCompiler 0.18.2 (2023-12-18)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-18-2-2023-12-18)[SiliconCompiler 0.18.1 (2023-12-13)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-18-1-2023-12-13)[SiliconCompiler 0.18.0 (2023-12-04)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-18-0-2023-12-04)[SiliconCompiler 0.17.0 (2023-11-16)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-17-0-2023-11-16)[SiliconCompiler 0.16.3 (2023-11-02)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-16-3-2023-11-02)[SiliconCompiler 0.16.2 (2023-10-13)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-16-2-2023-10-13)[SiliconCompiler 0.16.1 (2023-10-11)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-16-1-2023-10-11)[SiliconCompiler 0.16.0 (2023-10-09)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-16-0-2023-10-09)[SiliconCompiler 0.15.4 (2023-09-25)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-15-4-2023-09-25)[SiliconCompiler 0.15.3 (2023-09-21)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-15-3-2023-09-21)[SiliconCompiler 0.15.2 (2023-09-18)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-15-2-2023-09-18)[SiliconCompiler 0.15.1 (2023-09-08)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-15-1-2023-09-08)[SiliconCompiler 0.15.0 (2023-08-31)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-15-0-2023-08-31)[SiliconCompiler 0.14.0 (2023-08-21)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-14-0-2023-08-21)[SiliconCompiler 0.13.2 (2023-08-10)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-13-2-2023-08-10)[SiliconCompiler 0.13.1 (2023-07-21)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-13-1-2023-07-21)[SiliconCompiler 0.13.0 (2023-07-07)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-13-0-2023-07-07)[SiliconCompiler 0.12.3 (2023-06-23)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-12-3-2023-06-23)[SiliconCompiler 0.12.2 (2023-06-14)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-12-2-2023-06-14)[SiliconCompiler 0.12.1 (2023-06-07)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-12-1-2023-06-07)[SiliconCompiler 0.12.0 (2023-05-24)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-12-0-2023-05-24)[SiliconCompiler 0.11.2 (2023-05-15)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-11-2-2023-05-15)[SiliconCompiler 0.11.1 (2023-05-03)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-11-1-2023-05-03)[SiliconCompiler 0.11.0 (2023-04-17)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-11-0-2023-04-17)[SiliconCompiler 0.10.2 (2023-04-04)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-10-2-2023-04-04)[SiliconCompiler 0.10.1 (2023-03-11)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-10-1-2023-03-11)[SiliconCompiler 0.10.0 (2023-03-08)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-10-0-2023-03-08)[SiliconCompiler 0.9.6 (2022-10-03)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-9-6-2022-10-03)[SiliconCompiler 0.9.5 (2022-09-12)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-9-5-2022-09-12)[SiliconCompiler 0.9.4 (2022-08-25)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-9-4-2022-08-25)[SiliconCompiler 0.9.3 (2022-08-01)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-9-3-2022-08-01)[SiliconCompiler 0.9.2 (2022-07-08)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-9-2-2022-07-08)[SiliconCompiler 0.9.1 (2022-06-21)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-9-1-2022-06-21)[SiliconCompiler 0.9.0 (2022-05-19)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-9-0-2022-05-19)[SiliconCompiler 0.7.0 (2022-03-02)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-7-0-2022-03-02)[SiliconCompiler 0.6.0 (2022-02-11)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-6-0-2022-02-11)[SiliconCompiler 0.4.1 (2022-01-06)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-4-1-2022-01-06)[SiliconCompiler 0.4.0 (2022-01-05)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-4-0-2022-01-05)[SiliconCompiler 0.3.1 (2021-12-21)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-3-1-2021-12-21)[SiliconCompiler 0.3.0 (2021-12-21)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-3-0-2021-12-21)[SiliconCompiler 0.1.1 (2021-12-08)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-1-1-2021-12-08)[SiliconCompiler 0.1.0 (2021-12-03)](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html#siliconcompiler-0-1-0-2021-12-03)[Schema Changes](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html)[0.57.2 -- 2026-09-28](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id1)[0.57.1 -- 2026-08-10](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id2)[0.57.0 -- 2026-07-21](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id3)[0.56.0 -- 2026-07-07](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id4)[0.55.0 -- 2026-07-01](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id5)[0.54.0 -- 2026-01-09](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id6)[0.53.1 -- 2026-01-06](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id7)[0.53.0 -- 2025-12-01](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id8)[0.52.1 -- 2025-10-31](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id9)[0.52.0 -- 2025-10-01](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id10)[0.51.5 -- 2025-08-29](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id11)[0.51.4 -- 2025-06-02](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id12)[0.51.3 -- 2025-05-16](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id13)[0.51.2 -- 2025-05-13](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id14)[0.51.1 -- 2025-05-09](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id15)[0.51.0 -- 2025-05-05](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id16)[0.50.0 -- 2025-02-21](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id17)[0.49.0 -- 2025-02-10](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id18)[0.48.6 -- 2024-12-20](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id19)[0.48.5 -- 2024-12-09](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id20)[0.48.4 -- 2024-11-05](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id21)[0.48.3 -- 2024-11-05](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id22)[0.48.2 -- 2024-09-18](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id23)[0.48.1 -- 2024-09-17](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id24)[0.48.0 -- 2024-09-15](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id25)[0.47.0 -- 2024-09-06](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id26)[0.46.0 -- 2024-09-06](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id27)[0.45.1 -- 2024-09-05](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id28)[0.45.0 -- 2024-09-04](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id29)[0.44.5 -- 2024-09-03](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id30)[0.44.4 -- 2024-08-27](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id31)[0.44.3 -- 2024-08-09](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id32)[0.44.2 -- 2024-07-29](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id33)[0.44.1 -- 2024-07-26](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id34)[0.44.0 -- 2024-07-25](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id35)[0.43.1 -- 2024-07-23](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id36)[0.43.0 -- 2024-07-22](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id37)[0.42.7 -- 2024-07-19](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id38)[0.42.6 -- 2024-07-09](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id39)[0.42.5 -- 2024-07-08](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id40)[0.42.4 -- 2024-07-08](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id41)[0.42.3 -- 2024-07-08](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id42)[0.42.2 -- 2024-07-08](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id43)[0.42.1 -- 2024-07-07](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id44)[0.42.0 -- 2024-07-07](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id45)[0.41.1 -- 2024-07-05](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id46)[0.41.0 -- 2024-07-03](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id47)[0.40.8 -- 2024-07-03](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id48)[0.40.7 -- 2024-07-02](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id49)[0.40.6 -- 2024-05-30](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id50)[0.40.5 -- 2024-05-28](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id51)[0.40.4 -- 2024-04-21](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id52)[0.40.3 -- 2024-03-14](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id53)[0.40.2 -- 2024-03-05](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id54)[0.40.1 -- 2024-02-28](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id55)[0.40.0 -- 2023-12-18](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id56)[0.39.0 -- 2023-11-17](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id57)[0.38.0 -- 2023-11-02](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id58)[0.37.2 -- 2023-11-02](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id59)[0.37.1 -- 2023-10-26](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id60)[0.37.0 -- 2023-09-20](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id61)[0.36.0 -- 2023-08-30](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id62)[0.35.0 -- 2023-08-03](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id63)[0.34.7 -- 2023-08-09](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id64)[0.34.6 -- 2023-08-08](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id65)[0.34.5 -- 2023-07-29](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id66)[0.34.4 -- 2023-07-27](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id67)[0.34.3 -- 2023-06-13](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id68)[0.34.2 -- 2023-06-09](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id69)[0.34.1 -- 2023-06-09](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id70)[0.34.0 -- 2023-05-19](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id71)[0.33.0 -- 2023-05-17](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id72)[0.32.0 -- 2023-04-12](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id73)[0.31.0 -- 2023-04-01](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id74)[0.30.0 -- 2023-04-07](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id75)[0.29.0 -- 2023-03-30](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id76)[0.28.0 -- 2023-03-06](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id77)[0.27.0 -- 2023-02-24](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id78)[0.26.0 -- 2023-02-21](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id79)[0.25.0 -- 2023-02-20](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id80)[0.24.0 -- 2023-02-13](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id81)[0.23.0 -- 2023-02-10](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id82)[0.22.0 -- 2023-02-02](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id83)[0.21.0 -- 2023-01-31](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id84)[0.20.0 -- 2023-01-27](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id85)[0.19.0 -- 2023-01-27](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id86)[0.18.0 -- 2023-01-26](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id87)[0.17.0 -- 2023-01-25](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id88)[0.16.1 -- 2023-01-21](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id89)[0.15.0 -- 2023-01-25](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id90)[0.14.0 -- 2023-01-22](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id91)[0.13.0 -- 2023-01-22](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id92)[0.12.0 -- 2023-01-18](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id93)[0.11.0 -- 2023-01-15](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id94)[0.10.0 -- 2023-01-01](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id95)[0.9.0 -- 2022-08-31](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#id96)[Machine-readable documentation](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/machine_readable.html)[Versions](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/machine_readable.html#versions)[The schema dump](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/machine_readable.html#the-schema-dump)[Dashboard](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/dashboard_how_to_guide.html)[Header](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/dashboard_how_to_guide.html#header)[Metrics Tab](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/dashboard_how_to_guide.html#metrics-tab)[Metrics Section](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/dashboard_how_to_guide.html#metrics-section)[Flowgraph Section](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/dashboard_how_to_guide.html#flowgraph-section)[Node Information Section](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/dashboard_how_to_guide.html#node-information-section)[File Viewer Tab](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/dashboard_how_to_guide.html#file-viewer-tab)[Manifest Tab](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/dashboard_how_to_guide.html#manifest-tab)[Display Preview Tab](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/dashboard_how_to_guide.html#display-preview-tab)[Graphs Tab](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/dashboard_how_to_guide.html#graphs-tab)


---

Source: https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/design_resources.html

## Design Glossary

A broad index of semiconductor design vocabulary, each entry linking out to
further reading.

> **Seealso**
> For the terms SiliconCompiler itself uses -- its objects, its execution
> model, and the subset of this vocabulary that appears in the documentation
> and in tool output -- see the [glossary](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#glossary).


### Architecture

- [ADC](https://en.wikipedia.org/wiki/Analog-to-digital_converter): Analog to Digital Converter
- [AES](https://en.wikipedia.org/wiki/Advanced_Encryption_Standard): Advanced encryption standard
- [Adder](https://en.wikipedia.org/wiki/Adder_%28electronics%29): Circuit to add two numbers
- [ALU](https://en.wikipedia.org/wiki/Arithmetic_logic_unit): Arithmetic logic unit
- [Amdahl's Law](https://en.wikipedia.org/wiki/Amdahl%27s_law): Amdahl's law of diminishing returns for speeding up fixed workloads
- [Arbiter](https://en.wikipedia.org/wiki/Arbiter_%28electronics%29): Arbitrates between competing requesters
- [ASIC](https://en.wikipedia.org/wiki/Application-specific_integrated_circuit): Application specific integrated circuit.
- [Audio codec](https://en.wikipedia.org/wiki/Audio_codec): Device/program that compresses/decompresses digital audio
- [Boolean algebra](https://en.wikipedia.org/wiki/Boolean_algebra): Algebra in which variables are either true or false
- [BTB](https://en.wikipedia.org/wiki/Branch_target_predictor): Branch target buffer
- [Cache](https://en.wikipedia.org/wiki/Cache_%28computing%29): Local storage of program and/or data for future use.
- [Cache coherence](https://en.wikipedia.org/wiki/Cache_coherence): Consistency of shared data that is stored in multiple local caches.
- [CAM](https://en.wikipedia.org/wiki/Content-addressable_memory): Content addressable memory
- [CISC](https://en.wikipedia.org/wiki/Complex_instruction_set_computing): Complex instruction set computing
- [Coprocessor](https://en.wikipedia.org/wiki/Coprocessor): A processor used to supplement operations of a primary (host) processor.
- [CPI](https://en.wikipedia.org/wiki/Cycles_per_instruction): Cycles per instruction
- [CPU](https://en.wikipedia.org/wiki/Central_processing_unit): Central processing unit
- [CRC](https://en.wikipedia.org/wiki/Cyclic_redundancy_check): Cyclic redundancy check
- [CSA](https://en.wikipedia.org/wiki/Carry-save_adder): Carry save adder
- [DAC](https://en.wikipedia.org/wiki/Digital-to-analog_converter): Digital to Analog Converter
- [Distributed Computing](https://en.wikipedia.org/wiki/Distributed_computing): Computer with components working towards common goal with without strict coupling.
- [DLL](https://en.wikipedia.org/wiki/Delay-locked_loop): Delay locked loop
- [DMA](https://en.wikipedia.org/wiki/Direct_memory_access): Direct memory access
- [DDR](https://en.wikipedia.org/wiki/Double_data_rate):Double data rate
- [DDS](https://en.wikipedia.org/wiki/Direct_digital_synthesizer): Direct digital synthesis
- [DSM](https://en.wikipedia.org/wiki/Distributed_shared_memory): Distributed shared memory
- [DSP](https://en.wikipedia.org/wiki/Digital_signal_processor): Digital signal processor
- [ECC](https://en.wikipedia.org/wiki/ECC_memory): Error correcting code
- [Ethernet](https://en.wikipedia.org/wiki/Ethernet): Family of standard network technologies
- [Fault Tolerance](https://en.wikipedia.org/wiki/Fault_tolerance): The ability of a system to keep operating in the event of failure of one of its components.
- [FRAM](https://en.wikipedia.org/wiki/Ferroelectric_RAM): Non-volatile RAM based on ferroelectric layer.
- [FPGA](https://en.wikipedia.org/wiki/Field-programmable_gate_array): Field-programmable gate array is a chip that can be reprogrammed "in the field".
- [FIFO](https://en.wikipedia.org/wiki/FIFO_%28computing_and_electronics%29): First in first out buffer
- [GPU](https://en.wikipedia.org/wiki/Graphics_processing_unit): Integrated circuit for accelerating the creation of graphics on a display.
- [DRAM](https://en.wikipedia.org/wiki/Dynamic_random-access_memory): Dynamic random-access semiconductor memory
- [Flash](https://en.wikipedia.org/wiki/Flash_memory): Non-volatile semiconductor memory
- [FFT](https://en.wikipedia.org/wiki/Fast_Fourier_transform): Fast Fourier transform
- [FPU](https://en.wikipedia.org/wiki/Floating_point): Floating point unit
- [GPIO](https://en.wikipedia.org/wiki/General-purpose_input/output): General purpose input output, controllable at run time
- [Gray code](https://en.wikipedia.org/wiki/Gray_code): Binary system where successive values differ by one bit
- [HBM](https://en.wikipedia.org/wiki/High_Bandwidth_Memory): High bandwidth memory
- [I2C](https://en.wikipedia.org/wiki/I%C2%B2C): Multi-master 2 wire bus
- [LAN](https://en.wikipedia.org/wiki/Local_area_network): Local area network
- [LFSR](https://en.wikipedia.org/wiki/Linear_feedback_shift_register): Linear feedback shift register
- [LSB](https://en.wikipedia.org/wiki/Least_significant_bit): Least significant bit
- [LUT](https://en.wikipedia.org/wiki/Lookup_table): An array that replaces runtime computation with a simpler array indexing operation
- [LVDS](https://en.wikipedia.org/wiki/Low-voltage_differential_signaling): Low-voltage differential signaling (also TIA/EIA-644)
- [MII](https://en.wikipedia.org/wiki/Media-independent_interface): Media independent interface for PHY chips
- [MIMD](https://en.wikipedia.org/wiki/MIMD): Multiple instructions multiple data architecture
- [MMU](https://en.wikipedia.org/wiki/Memory_management_unit): Memory management unit
- [MSB](https://en.wikipedia.org/wiki/Most_significant_bit): Most significant bit
- [MUX](https://en.wikipedia.org/wiki/Multiplexer): Multiplexer
- [Multiplier](https://en.wikipedia.org/wiki/Binary_multiplier): Binary multiplier
- [NCO](https://en.wikipedia.org/wiki/Numerically_controlled_oscillator): Numerically controlled oscillator
- [NOC](https://en.wikipedia.org/wiki/Network_on_a_chip): Network on a chip
- [Parallel Computing](https://en.wikipedia.org/wiki/Parallel_computing): A type of computation where many operations are carried out simultaneously.
- [PCM](https://en.wikipedia.org/wiki/Phase-change_memory): Phase change memory
- [PCIe](https://en.wikipedia.org/wiki/PCI_Express): High Speed serial computer expansion bus
- [PIC](https://en.wikipedia.org/wiki/Programmable_Interrupt_Controller): Programmable interrupt controller
- [Priority Encoder](https://en.wikipedia.org/wiki/Priority_encoder): A circuit or algorithm that compresses multiple binary inputs into a smaller number of outputs
- [PLL](https://en.wikipedia.org/wiki/Phase-locked_loop): Phase locked loop
- [PWM](https://en.wikipedia.org/wiki/Pulse-width_modulation): Pulse width modulation
- [Q](https://en.wikipedia.org/wiki/Q_%28number_format%29): Q fixed point number format
- [RAID](https://en.wikipedia.org/wiki/RAID): Redundant array of disks
- [Reconfigurable Computing](https://en.wikipedia.org/wiki/Reconfigurable_computing): Collection of customizable datapaths connected together by a fabric
- [RISC](https://en.wikipedia.org/wiki/Reduced_instruction_set_computing): Reduced instruction set computing
- [ROM](https://en.wikipedia.org/wiki/Read-only_memory): Read only memory (denser than RAM)
- [SBC](https://en.wikipedia.org/wiki/Single-board_computer): Single board computers
- [SDR](https://en.wikipedia.org/wiki/Software-defined_radio): Software defined radio
- [SERDES](https://en.wikipedia.org/wiki/SerDes): Serializer/deserializer
- [Shift Register](https://en.wikipedia.org/wiki/Shift_register): Set of registers that shifts bits one position at a time
- [SIMD](https://en.wikipedia.org/wiki/SIMD): Single instruction multiple data
- [Schmitt Trigger](https://en.wikipedia.org/wiki/Schmitt_trigger): Comparator circuit with hysteresis
- [SPI](https://en.wikipedia.org/wiki/Serial_Peripheral_Interface_Bus): Synchronous 4 wire master/slave interface
- [SRAM](https://en.wikipedia.org/wiki/Static_random-access_memory): Static random access semiconductor memory
- [TLB](https://en.wikipedia.org/wiki/Translation_lookaside_buffer): Translation lookaside buffer
- [UART](https://en.wikipedia.org/wiki/Universal_asynchronous_receiver/transmitter): Asynchronous 2 wire point to point interface
- [USB](https://en.wikipedia.org/wiki/USB): 2 wire point to point 5 V interface
- [Video codec](https://en.wikipedia.org/wiki/Video_codec): Device/program that compresses/decompresses digital video
- [Virtual Memory](https://en.wikipedia.org/wiki/Virtual_memory): The automatic mapping of virtual program addresses to physical addresses
- [VLIW](https://en.wikipedia.org/wiki/Very_long_instruction_word): Very long instruction level parallelism
- [WAN](https://en.wikipedia.org/wiki/Wide_area_network): Wide area network
- [WIFI](https://en.wikipedia.org/wiki/Wi-Fi): Wireless local area network
- [8b10b](https://en.wikipedia.org/wiki/8b/10b_encoding): Code that maps 8-bits to 10bit DC balanced symbols


### Design

- [Antenna effect](https://en.wikipedia.org/wiki/Antenna_effect): Plasma induced gate oxide damage that can occur during semiconductor processing.
- [Asynchronous logic](https://en.wikipedia.org/wiki/Asynchronous_circuit): Logic not governed by a clock circuit or global clock.
- [ATPG](https://en.wikipedia.org/wiki/Automatic_test_pattern_generation): Automatic test pattern generation
- [BIST](https://en.wikipedia.org/wiki/Built-in_self-test): Built in Self Test
- [Chip](https://en.wikipedia.org/wiki/Integrated_circuit): A set of electronic circuits on one small plate ("chip") of semiconductor material, normally silicon.
- [Clock domain crossing](https://en.wikipedia.org/wiki/Clock_domain_crossing): Traversal of signal in synchronous digital ssytem from one clock domain to another.
- [Clock gating](https://en.wikipedia.org/wiki/Clock_gating): Technique whereby clock in synchronous logic is shut off when idle.
- [CMOS](https://en.wikipedia.org/wiki/CMOS): Complimentary metal-oxide semiconductor
- [Cross talk](https://en.wikipedia.org/wiki/Crosstalk): The coupling of nearby signals on a chip, usually through capacitive coupling.
- [CTS](https://en.wikipedia.org/wiki/Clock_signal): Clock tree synthesis
- [Domino logic](https://en.wikipedia.org/wiki/Domino_logic): Fast clocked logic with reduced capacitive load
- [DEF](https://en.wikipedia.org/wiki/Design_Exchange_Format): Design Exchange Format for layout
- [DFM](https://en.wikipedia.org/wiki/Design_for_manufacturability): Extended DRC rules specifying how to make a high yielding design.
- [DFT](https://en.wikipedia.org/wiki/Design_for_testing): Design for test
- [Die](https://en.wikipedia.org/wiki/Die_%28integrated_circuit%29): Small block of semiconductor material that can be cut ("diced") from a silicon wafer.
- [DRC](https://en.wikipedia.org/wiki/Design_rule_checking): Design Rule Constraints specifying manufacturing constraints.
- [DV](https://en.wikipedia.org/wiki/Functional_verification): Design verification is the process of verifying that the logic design conforms to specification.
- [ECO](https://en.wikipedia.org/wiki/Engineering_change_order): Engineering change order
- [EDA](https://en.wikipedia.org/wiki/Electronic_design_automation): Electronic Design Automation tools used to enhance chip design productivity.
- [EDA companies](https://en.wikipedia.org/wiki/List_of_EDA_companies): List of EDA companies
- [Electromigration](https://en.wikipedia.org/wiki/Electromigration): Transport of material caused by the gradual movement of the ions in a conductor.
- [EMI](https://en.wikipedia.org/wiki/Electromagnetic_interference): Electromagnetic interference.
- [ESD](https://en.wikipedia.org/wiki/Electrostatic_discharge): Electrostatic discharge is the sudden flow of electricity between two electrically charged objects.
- [Fabless](https://en.wikipedia.org/wiki/Fabless_manufacturing): The design and sale of semiconductor devices while outsourcing the manufacturing to 3rd party.
- [FEOL](https://en.wikipedia.org/wiki/Front_end_of_line): Front end of line processing.
  Includes all chip processing up to but not including metal interconnect layers.
- [Flip-flop](https://en.wikipedia.org/wiki/Flip-flop_%28electronics%29):: A clocked circuit that has two stable states and can be used to store state information.
- [Foundry](https://en.wikipedia.org/wiki/Semiconductor_fabrication_plant): Semiconductor company offering manufacturing services.
- [Full custom design](https://en.wikipedia.org/wiki/Full_custom): Design methodology involving layout and interconnection of individual transistors.
- [GDSII](https://en.wikipedia.org/wiki/GDSII): Binary format of design database sent to foundry.
- [Hardware Emulation](https://en.wikipedia.org/wiki/Hardware_emulation): Process of imitating the behavior a system under design with another piece of hardware.
- [HDL](https://en.wikipedia.org/wiki/Hardware_description_language): Specialized hardware description language for describing electronic circuits.
- [Hold time](https://en.wikipedia.org/wiki/Flip-flop_%28electronics%29#Timing_parameters): Minimum time synchronous input should hold steady after clock event.
- [IP](https://en.wikipedia.org/wiki/Semiconductor_intellectual_property_core): Semiconductor reusable design blocks containing author's Intellectual Property.
- [IP Vendors](https://en.wikipedia.org/wiki/List_of_semiconductor_IP_core_vendors): List of commercial semiconductor IP vendors.
- [ISI](https://en.wikipedia.org/wiki/Intersymbol_interference): Intersymbol interference
- [Jitter](https://en.wikipedia.org/wiki/Jitter): Deviation from perfect periodicity.
- [Latchup](https://en.wikipedia.org/wiki/Latch-up): Short circuit due to creation of a low-impedance path between the power supply rails of a circuit.
- [Layout](https://en.wikipedia.org/wiki/Integrated_circuit_layout): Physical representation of an integrated circuit.
- [LEF](https://en.wikipedia.org/wiki/Library_Exchange_Format): Standard Cell Library Exchange Format layout.
- [Logical Effort](https://en.wikipedia.org/wiki/Logical_effort): Technique used to normalize (and optimize) digital circuits speed paths.
- [LVS](https://en.wikipedia.org/wiki/Layout_Versus_Schematic): Layout Versus Schematic software checks that the layout is identical to the netlist.
- [Mask Works](https://en.wikipedia.org/wiki/Integrated_circuit_layout_design_protection): Copyright law dedicated to 2D and 3D integrated circuit "layouts".
- [Mealy machine](https://en.wikipedia.org/wiki/Mealy_machine): A finite state machine whose outputs depend on current state and the current inputs.
- [Metastability](https://en.wikipedia.org/wiki/Metastability_in_electronics): Ability of a digital electronic system to persist for an unbounded time in an unstable equilibrium.
- [MLS](https://en.wikipedia.org/wiki/Moisture_sensitivity_level): Packaging and handling precautions for some semiconductors.
- [Moore Machine](https://en.wikipedia.org/wiki/Moore_machine): Finite state machine whose outputs depend only on its current state.
- [Moore's Law](https://en.wikipedia.org/wiki/Moore%27s_law): Observation by Moore that the number of transistors in an IC doubles approximately every two years.
- [MOSFET](https://en.wikipedia.org/wiki/MOSFET): Metal oxide field effect transistor.
- [MOSIS](https://en.wikipedia.org/wiki/MOSIS): Foundry service project offering MPWs and low volume manufacturing.
- [MPW](https://en.wikipedia.org/wiki/Multi-project_wafer_service): Multi-project wafer service that integrates multiple designs on one reticle (aka "shuttle").
- [MTBF](https://en.wikipedia.org/wiki/Mean_time_between_failures): Mean time between failures.
- [Multi-threshold CMOS](https://en.wikipedia.org/wiki/Multi-threshold_CMOS): CMOS technology with multiple transistor types with different threshold voltages.
- [Optical proximity correction](https://en.wikipedia.org/wiki/Optical_proximity_correction): Technique used to compensate for semiconductor diffraction/process effects.
- [Pass Transistor Logic](https://en.wikipedia.org/wiki/Pass_transistor_logic): Logic that connects input to non-gate terminal of mosfet transistor.
- [Physical design](https://en.wikipedia.org/wiki/Physical_design_%28electronics%29): Physical design flow ("layout").
- [PDK](https://en.wikipedia.org/wiki/Process_design_kit):  Process design kits consisting of a minimum set of files needed to design in a specific process.
- [Power gating](https://en.wikipedia.org/wiki/Power_gating): Technique used to reduce leakage/standby power by shutting of the supply to the circuit.
- [P&R](https://en.wikipedia.org/wiki/Place_and_route): Automated Place and Route of a circuit using an EDA tool.
- [PVT Corners](https://en.wikipedia.org/wiki/Process_corners): Represents the extreme process, voltage, temperature that could occur in a given semiconductor process.
- [Radiation Hardening](https://en.wikipedia.org/wiki/Radiation_hardening): Act of making devices resistant to damage caused by ionizing radiation.
- [RTL](https://en.wikipedia.org/wiki/Register-transfer_level): Design abstraction for digital circuit design.
- [Setup time](https://en.wikipedia.org/wiki/Flip-flop_%28electronics%29#Timing_parameters): Minimum time synchronous input should be ready before clock event.
- [SEU](https://en.wikipedia.org/wiki/Single_event_upset): Change of state caused by one single ionizing particle (ions, electrons, photons...).
- [Signoff](https://en.wikipedia.org/wiki/Signoff_%28electronic_design_automation%29): The final approval that the design is ready to be sent to foundry for manufacturing.
- [SOC](https://en.wikipedia.org/wiki/System_on_a_chip): System On Chip
- [Spice](https://en.wikipedia.org/wiki/SPICE): Open source analog electronic circuit simulator.
- [STA](https://en.wikipedia.org/wiki/Static_timing_analysis): Method of computing the expected timing of a digital circuit without requiring full circuit simulation.
- [Standard Cell Design](https://en.wikipedia.org/wiki/Standard_cell): Design process relying on a fixed set of standard cells.
- [Subthreshold Leakage](https://en.wikipedia.org/wiki/Subthreshold_conduction): Current between source and drain in MOSFET when transistor is "off".
- [Synchronous logic](https://en.wikipedia.org/wiki/Synchronous_circuit): Logic whose state is controlled by a synchronous clock.
- [Synthesis](https://en.wikipedia.org/wiki/Logic_synthesis): Translation of high level design description (e.g. Verilog) to a netlist format (e.g. standard cell gate level).
- [SystemC](https://en.wikipedia.org/wiki/SystemC): Set of C++ classes and macros for simulation. Commonly used for high level modeling and testing.
- [Tape-out](https://en.wikipedia.org/wiki/Tape-out): Act of sending photomask chip database ("layout") to the manufacturer.
- [TCL](https://en.wikipedia.org/wiki/Tcl): Scripting language used by most of the leading EDA chip design tools.
- [Transistor](https://en.wikipedia.org/wiki/Transistor): A semiconductor device used to amplify/switch electronic signals.
- [Verilog](https://en.wikipedia.org/wiki/Verilog): The dominant hardware description language (HDL) for chip design.
- [VLSI](https://en.wikipedia.org/wiki/Very-large-scale_integration): Very large Integrated Circuit (somewhat outdated term, everything is VLSI today).
- [Von Neumann architecture](https://en.wikipedia.org/wiki/Von_Neumann_architecture): Computer architecture in which instructions and data are stored in the same memory.
- [UVM](https://en.wikipedia.org/wiki/Universal_Verification_Methodology): Universal Verification Methodology


### Manufacturing

- [BEOL](https://en.wikipedia.org/wiki/Back_end_of_line): Back end of line processing for connecting together devices using metal interconnects.
- [Dicing](https://en.wikipedia.org/wiki/CMOS): Act of cutting up wafer into individual dies.
- [FinFet](https://en.wikipedia.org/wiki/Multigate_device): Non planar, double-gate transistor.
- [Photo-lithography](https://en.wikipedia.org/wiki/Photolithography): Process used in micro-fabrication to pattern parts of a thin film or the bulk of a substrate.
- [Photomasks](https://en.wikipedia.org/wiki/Photomask): Opaque plates with holes or transparencies that allow light to shine through in a defined pattern.
- [Reticle](https://en.wikipedia.org/wiki/Photomask): A set of photomasks used by a stepper to step and print patterns onto a silicon wafer.
- [Semiconductor Fabrication](https://en.wikipedia.org/wiki/Semiconductor_device_fabrication): Process used to create the integrated circuits.
- [Silicon](https://en.wikipedia.org/wiki/Silicon): Element (Si), forms the basis of the electronic revolution.
- [Silicon on insulator](https://en.wikipedia.org/wiki/Silicon_on_insulator): Layered silicon--insulator--silicon with reduced parasitic capacitance.
- [Stepper](https://en.wikipedia.org/wiki/Stepper): Machine that passes light through reticle onto the silicon wafer being processed.
- [TSV](https://en.wikipedia.org/wiki/Through-silicon_via): Vertical electrical connection (via) passing completely through a silicon wafer or die.
- [Wafer](https://en.wikipedia.org/wiki/Wafer_(electronics)):: Thin slice of semiconductor material used in electronics for the fabrication of integrated circuits.
- [Wafer thinning](https://en.wikipedia.org/wiki/Wafer_backgrinding): Wafer thickness reduction to allow for stacking and high density packaging.


### Packaging

- [3D IC's](https://en.wikipedia.org/wiki/Three-dimensional_integrated_circuit): The process of stacking integrated circuits and connecting them through TSVs.
- [BGA](https://en.wikipedia.org/wiki/Ball_grid_array): Ball grid array is a type of surface-mount packaging (a chip carrier) used for integrated circuits.
- [BGA substrate](https://en.wikipedia.org/wiki/Ball_grid_array): A miniaturized PCB that mates the silicon die to BGA pins.
- [Bumping](https://en.wikipedia.org/wiki/Flip_chip): Placing of bumps on wafer/dies in preparation for package assembly.
- [DIMM](https://en.wikipedia.org/wiki/DIMM): Dual in line memory module.
- [Flip-chip](https://en.wikipedia.org/wiki/Flip_chip): Method of bonding a silicon die to package using solder bumps.
- [IC Assembly](https://en.wikipedia.org/wiki/Integrated_circuit_packaging): Semiconductor die is encased in a supporting case "package".
- [Interposer](https://en.wikipedia.org/wiki/Interposer): Electrical interface used to spread a connection to a wider pitch.
- [Heat sink](https://en.wikipedia.org/wiki/Heat_sink): A passive heat exchanger.
- [Heat pipe](https://en.wikipedia.org/wiki/Heat_pipe): Device for efficiently transferring heat between two solid interfaces.
- [KGD](https://en.wikipedia.org/wiki/Wafer_testing): Known Good Die. Dies that have been completely tested at wafer probe.
- [Leadframe](https://en.wikipedia.org/wiki/Lead_frame): Metal structure inside a chip package that carry signals from the die to the outside.
- [POP](https://en.wikipedia.org/wiki/Package_on_package): Package on Package
- [SIP](https://en.wikipedia.org/wiki/System_in_package): System In Package
- [SMT](https://en.wikipedia.org/wiki/Surface-mount_technology): Technique whereby packaged chips are mounted directly onto the PCB surface.
- [Through-hole](https://en.wikipedia.org/wiki/Through-hole_technology): Technique where package pins are inserted in drilled holes and soldered on opposite side of the board.
- [Wirebond](https://en.wikipedia.org/wiki/Wire_bonding): Method of bonding a silicon die to a package using wires.
- [WSI](https://en.wikipedia.org/wiki/Wafer-scale_integration): Wafer scale integration


### Test

- [Arbitrary Waveform Generator](https://en.wikipedia.org/wiki/Arbitrary_waveform_generator): Electronic instrument used to generate arbitrary signal waveforms.
- [ATE](https://en.wikipedia.org/wiki/Automatic_test_equipment): Automatic Test Equipment for testing integrated circuits.
- [Burn-in](https://en.wikipedia.org/wiki/Burn-in): Process of screening parts for potential premature life time failures.
- [DIB](https://en.wikipedia.org/wiki/DUT_board): Device Interface Board for interfacing DUT to ATE. Also called DUT board, probe card, load board, PIB.
- [DMM](https://en.wikipedia.org/wiki/Multimeter): Electronic instrument for measuring voltage, current, and resistance.
- [DUT](https://en.wikipedia.org/wiki/Device_under_test): Device under test
- [FIB](https://en.wikipedia.org/wiki/Focused_ion_beam): Focused ion beam
- [JTAG](https://en.wikipedia.org/wiki/Joint_Test_Action_Group): Industry standard for verifying and testing/debugging printed circuit boards after manufacturing.
- [Logic Analyzer](https://en.wikipedia.org/wiki/Logic_analyzer): Electronic instrument for capturing multiple digital signal from a system.
- [MCM](https://en.wikipedia.org/wiki/Multi-chip_module): Multi-chip Module
- [Oscilloscope](https://en.wikipedia.org/wiki/Oscilloscope): Electronic instrument for tracking the change of an electrical signal over time.
- [Probe Card](https://en.wikipedia.org/wiki/Probe_card): A direct interface between electronic test systems and a semiconductor wafer.
- [SEM](https://en.wikipedia.org/wiki/Scanning_electron_microscope): Scanning electron microscope
- [Shmoo Plot](https://en.wikipedia.org/wiki/Shmoo_plot): An ASCII plot of a component response over a range of conditions.
- [Spectrum Analyzer](https://en.wikipedia.org/wiki/Spectrum_analyzer): Electronic instrument for measuring the power of the spectrum of an unknown signal.


---

Source: https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/slurmsetup.html

## Slurm setup

The SiliconCompiler project is capable of deferring individual job steps to hosts in a high-performance computing cluster.
Currently, only the [Slurm job scheduler](https://slurm.schedmd.com/overview.html) is supported.

In order to use this functionality, you will need access to a Slurm cluster.
Configuring a performant HPC cluster is outside the scope of this document, but this chapter will walk you through the process of configuring your local machine as a "cluster" consisting of a single host.
It will also describe how to test the Slurm functionality, and how to add new hosts to a cluster.

This chapter will use Ubuntu 20.04 as a target OS, but the process should be very similar for other UNIX-like systems.

> **Note**
> If you only need a cluster to test against rather than one to keep, there is
> a containerised one checked in at `setup/server/`. A single
> `docker compose up` brings up `slurmctld`, `slurmdbd`, `slurmrestd`
> and one or more compute nodes alongside `sc-server`, and it needs none of
> the host configuration described below. See
> [For Developers: Custom Servers](https://docs.siliconcompiler.com/en/latest/user_guide/remote_processing.html#custom-servers).


### Initial Slurm Configuration


#### User and Group Configuration

Before installing the Slurm software, you should create users and groups named slurm and munge:

```
groupadd slurm
groupadd munge
useradd slurm -g slurm
useradd munge -g munge
```

It is **VERY IMPORTANT** that these users and groups have the same UIDs and GIDs on every host in the cluster.
Our test "cluster" will only have a single host, but if you want to set up a real cluster later, you can create these groups and users with specific IDs:

```
groupadd slurm -g <slurm_gid>
groupadd munge -g <munge_gid>
useradd slurm -u <slurm_uid> -g <slurm_gid>
useradd munge -u <munge_uid> -g <munge_gid>
```

You can find existing user and group IDs in the /etc/passwd file, or by using the id and getent commands:

```
id -u <username>
getent group <groupname>
```

Note that changing a user or group's ID after it already exists can cause issues, because filesystem permissions are usually not updated to match the new IDs.


#### Slurm Daemon Installation

The core Slurm scheduling logic is contained in two daemons:

- slurmctld: The "Slurm control daemon" runs on a "control node". This daemon manages the "compute nodes" in a cluster and delegates jobs to them.
- slurmd: The "Slurm daemon" runs on "compute nodes". This daemon listens for new commands from the "control node", and executes jobs which are sent to the host that it is running on.

Because we are setting up a test cluster on a single host, we will run both daemons on the same machine.

The slurm daemons, and a supporting slurm-client package, should be available in the package managers of common Linux distributions.
In Ubuntu, you can install them with:

```
apt-get install slurmctld slurmd slurm-client
```

Slurm also relies on munge to encrypt communications between hosts.
It should be installed as a dependency of the Slurm packages, but if not:

```
apt-get install munge
```

Munge will create a default key when it is installed at /etc/munge/munge.key. This key must be identical on every host in the cluster, so if you set up a cluster with multiple hosts, you will need to copy this file onto every host in the cluster.
You can re-generate a new munge key with:

```
sudo create-munge-key
```


#### Slurm Configuration Files

A minimal Slurm cluster requires three basic configuration files:

- /etc/slurm-llnl/cgroup.conf: A "control group" configuration file.
  This describes which resources Slurm is allowed to access, and how Slurm should manage system resources.
- /etc/slurm-llnl/cgroup_allowed_devices.conf: A list of filesystem paths to devices which Slurm should be able to access.
  The name and location of this file is arbitrary; it will be referenced in the cgroup.conf file.
- /etc/slurm-llnl/slurm.conf: The core cluster configuration file.
  This describes which hosts should be included in a cluster, what those hosts' capabilities and roles are.
  It can also include config variables for various cluster behaviors.

Most of the contents of the example files presented here come from the Slurm project's documentation.
You may need to extend or modify them if you create a more complex cluster with more hosts or system resources.


##### cgroup.conf

A minimal /etc/slurm-llnl/cgroup.conf file is fairly brief:

```
CgroupMountpoint="/sys/fs/cgroup"
CgroupReleaseAgentDir="/etc/slurm-llnl/cgroup"
AllowedDevicesFile="/etc/slurm-llnl/cgroup_allowed_devices.conf"
ConstrainCores=no
ConstrainRAMSpace=yes
ConstrainSwapSpace=no
ConstrainDevices=no
AllowedRamSpace=100
AllowedSwapSpace=0
MaxRAMPercent=100
MaxSwapPercent=100
MinRAMSpace=30
```

If your Linux installation places its control group devices in a different directory from /sys/fs/cgroup, you may need to modify that parameter.

> **Note**
> Two options that older versions of this sample carried have since been
> retired and should not be set: TaskAffinity, gone since Slurm 23.02, and
> CgroupAutomount, which Slurm 24.05 reports as defunct
> (*"please remove it from cgroup.conf"*).

The AllowedDevicesFile parameter refers to the cgroup_allowed_devices.conf file which we will create in the next section.

You can read more about cgroup.conf parameters [in the Slurm documentation](https://slurm.schedmd.com/cgroup.conf.html).


##### cgroup_allowed_devices.conf

The list of cgroup devices which Slurm should be allowed to access is typically quite short.
This file path should match the value of AllowedDevicesFile in your etc/slurm-llnl/cgroup.conf file:

```
/dev/null
/dev/urandom
/dev/zero
/dev/sda*
/dev/cpu/*/*
/dev/pts/*
```

If your system has other core resources that the cluster may need to access, you can add those device paths here.


##### slurm.conf

The most reliable way of setting up a comprehensive slurm.conf file is by using Slurm's "configurator" tool, but the large number of fields can be confusing if you are new to Slurm.

The "configurator" is a self-contained HTML page that ships with the Slurm documentation package, so you can run it locally:

```
apt-get install slurm-wlm-doc
```

The "configurator" pages will then be installed on your local machine, and you will be able to open them in a web browser.
The default file paths in Ubuntu are:

```
/usr/share/doc/slurm-wlm/html/configurator.html
/usr/share/doc/slurm-wlm/html/configurator.easy.html
```

For our minimal single-host test cluster, you can skip the "configurator" and use this as a template:

```
# slurm.conf file.
# Put this file on all nodes of your cluster.
# See the slurm.conf man page for more information.
SlurmctldHost=<your_hostname>

MpiDefault=none
ProctrackType=proctrack/cgroup
ReturnToService=1
SlurmctldPidFile=/run/slurmctld.pid
SlurmdPidFile=/run/slurmd.pid
SlurmdSpoolDir=/var/spool/slurmd
SlurmUser=slurm
StateSaveLocation=/var/spool/slurm
SwitchType=switch/none
TaskPlugin=task/cgroup
#SrunPortRange=<start_port>-<end_port>

# SCHEDULING
SchedulerType=sched/backfill
SelectType=select/linear

# LOGGING AND ACCOUNTING
AccountingStorageType=accounting_storage/none
ClusterName=<cluster_name>

JobAcctGatherType=jobacct_gather/none
SlurmctldLogFile=/var/log/slurm-llnl/log.log
SlurmdLogFile=/var/log/slurm-llnl/dlog.log

# COMPUTE NODES
NodeName=<your_hostname> NodeAddr=<your_dns> Features=SHARED <host_info>
PartitionName=debug Nodes=<your_hostname> Default=YES MaxTime=INFINITE State=U
```

Note the Features=SHARED parameter in the compute node definition.
Slurm allows you to define attributes to restrict which compute nodes are allowed to run which jobs.
The SiliconCompiler project uses SHARED as a catch-all feature when more complex job delegation is not required.

The <your_hostname> values should be set to the output of the hostname command, and the <your_dns> value should be set to a value which DNS services will resolve to your host.
Cloud providers will typically provide a public DNS for virtual hosts, but you can use localhost for a test cluster on your local machine.

The <host_info> values define the capabilities of a compute node; number of CPUs, available RAM, etc.
You can get these values for a host by running slurmd -C, and copying the output from CPUs=[...] through RealMemory=[...]. You may want to reduce the RealMemory value a bit, because Slurm will take nodes out of service if their available RAM falls below that threshold.

The SrunPortRange value is commented out here, but you can use it to limit the range of ports which Slurm is allowed to use for "phoning home" from compute nodes to the control node.
If you want to avoid using reserved ports or set up a firewall rule with more restrictive port ranges than 0-65535, you can set your desired port range with this parameter.

The ClusterName parameter is arbitrary.
I like to name clusters after roads, but things like mountains, forests, mythical figures, etc.
are also good choices.
Slurm's documentation recommends using lowercase characters in the name.
It looks like this parameter is mostly used for accounting in Slurm's optional database extension, so it should not be too important in a minimal test cluster.

**Important note**: Every host in your cluster should use an identical slurm.conf file.
If you eventually set up a cluster with shared networked storage, you can easily propagate changes to slurm.conf by placing the file in shared storage, and making each host's /etc/slurm-llnl/slurm.conf file a symbolic link to <shared_storage>/slurm.conf.


#### Slurm Startup

To start your slurm cluster, all you need to do is restart the slurmctld and slurmd daemons.
These daemons should be restarted on all hosts in the cluster whenever you make changes to configuration files like slurm.conf:

```
sudo service restart slurmctld
sudo service restart slurmd
```

Once the daemons are running with the correct config files loaded, you should be able to issue commands to the cluster using srun:

```
srun hostname
```


#### Running SiliconCompiler on a Cluster

To run a SiliconCompiler job on your cluster, all you need to do is set the [`[option,scheduler,name]`](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#param-project-option-scheduler-name) schema parameter to slurm. If you are using the Python API:

```
project.option.scheduler.set_name('slurm')
```

If you are running a job from the command-line, simply add -scheduler slurm to the command.

There are a few restrictions to be aware of if you decide to set up a more complex cluster:

- Clustered jobs must be run from a host which is acting as the "control node" for a Slurm cluster.
- The build directory must be placed in a location which is accessible to all hosts in the cluster.
  If you have multiple hosts in your cluster, they will need to share a networked storage drive using a protocol such as NFS.


---

Source: https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/licenses.html

## Licenses


### Software License

Original SiliconCompiler software is licensed under an [Apache 2.0 license](https://github.com/siliconcompiler/siliconcompiler/blob/main/LICENSE).


### Documentation License

This document is released under a Creative Commons Attribution 4.0 International License.


### Dependency Licenses

SC relies on the following Python dependencies, which are licensed as shown.
Note this table includes dependencies of the dependencies directly declared by
SiliconCompiler.

|  |  |  |  |
| --- | --- | --- | --- |
| **Name** | **Version** | **License** | **Extra** |
| [distro](https://pypi.org/project/distro) | 1.9.0 | Apache Software License |  |
| [docker](https://pypi.org/project/docker) | 7.2.0 | Apache-2.0 |  |
| [fasteners](https://pypi.org/project/fasteners) | 0.20 | Apache-2.0 |  |
| [GitPython](https://pypi.org/project/GitPython) | 3.2.1 | BSD-3-Clause |  |
| [graphviz](https://pypi.org/project/graphviz) | 0.21 | MIT |  |
| [lambdapdk](https://pypi.org/project/lambdapdk) | 0.2.22 | Apache-2.0 |  |
| [orjson](https://pypi.org/project/orjson) | 3.13.0 | MPL-2.0 AND (Apache-2.0 OR MIT) |  |
| [packaging](https://pypi.org/project/packaging) | 26.3 | Apache-2.0 OR BSD-2-Clause |  |
| [pillow](https://pypi.org/project/pillow) | 12.3.0 | MIT-CMU |  |
| [psutil](https://pypi.org/project/psutil) | 7.2.2 | BSD-3-Clause |  |
| [PyGithub](https://pypi.org/project/PyGithub) | 2.10.0 | GNU Library or Lesser General Public License (LGPL) |  |
| [pyslang](https://pypi.org/project/pyslang) | 11.0.0 | MIT License |  |
| [PyYAML](https://pypi.org/project/PyYAML) | 6.0.3 | MIT License |  |
| [requests](https://pypi.org/project/requests) | 2.34.2 | Apache Software License |  |
| [rich](https://pypi.org/project/rich) | 15.0.0 | MIT License |  |
| [cocotb](https://pypi.org/project/cocotb) | 2.1.0 | BSD-3-Clause | cocotb |
| [pandas](https://pypi.org/project/pandas) | 3.0.6 | BSD License | dashboard |
| [streamlit](https://pypi.org/project/streamlit) | 1.65.0 | Apache-2.0 | dashboard |
| [streamlit-antd-components](https://pypi.org/project/streamlit-antd-components) | 0.3.2 | -- | dashboard |
| [streamlit-autorefresh](https://pypi.org/project/streamlit-autorefresh) | 1.0.1 | -- | dashboard |
| [pydata-sphinx-theme](https://pypi.org/project/pydata-sphinx-theme) | 0.19.0 | BSD License | docs |
| [sc-leflib](https://pypi.org/project/sc-leflib) | 0.5.2 | Apache-2.0 | docs |
| [Sphinx](https://pypi.org/project/Sphinx) | 8.2.3 | BSD-2-Clause | docs |
| [codespell](https://pypi.org/project/codespell) | 2.4.3 | GPL-2.0-only | lint |
| [tclint](https://pypi.org/project/tclint) | 0.9.0 | MIT License | lint |
| [google-vizier](https://pypi.org/project/google-vizier) | 0.1.21 | Apache Software License | optimizer |
| [aiohttp](https://pypi.org/project/aiohttp) | 3.14.5 | Apache-2.0 AND MIT | server |
| [fastjsonschema](https://pypi.org/project/fastjsonschema) | 2.22.2 | BSD License | server |
| [pytest](https://pypi.org/project/pytest) | 9.1.1 | MIT | test |
| [pytest-asyncio](https://pypi.org/project/pytest-asyncio) | 1.4.0 | Apache-2.0 | test |
| [pytest-cov](https://pypi.org/project/pytest-cov) | 7.1.0 | MIT | test |
| [pytest-split](https://pypi.org/project/pytest-split) | 0.11.0 | MIT License | test |
| [pytest-timeout](https://pypi.org/project/pytest-timeout) | 2.4.0 | DFSG approved; MIT License | test |
| [pytest-xdist](https://pypi.org/project/pytest-xdist) | 3.8.0 | MIT | test |
| [PyVirtualDisplay](https://pypi.org/project/PyVirtualDisplay) | 3.0 | BSD License | test |
| [responses](https://pypi.org/project/responses) | 0.26.3 | Apache-2.0 | test |


---

Source: https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/changelog.html

## Revision History and Change Log

The changes in each SiliconCompiler release version are described below. Commit
version shown in (). Where applicable, the contributors that suggested a given
feature are shown in [].


### SiliconCompiler 0.38.11 (2026-10-15)

**Major:**

- Removed the sc-dashboard and sc-server commands in favor of python3 -m siliconcompiler.apps.utils.dashboard and python3 -m siliconcompiler.remote.server, and the cleanup support app in favor of sc-config cache clean.

**Minor:**

- Added sc-config, which lists and changes settings, sets up and tests job status email, shows and sweeps the cache, and prints where SiliconCompiler keeps its files.
- Added --gui, --web and --shell to a node's replay.sh, where the tool supports them, to rerun the step in its GUI, web viewer or interactive prompt and leave it open; an sc-issue testcase's run.sh passes them through.
- Added RunListener, registered with Scheduler.add_listener, to hear a run start, each node start and finish, and the run end, and deprecated TaskScheduler.register_callback in its favor.
- Added opensta to the asic, asic-hls and asic-soda groups of sc-install.
- Tools:

- openroad: added pdn_dont_add_pins to power_grid, and made init_floorplan read a bump map produced by an earlier step.


### SiliconCompiler 0.38.10 (2026-10-06)

**Major:**

- Removed the public server as the default for remote runs, so a remote run now fails unless a server has been configured with sc-remote.

**Minor:**

- Added gitlab:// and s3:// dataroots, the latter through a new s3 extra, along with a +private form of every scheme and python:// paths to a directory inside a package.
- Masked dataroot credentials in logs, in the manifests a run writes for its tools, and in sc-issue testcases, which also leave out environment variables that look like secrets.
- Reworked file collection for remote runs and sc-issue so collected files keep their names, each file is stored once, and links inside a collected directory are kept.
- Changed sc-show without a file to open the richest view a build has, an odb ahead of the def beside it, and made sc-show -list print the order it searches in.
- Added nested -f and -F file lists, -I include directories and -v library files to Design.read_fileset.
- Added a toolscripts entry point so a package can add tools to sc-install or override SiliconCompiler's version pins, along with reusable workflows that keep those pins current and build their docker images.
- Tools:

- klayout: changed the screenshot margin to a percentage of the design's size, defaulting to 1%, rather than a distance in microns.
- openroad: fixed a def opened with sc-show losing its contents when a hierarchical netlist sat beside it, and detailed routing ignoring [asic,minlayer] and [asic,maxlayer].
- yosys: added cross-boundary optimization of a design that is not flattened, on by default with yosys 0.58 or newer, and SAT-based flip-flop merging through opt_dff_sat.


### SiliconCompiler 0.38.9 (2026-09-21)

**Minor:**

- Reworked how a run reuses an existing build directory: an upstream excluded by [option,from], [option,to] or [option,prune] that cannot supply what depends on it is now rebuilt, rather than the run failing on an input nothing in it can produce.
- Added a task's declared input and output to what decides whether a node has to rerun.
- Fixed a previous run's SKIPPED status being carried into the next run, which stopped a re-enabled step from running.
- Added token authentication for gitlab and bitbucket dataroots, and fixed tokens being sent under the wrong username, written into the logged clone URL, and prompted for on a machine that cannot answer.
- Moved pandas into the dashboard extra and added a server extra for running sc-server, so a default install carries only what a local flow needs.
- Sped up the initial load by deferring imports that only part of a run needs.
- Tools:

- openroad: added support for rectilinear floorplans, and required an explicit die and core area when a padring is used.


### SiliconCompiler 0.38.8 (2026-09-14)

**Minor:**

- Split the cache directory into dataroot for downloaded data sources and tools for the caches tools keep between runs, and added Task.cachedir so a tool cache lands where [option,cachedir] covers it.
- Added an automatic sweep of the data source cache at the start of a run, throttled to once a week and to entries unused for 90 days, both tunable through cleanupdays and cleanupinterval.
- Added Task.get_digest, a hash of everything that configures a task, for naming a cache directory after a configuration rather than after a tool.
- Reworked [option,continue], which is set on the node that may fail: nodes downstream of an excused failure now run on the inputs that did arrive instead of being skipped.
- Added run cancellation to the scheduler, which keeps queued nodes from starting and ends the ones already running along with their descendants.
- Fixed environment variables that are declared without a value being handed to the tool as None.
- Added docker as a cluster type for sc-server, moved its job directories under a build root, and pointed compute nodes at a cluster-wide cache rather than the home directory of whoever runs them.
- Added a docker compose deployment of a server and a slurm cluster under setup/server.
- Tools:

- bambu: write the compiler cache ccache keeps into the tool cache rather than the home directory.
- chisel: keep coursier's jar cache in the tool cache.
- keplerformal: added reset_port and reset_cycles to the sec task, and treat a difference the tool finds as a verdict rather than as a failure to run.
- openroad: added the scan_clock_mixing, scan_max_length and scan_max_chains scan chain controls to global placement, and made logic depth reporting ask for a single path per group so it no longer exhausts memory.
- opensta: made logic depth reporting ask for a single path per group so it no longer exhausts memory.
- verilator: write the compiler cache ccache keeps into the tool cache rather than the home directory.


### SiliconCompiler 0.38.7 (2026-09-03)

**Minor:**

- Shrank the tool container images: symbols are now stripped from every installed tool, packages a tool only needed to build itself are removed, link-time-only static archives are dropped, and a tool image is no longer copied into sc_tools when a dependent image already carries it. Added sc_remove_prereqs and sc_strip_prefix to the tool install helpers.
- Tools:

- chisel: install a JRE of its own rather than relying on the one surelog pulls in for its build, and skip the sbtn launchers built for other platforms.
- mlir: install only the components the flow and soda-opt need instead of the whole LLVM install tree.
- openroad: keep tie cells in the netlist written out for logical equivalence checking.


### SiliconCompiler 0.38.6 (2026-09-02)

**Minor:**

- Added LECFlow, a logical equivalence check flow, with combinational, sequential and k-induction checks. [jyrj]
- Added a SODA Synthesizer front end, which takes a machine learning model in MLIR through soda-opt and Bambu into the normal ASIC flow, along with SODAASICFlow and a tutorial and example. The elaboration, synthesis and ASIC flows now take a frontend flowgraph instead of a language, so a front end can live beside the tool driver it belongs to.
- Split tool output onto its own LOG and LOGERROR log levels so it can be told apart from SiliconCompiler's own messages, and made quiet apply to a task's own logging without hiding why a run stopped.
- Reworked SDC clock extraction to handle line continuations, variables and the SDC files of timing modes, and added get_clock_port.
- Added job cancellation to the remote server and the slurm scheduler, along with job ownership checks, an upload size limit, and a client that works before a server has been configured.
- Fixed sc-show to honor the tool it was given, and to find the open, show and screenshot tasks that are not hard-coded.
- Moved the tool container builds to Ubuntu 24.
- Tools:

- bambu: added RTL simulation, cell area and cycle count reporting, and parameters for the constraints and technology files, memory allocation policy, front-end compiler and testbench filesets.
- mlir: added a tool driver for the MLIR tools.
- openroad: added support for the ccs delay model and logic depth histogram reports.
- opensta: added support for the ccs delay model and an interactive open task.
- soda: added a soda-opt tool driver.
- yosys: added an interactive open task.


### SiliconCompiler 0.38.5 (2026-08-18)

**Minor:**

- Added the gt2n_demo and icsprout55_demo targets.
- Added set_dieoutline and set_coreoutline, which take the width and height in the same order as get_diesize and get_coresize return them. These deprecate set_diearea_rectangle and set_corearea_rectangle, which took the height first.
- Allowed the tool install scripts to run without sudo access when the prerequisite packages are already present, which makes an unprivileged install into the default ~/.local prefix possible.
- Tools:

- openroad/opensta: brought the setup and hold timing reports to parity, filled in the reports that were missing, and moved the per-corner reports into a per-scenario directory.


### SiliconCompiler 0.38.4 (2026-08-13)

**Minor:**

- Added PNRFlow, a place-and-route only flow, which ASICFlow is now assembled from.
- Added computation of the core or die area from coremargin when only one of the two is provided.
- Added support for xz and Zstandard compressed tarballs to package downloads, and switched archive format detection to the contents of the download rather than its name.
- Ensured the remote configuration file, which can hold a plaintext password or API key, is only readable by the user.
- Sped up manifest writing for manifests containing non-ASCII characters.
- Reorganized the documentation landing page, and added a padring tutorial and example, simulation and OpenROAD how-tos, and an external libraries page.
- Tools:

- openroad: aligned the place-and-route flow with ORFS and LibreLane, adding an opt-in timing repair on the global routing parasitics (rsz_enable) and a new antenna repair node after detailed routing, added an opt-in setup timing repair on the synthesized netlist (repair_synth_timing), which is an alternative to removing the synthesis buffers rather than additive.


### SiliconCompiler 0.38.3 (2026-08-10)

**Major:**

- Removed the Schematic schema, since it was unused.

**Minor:**

- Added flowgraph callbacks, allowing flows to be modified after being inserted into a project.
- Added a beta version of hierarchy handling to elaboration to support parameterized modules.
- Added csv as an accepted task manifest format.
- Fixed unsupported schedulers being silently accepted.
- Fixed remote package re-download and ensured cached packages are only extracted once.
- Expanded the documentation with new tutorials, examples, FAQs, and how-tos, along with link checking.
- Added Ubuntu 26 and RHEL 9 tool build fixes with build selection and a weekly build schedule.
- Tools:

- openroad: added a PEX correlation methodology, along with the openroad_pex flow and calibration APIs, which replaces generate_openroad_rcx.
- openroad/opensta: reorganized the generated reports to make them easier to follow.
- verilator: added support for --trace-structs and --trace-depth. [HU90m]
- sby: switched the default engine from boolector to bitwuzla.


### SiliconCompiler 0.38.2 (2026-07-15)

**Minor:**

- Added a cached schema class to speed up loading, with support for frozen schemas.
- Added system-wide settings, letting an administrator provide machine-wide defaults.
- Added tool-install checks to avoid rebuilding already-installed tools.
- Tools:

- opensta: added support for reading VCD files for switching-activity-driven timing analysis.
- yosys: removed the standalone yosys-slang plugin now that it ships with yosys 0.67.


### SiliconCompiler 0.38.1 (2026-07-09)

**Minor:**

- Added a formal property check flow (PropertyCheckFlow) for BMC, cover, and prove modes.
- Tools:

- sby: added a SymbiYosys formal verification tool with install scripts for Ubuntu 22/24/26.
- yosys: refactored synthesis scripts and shared TCL procs, and added tests for slang usage.


### SiliconCompiler 0.38.0 (2026-07-08)

**Major:**

- Removed support for Python 3.9.
- Changed the global-value key from global to * to avoid name conflicts, with legacy read support for older manifests.
- Added rename_node to allow flowgraph nodes to be renamed.
- Added value ranges and limits to schema types using Ada-style notation, e.g. int<0..100>, float<..1.0>, and enums like str<a,b,c>.
- Moved the dashboard to an optional dependency.

**Minor:**

- Added language detection to targets.
- Added a warning when installed pip package versions are out of sync.
- Made get_cores aware of the scheduler's processor affinity.
- Allowed partial matches when setting and getting flows.
- Made filelist generation depth first.
- Added Ubuntu 26 tool install scripts.
- Fixed warnings about leaked resources and mishandled atexit cleanup.
- Tools:

- openroad: added a parasitic extraction (PEX) interface to the PDK with a warning when no corner is found, and added a dedicated cleanup task that moves logic cleanup out of floorplanning.
- montage: added a convert tool, automatic montage handling, and host-scaled ImageMagick resource limits via a private policy.xml.
- icarus/verilator: added a parameter to set the timescale for compilation.


### SiliconCompiler 0.37.12 (2026-06-09)

**Minor:**

- Added breakpoint handling in the scheduler to avoid multiple breakpoints from running at the same time.
- Tools:

- img2stream: added LEF output.
- pyslang: updated to version 11.
- openroad: fixed write_views on missing OpenRCX files.
- verilator: added support for verilog only testbenches.


### SiliconCompiler 0.37.11 (2026-05-20)

**Minor:**

- Fixed error message in smake when no file is provided.
- Improved path/dir/file type checking in schema types.
- Fixed issue where flows would be marked as failed when using option,from.
- Added preferred indicator to sc-show -list.


### SiliconCompiler 0.37.10 (2026-05-11)

**Minor:**

- Fixed flowgraph handling of builtin tasks, like min and max, to correctly handle the input/output file checks.
- Fixed the time reporting on the dashboard to avoid double counting parallel tasks.
- Tools:

- openroad: added checks for pin placement outside die area and added support for glob skip reports.


### SiliconCompiler 0.37.9 (2026-05-08)

**Minor:**

- Made the breakpoint interface more robust and fixed issues with text getting garbled.
- Fixed issue when setting option,from where flowgraph would ignore it if the step appeared in a leg with parallel paths.
- Tools:

- openroad: added better handling of pin placement.


### SiliconCompiler 0.37.8 (2026-05-04)

**Major:**

- Added OpenTask as parent class to ShowTask and ScreenshotTask, which enable opening in the commandline.

**Minor:**

- Added .write_depgraph to Project to enable displaying the dependency graph of a project.
- Fixed calls to sc-issue to remove the requirement to add -cfg.
- Fixed file collection to avoid collecting a file twice.
- Updated log reading handling to better handle tools that emit partial lines.
- Fixed git file resolver when LFS is used.
- Tools:

- openroad: added support for OpenTask and reordered the creation of placement blockages.


### SiliconCompiler 0.37.7 (2026-04-21)

**Minor:**

- Added dataroot resolver to allow for nesting dataroots.
- Fixed log files accumulating in the build directory and updated log naming to make it easier to identify runs.
- Added job termination when system memory exceeds 99% utilization.
- Tools:

- openroad: added support for placement and routing blockages in init floorplan.


### SiliconCompiler 0.37.6 (2026-04-15)

**Minor:**

- Switched to marking cached downloads as readonly to avoid accidental overwrites.
- Added utility app to cleanup caches with python3 -m siliconcompiler.apps.utils.cleanup.
- Updated targets to map regfiles from lambdalib.
- Added scp based file path resolver to allow files to be copied between machines.
- Tools:

- openroad: Added option to check that all pins are placed and remove blockages created during macro placement.


### SiliconCompiler 0.37.5 (2026-04-08)

**Minor:**

- Added -tool option to sc-show to allow for tool filtering.
- Ensure the flow restarts when the topmodule name changes.
- Tools:

- openroad: Added support for handling 3D pin placement, reordered macro placement to occur before padring generation, and added 3D blox viewing support.


### SiliconCompiler 0.37.4 (2026-03-25)

**Minor:**

- Tools:

- cocotb: Added plusargs task to allow for easier access to plusargs in simulations.


### SiliconCompiler 0.37.3 (2026-03-22)

**Minor:**

- Updated layout handling of the dashboard to better handle future modifications.
- Added help screen to dashboard and basic controls for what is displayed.
- Added check for adding dependencies to projects without a name.
- Added support for ?submodules=<True/False> for git dataroots to control pulling submodules.
- Tools:

- klayout: added task to convert images to GDS.
- vcd2fst: added to support converting VCD files to FST.


### SiliconCompiler 0.37.2 (2026-03-09)

**Minor:**

- Fixed recursive call on .write_fileset to avoid excessive recursion.
- Fixed file log installation to ensure the log contains errors from tool setup.
- Added additional error checks when adding aliases to check for no-op aliases.
- Added basic handling of type hinting to smake.
- Tools:

- openroad: update scripts to provide initial handling of multi-mode timing.
- opensta: update scripts to provide initial handling of multi-mode timing.


### SiliconCompiler 0.37.1 (2026-02-26)

**Minor:**

- Fixed handling of tokens during github+private dataroot resolution.
- Fixed from_dict handling to correctly restore a schema from file.
- Ensure the checks in .run() gracefully handle missing files.
- Tools:

- klayout: default to writing gzipped files.
- openroad: default to writing gzipped odb and def files.


### SiliconCompiler 0.37.0 (2026-02-24)

**Major:**

- Changed schema to make design object base class for all libraries.

**Minor:**

- Fixed resizing of dashboard to ensure logs are visible after resize.
- Fixed dashboard use when breakpoints are present.
- Fixed sc-show to correctly handle -cfg.
- Fixed flowgraph handling when using option,from.
- Updated time format in dashboard to make it easier to read.
- Added get_flow to Project class to allow access to the loaded flowgraphs.
- Tools:

- klayout: added stream2lef task to generate a lef from a GDS or OAS file.
- openroad: fixed version parsing.
- opensta: added write_sdf and write_liberty support to timing task.
- vpr: updated pin constraint handling.


### SiliconCompiler 0.36.5 (2026-02-02)

**Minor:**

- Fixed dashboard line wrapping to correctly account for the width of the terminal.
- Reworked error handling to ensure backtrace is available when running with the dashboard.


### SiliconCompiler 0.36.4 (2026-01-31)

**Minor:**

- Fixed commandline handling of sc-issue when -cfg is missing.
- Added support for -jobs to sc-install to control number of build jobs.
- Updated detection of editable python installs.
- Fixed json serialization bug when journal is active.
- Tools:

- yosys: removed default use of kogge-stone techmap pass.
- openroad: correctly include lefs in floorplanning required keys.
- icarus, verilator: added support for cocotb plugins.


### SiliconCompiler 0.36.3 (2026-01-21)

**Minor:**

- Tools:

- builtin: added wait task to better handle stalling flow progress
- klayout: added merge task to provide a simple interface for merging multiple GDSs
- pyslang: updated to v10.0.0


### SiliconCompiler 0.36.2 (2026-01-16)

**Minor:**

- Corrected auto dataroot behavior when setting abs paths.
- Corrected logging during check_filepaths on design objects to ensure errors are printed.
- Added .get_library to Project to allow access to imported libraries.
- Tools:

- openroad: added option to bypass SDC loading.


### SiliconCompiler 0.36.1 (2026-01-10)

**Minor:**

- Expanded parameter setters for tasks.
- Tools:

- openroad: fixed pin constraints handling, added support for editing halos.


### SiliconCompiler 0.36.0 (2026-01-06)

**Major:**

- Changed schema to better handle timing constraints, by splitting out mode specific information from the scenarios.

**Minor:**

- Reimplemented flowgraph rendering with file IO information.
- Fixed tool version checking to support threaded runs.
- Reworked use of pipes during execution to avoid creating more pipes than needed.
- Fixed flowgraph IO checks to only check required files.
- Tools:

- klayout: fixed handling of GDS generation when foreign is specified in lef.
- openroad: added support for halo constraints.
- kelper-formal: added initial support for LEC with kepler-formal.


### SiliconCompiler 0.35.4 (2025-12-08)

**Major:**

- Added support for settings.json to allow users to set defaults and persistent options and controls for slurm nodes.

**Minor:**

- Added limit to the number of warnings/errors that will be printed to the terminal.
- Added copy_* methods to timing constraints to better support building multiple modes.
- Added support for flow to run collection if the specific node requires it.
- Added check for conflicting flow tasks and generate an error if one is found.
- Added Python 3.14 to testing matrix.
- Improved logging to help identify specific log files.
- Ensured data is cleaned up when a failure occurs while downloading remote data.
- Corrected missing history when failures occur in the flow.
- Fixed bug causing skipped tasks to not get re-executed when restarting flow.
- Tools:

- yosys: added warning to indicate that slang was not found, added controls for undefined signals, and buffer insertion.
- openroad: added support for using bmaps to place bumps, added IR drop task to provide better "what-if" analysis.
- vivado: added support for pre/post scripts.


### SiliconCompiler 0.35.3 (2025-11-10)

**Minor:**

- Added support for downloading .bz2 files as dataroots.
- Added new accessor methods to Flowgraph.
- Implemented lazy loading for the schema to significantly speed up loading from disk.
- Implemented multithreaded checks at the start of .run() to accelerate the determination of which nodes need to be re-run.
- Optimized runtime handling of .active_* attributes to avoid excessive copying.
- Corrected file upload behavior for the remote runner.
- Tools:

- klayout: Fixed the screenshot task to ensure it can be correctly inserted into a flowgraph.


### SiliconCompiler 0.35.2 (2025-10-28)

**Minor:**

- Corrected sc-issue handling of libraries to properly include pdk information.
- Added .find_task to Task class to replace get_task and deprecated this method.
- Restored missing copy flags in schema to ensure proper upload to remote runners.
- Added tool version check to start of .run() to allow for early version checking when possible.
- .check_filepaths now checks dependency filepaths too.
- Tools:

- builtin: added tasks for filtering files between nodes and entry node to copy files into the build directory.
- gtkwave: added fst to supported file extensions.
- openroad: fixed screenshot task to allow for insertion into flows and handling of timing information.
- surfer: added fst to supported file extensions.
- verilator: fixed path used for automatic VCD dump.


### SiliconCompiler 0.35.1 (2025-10-17)

**Minor:**

- Added support for providing external tool install scripts and groups to sc-install.
- Fixed installation order in sc-install to use lists instead of sets, preserving the intended group ordering.
- Fixed path handling to correctly resolve paths when dataroot starts with an environment variable.
- Updated task scheduling to more reliably honor the node order defined in the flowgraph.
- Tools:

- opensta: reimplemented task skipping logic for FPGA timing analysis.


### SiliconCompiler 0.35.0 (2025-10-08)

This release introduces a major architectural overhaul to improve usability, flexibility, and error checking.
These are changes that will require you to update all your existing scripts and workflows.
This is a release towards reaching v1.0.0.

**Major:**

- The monolithic Chip object has been replaced by a set of target-specific Project classes (ASIC, FPGA, Sim, and Lint). This change provides better type-hinting, validation, and isolates settings for different targets.
- The Design class is now the primary interface for managing sources. The old .input() calls have been replaced by a more structured "fileset" system, allowing you to group related files (e.g., RTL, SDC, etc.) and toggle them easily.
- The command-line dashboard, which shows real-time progress of a run, is now on by default for interactive sessions. This can be controlled via .option.set_nodashboard(True).
- The sc command-line application has been removed in favor of using Python scripts directly for better reproducibility. The .clock() helper method has also been removed.
- While direct schema manipulation with .set() and .add() remains supported, we now recommend using a more "Pythonic" API with helper methods for common settings. This improves code readability and reduces errors from misspelled keys.
- All task drivers have been rewritten to the new API.
- The core API has been refactored to be more object-oriented. Instead of interacting with a single, monolithic Chip object, you now work with distinct objects that have clear responsibilities, such as Project and Design.

**Minor:**

- Significantly expanded testing coverage of user facing methods to better support checks for backwards compatibility.


### SiliconCompiler 0.34.3 (2025-08-11)

**Minor:**

- Implemented support for sets in schema, denoted by {}.
- Fixed cache folder handling by appending unique ID to each folder to avoid name collisions.
- Command line dashboard shows siliconcompiler log when tool log is not available, output is now preserved on exit, and improved handling of multiple jobs layout.
- Added job.log to build directory to provide a file source for the logging as well as the terminal.
- Tools:

- slang: updated to slang v9.0.


### SiliconCompiler 0.34.2 (2025-07-21)

**Minor:**

- Fixed handling of tool command line arguments to ensure they are all strings.
- Fixed handling of schema parameters with default fields beyond just value.
- Fixed handling of schema set parameters.
- Added time delays when packages are locked to avoid deadlocks.
- Moved package caching to Resolver class to allow for shared caching across schema sections.
- Modified return value of .getkeys() to return a sorted tuple of the keys.


### SiliconCompiler 0.34.1 (2025-07-07)

**Major:**

- Removed support for Python 3.8.
- Changed node names from {step}{index} to {step}/{index} [Ciprian167].

**Minor:**

- Ensure only tool outputs are forwarded for skipped nodes.
- Tools:

- openroad: limit default max displacement for detailed placement optimizations.
- opensta: added support to gracefully handle empty input files.
- surfer: added support for surfer for waveform viewing [infinitymdm].
- vpr: added support to generate timing analysis files.


### SiliconCompiler 0.34.0 (2025-06-16)

**Major:**

- Added .find_files and .check_filespaths functionality to BaseSchema.
- Added functionality to BaseSchema to allow reverse traversal of the schema.
- Removed support for paths containing environmental variables.

**Minor:**

- Added a values only mode to getdict to only return the values in the schema.
- Changes the log color in the commandline dashboard to white for better visibility.


### SiliconCompiler 0.33.2 (2025-06-03)

**Minor:**

- Fixed bug in git submodule checkouts that left the incorrect version of the submodules checked out.
- Updated replay script to provide access to replay python scripts.
- Fixed bug in remote client that caused errors when running with hashing turned on.
- Updated [record,starttime] and [record,endtime] to include microseconds.
- Tools:

- slang: updated to version 8.1.


### SiliconCompiler 0.33.1 (2025-05-23)

**Minor:**

- Removed flowgraph utility functions and replaced with calls to flowgraph class.
- Fixed manifest merging during remote run.
- Switched core scheduler code to be class instead of a collection methods.
- Attempt to determine if sudo is needed during sc-install and selectively apply it.
- Tools:

- opensta: added support for sdf reading.
- slang: use elaboration for linting to ensure user feedback.
- yosys: ensure cell areas are annotated before determining flattening.


### SiliconCompiler 0.33.0 (2025-05-19)

**Major:**

- Core schema infrastructure rewritten to provide better testing and easier use when integration changes.

**Minor:**

- Added multi-job handling to command line dashboard and corrected handling of coloring in the log.
- Updated help, scopes, and default values in various keys int he schema.
- Allow packages to reference keys as data source.
- Speedup load time by selective loading large libraries.
- Added caching to flowgraph node handling to speed up common use cases.
- Tools:

- openroad: added gif of IR drop
- yosys: improved yosys-slang integration
- sv2v: allow runtime bypass via ['tool', 'sv2v', 'task', 'convert', 'var', 'skip_convert'] = True.


### SiliconCompiler 0.32.3 (2025-04-11)

**Major:**

- Added a commandline dashboard to provide quick overview of a run. Accessible by adding .dashboard(type='cli') before calling run(). [Ciprian167]

**Minor:**

- Fixed sc-issue bug that caused the directory to have a partial name.
- Fixed replay.sh generator that caused an invalid bash script to get generated during issue creation.
- Tools:

- openroad: fixed metal fill script bug that prevented the metal fill from executing properly.
- opensta: added build scripts for opensta.
- yosys: added ability use yosys as a frontend for simple design.


### SiliconCompiler 0.32.2 (2025-03-31)

**Minor:**

- Expanded tool builds to support arm architectures, where possible.
- Added tool group descriptions to sc-install -help.
- Tools:

- openroad: added repair design option to repair timing to reduce number of design rule violations.
- yosys: split the FPGA and ASIC synthesis flows.


### SiliconCompiler 0.32.1 (2025-03-13)

**Minor:**

- Added github specific url resolver for downloading artifacts from github.
- Added support to specify step and index for sc-show and sc-dashboard.


### SiliconCompiler 0.32.0 (2025-03-11)

**Major:**

- Changed default behavior of .summary to only print metrics summary, and added .snapshot to generate and display job summary image.
- Moved default verilog/system verilog frontend parser to Slang.

**Minor:**

- Changed examples to use a requirements.txt file for external dependencies.
- Tools:

- openroad: added timing histogram reports.


### SiliconCompiler 0.31.1 (2025-03-06)

**Minor:**

- Fixed tcl manifest to correctly reflect the data types from the schema.
- Added end of install status message to sc-install.
- Tools:

- vpr: updated to v9.0 and added timing metrics extraction.


### SiliconCompiler 0.31.0 (2025-03-03)

**Major:**

- Updated schema to support further advanced packaging.

**Minor:**

- Improved the generation of relay files to provide better insight when debugging.
- Disabled the generation of the html report by default.
- Fixed the handling of environmental variables to ensure they are all set at the start of the node execution.
- Made schema fields pernode and scope enums for easier handling.
- Tools:

- openroad: added global routing metrics recording.
- yosys: added support for loading slang and moosic plugins.


### SiliconCompiler 0.30.0 (2025-02-18)

**Major:**

- Updated schema to support advanced packaging.

**Minor:**

- Added additional feedback during sc-install if user paths are not configured.
- Added support for generating screenshots and displaying .dot files.
- Tools:

- bluespec: fixed support for builtin modules.
- openroad: added macro placement constraints script option via ['tool', 'openroad', 'task', 'macro_placement', 'file', 'rtlmp_constraints'], automatic power grid blockage for pins via ['tool', 'openroad', 'task', 'power_grid', 'file', 'fixed_pin_keepout'].


### SiliconCompiler 0.29.4 (2025-02-06)

**Minor:**

- Added helper function to allow tasks to handle clock information in a uniform method.
- Improved feedback on unsupported platforms during sc-install.
- Tools:

- bambu: updates to better handle platform and clock information.
- openroad: added recover_power option support.
- yosys: switch to use builtin keep_hierarchy to speedup compile times.


### SiliconCompiler 0.29.3 (2025-01-28)

**Major:**

- Added color support to logger to allow for easier identification of warnings and errors.

**Minor:**

- Corrected install scripts for surelog and bambu.
- Fixed task setup order to avoid setting up tasks before the input nodes have been setup.
- Tools:

- slang: added elaboration task.
- yosys: added controls for separator used during flattening via ['tool', 'yosys', 'task', 'syn_asic', 'var', 'hierarchy_separator'].


### SiliconCompiler 0.29.2 (2025-01-16)

**Major:**

- Added gtkwave show task to allow for vcd viewing.
- Removed enablement for conda-eda as this is no longer a supported project.

**Minor:**

- Allow passing a file path to .register_source to make it easier to handle retive path to the current file.
- Tools:

- openroad: added support for mutli-bit flipflop mapping and initial support for scan chain insertion, correct pin ordering from constraints.


### SiliconCompiler 0.29.1 (2025-01-09)

**Major:**

- Added optional optimizer install extra to provide design optimization via google-vizier.

**Minor:**

- Added capability to import flist files via Chip.import_flist
- Added quiet loglevel to limit siliconcompiler logging to just the most critical information.
- Tools:

- openroad: switch to turn on new macro placer by default and correct handling of dont_use based on cell lists.
- yosys: add detailed metrics for cell counts, added support for handling clockgate insertion, simplified library file handling, and updated lec task.
- sta: added check_library task to help verify library setups for asic flows.


### SiliconCompiler 0.29.0 (2024-12-12)

**Major:**

- Update asicflow and openroad driver to utilize smaller tasks. This is a breaking change from the previous implementation, but allows for better flow composability.
- Added ['record', 'pythonversion'] and ['record', 'pythonpackage'] to schema to allow to better environment and provenance tracking.

**Minor:**

- Reworked remote client into single class to allow for better job tracking locally.
- Updated logic for printing package access information to avoid repeating information when possible during a run.
- Tools:

- openroad: rework tasks into smaller tasks, add access to eliminate_dead_logic via ['tool', 'openroad', 'task', 'init_floorplan', 'var', 'remove_dead_logic']
- yosys: fix fpga synthesis to allow for better macro extraction and added ability to map tri-state buffers to asic synthesis.


### SiliconCompiler 0.28.9 (2024-11-27)

**Minor:**

- Added option to limit size of emailed logs based on number of lines.
- Fixed handling of find_files in frontend tools
- Removed automatic error when FPGA is not loaded, as this can be handled by the tool/task drivers.
- Tools:

- vivado: update tool and task drivers to handle v2024.x and cleaned up output filenames.


### SiliconCompiler 0.28.8 (2024-11-20)

**Minor:**

- Fixed dashboard handling of graph metrics when job history contains different sets.
- Tools:

- openroad: added reporting of module cell areas.
- vpr: added options to prevent crashing in designed with dangling ports.


### SiliconCompiler 0.28.7 (2024-11-12)

**Minor:**

- Correct requirements to remove dashboard from python 3.9.7, due to issue in 3.9.7.


### SiliconCompiler 0.28.6 (2024-11-12)

**Minor:**

- Added a support module to call for the manifest summary from python3 -m siliconcompiler.apps.utils.summarize -cfg <file>.
- Removed dashboard from python 3.9.7, due to issue in 3.9.7.
- Tools:

- openroad: updated metrics task to allow for verilog inputs.


### SiliconCompiler 0.28.5 (2024-11-06)

**Major:**

- Added interposer_demo target and interposerflow and drcflow.

**Minor:**

- Added macroarea, padcellarea, and stdcellarea to metrics.
- Added footprint to datasheet in schema.
- Improved handling of sc-show and sc-dashboard when searching for manifests.
- Tools:

- openroad: added metrics task to collect metrics and an rdlroute task to perform floorplan initization and rdlrouting.
- klayout: fixed handling of fill during GDS generation.


### SiliconCompiler 0.28.4 (2024-10-28)

**Major:**

- Added testing support for Python 3.13.

**Minor:**

- Added support to allow dashboard to auto select an open port if not specified.
- Tools:

- openroad: updated minimum version to support database markers and added support to save clock routing.
- surelog: ensure its require list is complete to properly detect changes in inputs.
- yosys: added screenshot task.
- klayout: added drc task to run DRC and convert_drc_db task to convert a klayout DRC database to openroads.
- vpr: added vpr_device_code support.
- magic: added support for uncompressing LEF files.


### SiliconCompiler 0.28.3 (2024-10-14)

**Major:**

- Added sc-install utility application to help install tools on supported platforms.

**Minor:**

- Added rhel8 and rhel9 install scripts.
- Fixed bug in sc-install to account for different operating systems support.
- Ensure generated files .errors and .warnings are included in the metrics files.
- Tools:

- openroad: added options to control optimization (remove_synth_buffers, rsz_skip_setup_repair, and rsz_skip_hold_repair).
- xdm: added install script.


### SiliconCompiler 0.28.2 (2024-10-02)

**Major:**

- Added sc-install utility application to help install tools on supported platforms.

**Minor:**

- Updated .input/.output to support receiving lists of files.


### SiliconCompiler 0.28.1 (2024-09-20)

**Major:**

- Updated lambdapdk to add support for ihp130 and added demo target.

**Minor:**

- Tools:

- openroad: fix rotation handling in floorplanning.
- xyce: updated tool driver implementation.
- xdm: added xyce netlist conversion tool.
- openfpgaloader: removed non-functional implementation of openfpgaloader driver.


### SiliconCompiler 0.28.0 (2024-09-18)

**Major:**

- Updated schema constraints to remove the use of the z-axis.
- Added schematic information to the schema.
- Changed component placement constraints to reference the lower left corner of the instance instead of the center.

**Minor:**

- Tools:

- openroad: updated to account for new placement and rotation constraints.


### SiliconCompiler 0.27.1 (2024-08-28)

**Minor:**

- Fix path handling from commandline.


### SiliconCompiler 0.27.0 (2024-08-28)

**Major:**

- Deprecated .load_target() in favor of .use().
- Added a -use option to the sc cli app to allow for loading of modules.
- Removed the chip input from libraries, pdks, fpga, etc to simplify setup.


### SiliconCompiler 0.26.5 (2024-08-26)

**Major:**

- Moved surelog distribution to a separate package, making SiliconCompiler a pure python distribution.

**Minor:**

- Fixed handling of files and directories from the commandline interface.


### SiliconCompiler 0.26.4 (2024-08-22)

**Minor:**

- Limit schema sections getting imported from libraries to speed up importing.
- Added verilator tool option to dvflow.
- General speedup improvements to schema object.
- Added find_node_file helper function to make accessing files in the node run directory as easy as possible.


### SiliconCompiler 0.26.3 (2024-08-20)

**Major:**

- Removed -generate from sc-issue when creating a sharable testcase.
- Allow for recursive definitions of asic logic and macro libs from imported libraries.

**Minor:**

- smake improved handling of boolean arguments and arguments with default values.
- Corrected .swap_library to correctly swap libraries.


### SiliconCompiler 0.26.2 (2024-08-15)

**Minor:**

- Added portname to pins in schema.
- Allow .swap_library to swap to None when removing a soft-library.
- Tools:

- openroad: fixed max density error to 100% and allow for multiple padring files to be loaded instead of just one.


### SiliconCompiler 0.26.1 (2024-08-02)

**Major:**

- Added smake commandline tool to enable a Makefile like interface to make.py files.
- Removed the need to have local execution for remote jobs.

**Minor:**

- Added additional helper functionality to Library, PDK, and FPGA to better handle package registration.


### SiliconCompiler 0.26.0 (2024-07-30)

**Major:**

- Removed ['option', 'copyall'] from schema.
- Updated ['option', 'loglevel'] to be lower case settings.
- Added ['record', 'toolexitcode] to track the tool exit code during execution.
- Added whitelist of directories to sc-remote to avoid uploaded directories not approved by the user.
- Add support to automatically add soft IP libraries to ['option', 'library'] if specified by the library developer.


### SiliconCompiler 0.25.0 (2024-07-26)

**Major:**

- Removed ['option', 'mode'] and ['option', 'frontend'] from schema.
- Moved flowgraph runtime information into ['record', ...].
- Implemented a dynamic flowgraph that is capable to skipping nodes that are not needed, for example in the case that a design contains VHDL and not verilog, the verilog preprocessing is skipped.
- Split ['input', 'rtl', 'verilog'] into  ['input', 'rtl', 'systemverilog'] and  ['input', 'rtl', 'verilog'] to be better able to tell the file types apart.
- Added support for remote jobs to be marked as rejected.

**Minor:**

- Fixed issue generation for python only tasks.
- Added memory usage collection to python only tasks.
- Prevent Chip.collect() from collecting the user home directory and current build directory.
- Tools:

- slang: added warning and error metrics collection.


### SiliconCompiler 0.24.1 (2024-07-11)

**Major:**

- Added slang tool with a lint task.

**Minor:**

- Corrected reading of previous run manifests to avoid loading manifests of nodes while will need to be rerun.


### SiliconCompiler 0.24.0 (2024-07-09)

**Major:**

- Overhaul of Chip and Schema python APIs.

- Major Chip function changes: renamed register_package_source -> register_source and _getworkdir -> getworkdir.
- Major Schema function changes: renamed _has_field -> has_field, _remove -> remove, and _is_empty -> is_empty.

- Overhaul of Schema keys to clean unused keys and keys with overlapping purposes, major changes:

- Added metrics: drcs, setupskew, holdskew, and inverters.
- Removed the unit section of the Schema.
- Renamed ['option', 'cache'] -> ['option', 'cachedir'].
- Merged behavior of ['option', 'flowcontinue'] and ['option', 'continue'] into ['option', 'continue'].
- Removed ['option', 'relax'], ['option', 'trace'], ['option', 'skipall'], and ['option', 'skipchecks'].

- Add ability for job scheduler to send status update emails via ['option', 'scheduler', 'msgcontact'] and ['option', 'scheduler', 'msgevent'].
- Make resume the default behavior for runs, when a new run is needed ['option', 'clean'] can be set to True to delete the old run and start fresh.
- Add capability to copy an old run and resume from a specific node, allowing users to preserve the original run while avoiding rerunning previous steps.

**Minor:**

- Add option to write_flowgraph to add file annotations to graphs.


### SiliconCompiler 0.23.4 (2024-07-02)

**Major:**

- Add support for docker based running through the use of the ['option', 'scheduler', 'name'] = 'docker'.

**Minor:**

- Ensure that exceptions are printed to log when they occur during runs.
- Added timestamp checking to resume checks when file hashes are not available.
- Implemented totaltime metric to track the total execution time of a run.


### SiliconCompiler 0.23.3 (2024-06-25)

**Minor:**

- Expended daily CI testing to include all examples.
- Cleaned up python requirements to remove unused ones.
- Added verbose and require_reports flags to check_checklists to allow for better control of checklist checking.


### SiliconCompiler 0.23.2 (2024-06-20)

**Minor:**

- Limit logging while generating testcases during run.
- Move sc-leflib to test requirements


### SiliconCompiler 0.23.1 (2024-06-18)

****Major:****

  - Fixed accounting for resources in scheduler.
  - Removed limitation that prevents slurm from being the first node in the execution graph.
  - Added capability to generate standalone testcases on failures to make issue reporting easier.

**Minor:**

- Print stacktraces in logger to allow for better tracking of errors.

- Tools:

  - opensta: fixed thread handling in tool driver and added a library reporting task to collect information about timing libraries.
  - openroad: correct image collecting to avoid generating IR drop on every task.
  - slurm: provide clear error message when slurm is not installed.
  - surelog: correct top module handling in systemverilog mode.


### SiliconCompiler 0.23.0 (2024-06-13)

****Major:****

  - Added support to hash directories.
  - Ensure that resume removes stale data in following nodes during run.
  - Run provides warning if system is running out of memory.
  - Local scheduler updated to prevent executing parallel nodes which exceed the resources available, also controllable via ['option', 'scheduler', 'maxnodes'].
  - Added support for nodes to receive the same file from multiple inputs.
  - Added support to detect changes to the input files and node settings during resume and rerun those nodes.
  - Added support for mixed-frontends.

**Minor:**

- Ensure that global values can be access and modified in strict mode.
- Added build scripts to tools for ubuntu 24.04.
- Added synflow which runs yosys synthesis and opensta timing.
- In strict mode, only files declared by a task driver will be copied into the inputs directory.
- In the event of a tool failure the node will run to completion before erroring out to allow for additional data gathering.
- Renamed export step in asicflow to ensure proper graph handling.

- Tools:

  - opensta: added a standalone tool with timing task.
  - openroad: ensure the SDC file is correctly copied in when screenshot task is part of a flowgraph.


### SiliconCompiler 0.22.0 (2024-05-23)

****Major:****

  - Added support to handle casting to strings in the schema when setting a string key.
  - Added initial support to allow for type changing in the schema via Schema._change_type.
  - Corrected tool module searching to correctly allow for tool modules to be in __init__.py
  - Increased the default densities of all asic targets to 40%.

**Minor:**

- Tools:

  - openroad: added additional support to control what is written out in the export task.
  - verilator: ensure if the user defines the VERILATOR parameter, the tool driver filters it out as as generates an error otherwise.


### SiliconCompiler 0.21.13 (2024-05-15)

**Minor:**

- Tools:

  - openroad: fixed run issues related to placement density selection and missing DRV reporting.


### SiliconCompiler 0.21.12 (2024-05-13)

**Minor:**

- Search for summary image by walking backwards through the executed nodes.
- Sped up schema loading and merging by avoiding unneeded deepcopies.
- Added support to set a list in the schema with a 'set()'
- Tools:

  - ghdl: added support for ['option', 'define'].
  - yosys: added kogge-stone operator mapping to asic flow, removed library merging hack which is no longer needed.
  - openroad: added better support for selecting global placement density, added support to control metrics and reports in tasks via ['tool', 'openroad', 'task', <task>, 'var', 'reports'].
  - netgen: filter errors in stderr to ensure "Note:" are not interpreted as an error.
  - klayout: allow tool to handle fill importing natively from DEF.


### SiliconCompiler 0.21.11 (2024-04-26)

**Minor:**

- Added helper functions to tcl to make accessing schema information easier.
- Added helper functions to allow tools to have consistent behavior around picking from pdk/library/option variables during setup.
- Ensure the remote client downloads the final results from the remote to get any logs and error messages.
- Tools:

  - openroad: fixed default routing via settings.
  - klayout: made hide_layer variable more consistent with klayouts layer information, and added support for .gz file handling in show and screenshotting tasks.


### SiliconCompiler 0.21.10 (2024-04-22)

**Minor:**

- Switch to use templates for generating tool files instead of python print statements to make it easier to maintain.
- Added logic depth to schema metrics.
- Tools:

  - yosys: added support for handling hierarchy selection with globbing, added better handling of library merging to ensure liberty templates are properly copied in.
  - openroad: added support for extracting logic depth of the design and added irdrop extraction to tool driver.


### SiliconCompiler 0.21.9 (2024-04-12)

**Minor:**

- General cleanup of documentation building.
- Tools:

  - yosys: added support for specifying blackbox models via ['tool', 'yosys', 'task', 'syn_asic', 'var', 'blackbox_modules']


### SiliconCompiler 0.21.8 (2024-04-11)

**Minor:**

- Fixed packaging extraction when downloading from github.
- Fixed remote run file retrieval to avoid errors when extracting and moving files.
- Tools:

  - vpr: added support for show and screenshoting tasks.


### SiliconCompiler 0.21.7 (2024-04-02)

**Minor:**

- Update remote code to honor constraints transmitted by the remote runner.
- Add fall back to package locking when file system locking is not available.
- Fixed handling of github artifact packages.
- Added build scripts for ubuntu22.
- Tools:

  - vpr: add reporting images to tool driver, these can be disabled via ['tool', 'vpr', 'task', 'place' or 'route', 'var', 'enable_images'] = 'false'.


### SiliconCompiler 0.21.6 (2024-03-28)

**Minor:**

- Fixed handling of files with codec errors.
- Update package lock file handling to avoid race conditions in parallel flows.
- Tools:

  - yosys: minor code cleanup in FPGA flow.
  - vpr: add support for clock routing.
  - surelog: added wrapper comments in output file for parsing to indicate where segments of code came from.


### SiliconCompiler 0.21.5 (2024-03-21)

**Minor:**

- Added a github data source to handle data from private repositories.
- Tools:

  - vpr: added pin metrics collection for FPGA flows.


### SiliconCompiler 0.21.4 (2024-03-15)

**Minor:**

- Added keys to schema to track FPGA resources.
- Tools:

  - yosys: add metrics collection for FPGA flows.
  - vpr: added metrics collection for FPGA flows.


### SiliconCompiler 0.21.3 (2024-03-13)

**Minor:**

- Tools:

  - openroad: fixed handling of pin constraints
  - yosys: updated to take advantange of native dont_use interfaces


### SiliconCompiler 0.21.2 (2024-03-08)

**Minor:**

- Fix importing of package data from non libraries
- Fix unlocking behavior in schema keys


### SiliconCompiler 0.21.1 (2024-03-07)

**Minor:**

- Fix handling of python module packages on older versions of python.


### SiliconCompiler 0.21.0 (2024-03-07)

**Major:**

- Added support for handling soft libraries in the schema via ['option', 'library'] and updated all frontend task drivers to support these.

**Minor:**

- Ensure that libraries, which import a library, are handled correctly.


### SiliconCompiler 0.20.3 (2024-03-06)

**Minor:**

- Added testing to ensure command line arguments are all checked for functionality and follow the schema pattern.
- Fixed python package lookup when the installed package does not match the name of the distribution.
- Added print controls to command line applications to allow custom arguments to be displayed along with schema values via the key sc_print:.
- Updated the conda environment and added testing to ensure functionality.


### SiliconCompiler 0.20.2 (2024-02-20)

**Minor:**

- Fixed some issued identified by tclint.
- Added helper function to better detect locally installed and editable python packages for package registration.


### SiliconCompiler 0.20.1 (2024-02-12)

**Major:**

- Moved from hosting third party pdks in SiliconCompiler to fully using lamdapdk.
- Added a demonstration target for gf180.

**Minor:**

- Tools:

  - vpr: added support for pin constraints.
  - openroad: added estimated routing congestion to the task image writing and updated fmax metric collection to use OpenROAD directly.


### SiliconCompiler 0.20.0 (2024-02-01)

**Major:**

- Update file path hashing to include package information.

**Minor:**

- Tools:

  - yosys: update FPGA synthesis to better map LUTs and memories.
  - openroad: added option to control CTS with obstruction awareness via  via ['tool', 'openroad', 'task', 'cts', 'var', 'cts_obstruction_aware'].
  - klayout: added operation to be able to rename cells in layout via ['tool', 'klayout', 'task', 'operations', 'var', 'operations', 'rename_cell'].


### SiliconCompiler 0.19.1 (2024-01-24)

**Major:**

- Tools:

  - yosys: updated implementation for FPGA flow to better support flip-flop mapping and hard macro extraction and mapping.

**Minor:**

- Package downloading to ensure GitHub release artifacts can be downloaded from private repositories.


### SiliconCompiler 0.19.0 (2024-01-05)

**Major:**

- Expanded and clarified the datasheet category of the schema.


### SiliconCompiler 0.18.2 (2023-12-18)

**Minor:**

- Fixed resolving paths in package sources when paths contain environmental variables.


### SiliconCompiler 0.18.1 (2023-12-13)

**Minor:**

- Fixed importing of libraries to collect package sources during import.
- Tools:

  - klayout: fixed loading of schema in the presence of other modules named schema.


### SiliconCompiler 0.18.0 (2023-12-04)

**Major:**

- Added ['option', 'cache'] keypath to control the location of the cached data.
- Added support for Python 3.12


### SiliconCompiler 0.17.0 (2023-11-16)

**Major:**

- Added ['package', 'source', '<name>', 'path'] and ['package', 'source', '<name>', 'ref'] to support directly downloading of required data for a design, pdk, library, etc.
- Removed support for $SCPATH and ['option', 'scpath'] in favor of using package sources.

**Minor:**

- Tools:

  - yosys: fixed handling of blackboxes during verilog reading, improved the sdc parsing to better estimate the clock for yosys-abc
  - OpenROAD: fixed PDN file handling to only read files once to avoid errors from redefining the same grids.


### SiliconCompiler 0.16.3 (2023-11-02)

**Minor:**

- Removed unused ['flowgraph', '<graph>', '<step>', '<index>', 'valid'] field from schema.
- Tools:

  - klayout: fixed DEF to GDS generation by ensuring the correct units are used during DEF read in and fixes the stream writing to honor OASIS if requested.
  - OpenROAD: fixed handling of unidirectional layers in routing task and added tasks to support generating OpenRCX parasitic extraction decks.


### SiliconCompiler 0.16.2 (2023-10-13)

**Minor:**

- Added line numbers to the error and warning log files to aid in tracking down the message in the main log.


### SiliconCompiler 0.16.1 (2023-10-11)

**Minor:**

- Fixed incorrect settings when submitting remote jobs.


### SiliconCompiler 0.16.0 (2023-10-09)

**Major:**

- Deprecated support for Python 3.6 and 3.7.
- Added ['option', 'from'], ['option', 'to'], and ['option', 'prune'] to better control the execution of the flowgraph.
- Removed leflib from SilconCompiler and use the standalone implementation provided via pip install sc-leflib.

**Minor:**

- Moved the built in server to use the Schema class for handling its settings.
- Fixed handling of Windows paths when submitting jobs from a Windows machine to a linux runner.
- Corrected the return behavior from the schema .get() to ensure lists are copied instead of being returned by reference.
- Fixed behavior where sc-show would require both step and index to be specified and allowed for directories to be specified as the show target.
- Tools:

  - yosys: Updated to support new ABC interface for passing along dont_use cells.
  - verilator: added support for assertions via ['tool', 'verilator', 'task', 'compile'/'lint', 'var', 'enable_assert']


### SiliconCompiler 0.15.4 (2023-09-25)

**Minor:**

- Added -design to sc-dashboard and ensured common behavior between sc-show and sc-dashboard.
- Disabled sorting of keys in writing of the json schema to preserve the order in the original dictionary.
- Added an alias (siliconcompiler) to the commandline application sc to allow Windows users to be better able to use SiliconCompiler.
- Tools:

  - surelog: Ensure the bundled version is built using a static zlib library for Windows distribution.
  - OpenROAD: Added more controls over the heatmap image generation and to only write heatmaps with data available.


### SiliconCompiler 0.15.3 (2023-09-21)

**Minor:**

- Fixes to sc-show for viewing remote files to ensure it does not attempt to use the file paths from the remote, but instead the local file paths.
- Tools:

  - klayout: Use build technology files and layer display files in show and ensure these are placed into the outputs directory when exporting to a GDS.


### SiliconCompiler 0.15.2 (2023-09-18)

**Minor:**

- Fixes minor bug in the dashboard which prevented the launching the dashboard.
- Ensures all tool output goes through the logger.
- Improved implementation of .valid() to provide faster checking.
- Tools:

  - OpenROAD: fixed bugs in instance creation and pin access function calls. Implemented support for multiple library corners assigned to a single scenario in timing constraints.
  - yosys: Implemented support for multiple library corners assigned to a single scenario in timing constraints.


### SiliconCompiler 0.15.1 (2023-09-08)

**Major:**

- Merged sc-configure into sc-remote to unify the remote interface

**Minor:**

- Fixed missing information in documentation build for flowgraphs.
- Removed call to delete_job on remote jobs, relying on remote to handle cleanup instead.
- Refactored core run functions for better code management.


### SiliconCompiler 0.15.0 (2023-08-31)

**Major:**

- Updated schema to remove unused ['option', 'skipstep'] key and add record to store the remote job id in ['record', 'remoteid'].

**Minor:**

- Added additional error checking and file cleanup to remote run to ensure empty files are not left behind.
- Fixed handling of setting list of tuples in the schema to corrected parse the values.
- Tools:

  - OpenROAD - disabled timing optimizations by default, added support for generating report images in the screenshot task via ['tool', 'openroad', 'task', 'screenshot', 'var', 'include_report_images'].
  - Chisel - added support for handling build.sbt via the input fileset ['input', 'config', 'chisel'].


### SiliconCompiler 0.14.0 (2023-08-21)

**Major:**

- Reworked FPGA to allow for better handling of FPGA parameters in the schema.
- Added missing mechanical parameters to the schema and updating the signal interface naming for clarity.
- Stop execution upon node failures, instead of continuing with repeated failures.

**Minor:**

- Ensure ['option', 'nodisplay'] is set when the environment does not support graphics.
- Added error checking for ['option', 'steplist'] to match current flowgraph.
- Removed physyn step from asicflow.
- Fixed issue when running remote and the submitted files are not updated.
- Tools:

  - OpenROAD - update default value for [..., 'var', 'grt_macro_extension'] to '0' to allow for better routing.
  - verilator - reworked options selection to allow for better control of user selected tool options.
  - yosys - added support for blackboxes in libraries via ['library', <lib>, 'output', 'blackbox', 'verilog'].


### SiliconCompiler 0.13.2 (2023-08-10)

**Major:**

- Added graphs view to dashboard for comparing metrics across runs.
- Added `sc-remote` app for checking server status and interacting with running remote jobs (replaces `sc-ping`).

**Minor:**

- Added checkbox to dashboard for enabling "raw" view of manifest.
- Tools:

  - OpenROAD - made repair_design more verbose (requires updated version), added option to generate design images at end of task via ['tool', 'openroad', 'task', <task>, 'var', 'ord_enable_images'], tweaked pin placement behavior, added SDF file output to export task.
  - surelog - fixed driver to sanitize escape characters in Verilog output, added option to disable write cache via ['tool', 'surelog', 'task', 'parse', 'var', 'disable_write_cache'].
  - klayout - added option to allow missing cells in stream files via ['library', <lib>, 'option', 'var', 'klayout_allow_missing_cell'], added option to set DB units via ['pdk', <pdk>, 'var', 'klayout', 'units', <stackup>].


### SiliconCompiler 0.13.1 (2023-07-21)

**Minor:**

- Improved remote run reliability, including graceful time-outs when server not responding and thread-safety fixes.
- Added ['option', 'libext'] support for Surelog, Verilator, and Icarus.
- Removed dashboard support for Python 3.6.
- Made aesthetic tweaks to dashboard.
- Fixed bundled Surelog on pre-macOS 12.
- Tools:

  - yosys - fixed synthesis strategies.
  - verilator - added multithreading, added FST trace format support.
  - OpenROAD - bumped minimum version to better support IR drop analysis, added additional controls for abstract LEF generation, updated scripts to improve [ORFS](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts) correspondence, fixed to use correct layers for parasitic estimation.


### SiliconCompiler 0.13.0 (2023-07-07)

**Major:**

- Added dashboard to SiliconCompiler to allow better inspection of the run information and added sc-dashboard app to open and display the dashboard.

**Minor:**

- Added ['input', 'constraint', 'upf'] as a recognized format
- Tools:

  - surelog - added support for lowmem option via ['tool', 'surelog', 'task', 'parse', 'var', 'enable_lowmem']


### SiliconCompiler 0.12.3 (2023-06-23)

**Major:**

- Added new flow `screenshotflow` to enable generating high quality stream images via klayout and imagemagick/montage.
- Added new tool `execute` to enable executing the output of a previous task, such as in the case of compiling a binary in one step and executing it in the next.

**Minor:**

- `sc-show` fixed error handling when attempting to how a file without a manifest.
- Added support for pathlib.Path objects when setting file and dir type parameters in the manifest.
- Tools:

  - yosys - fixed marking liberty files dont_use and ensure each library is merged together for ABC. Updated driver to use lower case true/false for ['tool', 'openroad', 'task', '*', 'var'] to be consistent with other tools.
  - verilator - added support for pins-bv via ['tool', 'verilator', 'task', 'compile', 'var', 'pins_bv'] and compile modes via ['tool', 'verilator', 'task', 'compile', 'var', 'mode'].


### SiliconCompiler 0.12.2 (2023-06-14)

**Major:**

- Added additional arguments to `sc-show` to provide access to specific steps and indices in the run.

**Minor:**

- Tools:

  - OpenROAD - added generation of separate timing and power reports in the reports/ directory to provide better insights into the design, added additional parameters to timing repair to enable minimizing total negative slack ['tool', 'openroad', 'task', 'place', 'var', 'rsz_repair_tns'], and added support for RTL-MP for macro placement.
  - yosys - added initial support for hierarchical synthesis via ['tool', 'yosys', 'task', 'syn_asic', 'var', 'hier_threshold'], this is disabled by default while it is still in development.


### SiliconCompiler 0.12.1 (2023-06-07)

**Major:**

- Fixed writing of manifest to preserve values that were previously removed incorrectly.
- Updated recording of ['record', ...] to track tool versions, tool options, task start and end times, and SiliconCompiler version, while preserving control of sensitive records like ['record', 'ipaddr'] with ['option', 'track'].

**Minor:**

- Fixed handling of `sc-issue` to avoid clobbering the user set options and only bundle the required files for a testcase to minimize the size of the file.
- Added error checking for `create_cmdline` to check for invalid arguments.
- Tools:

  - OpenROAD - added support for disallowing one site gaps in detail placement ['tool', 'openroad', 'task', 'place', 'var', 'dpl_disallow_one_site']. Added support for ['option', 'warningoff']
  - surelog - Added support for ['option', 'warningoff']
  - Verilator - Added support for ['option', 'warningoff']


### SiliconCompiler 0.12.0 (2023-05-24)

**Major:**

- Added/updated parameters in ['datasheet'] section of the schema to allow for better capturing of design datasheet.
- Updated Verilator tool driver to support CFLAGS/LDFLAGS and fix linting task.
- Added operations task to klayout to allow for unit operations on GDSs like merging, adding outlines, rotating, etc.
- Added options to `archive()` to support archiving multiple jobs and filtering files to include.

**Minor:**

- Added enforcement of ['option', 'mode'] to ensure it is set for better manifest checking.
- Added per-pin voltage constraints for better support of multiple power/voltage domains, ['constraint', 'timing', scenario, 'voltage', pin].
- Fixed tool drivers to ensure proper use of `find_files()` is not done in `setup()`.
- Added check for permissions error while collecting child process memory statistics.


### SiliconCompiler 0.11.2 (2023-05-15)

**Major:**

- Updated `sc-issue` to generate self-contained testcases to allow for better sharing of testcases.
- Updated klayout tool driver to support map-file option for DEF-GDS export step, and remove need for hard coded options in `.lyt` file in favor of getting values from the schema.

**Minor:**

- Updated loading order to target in commandline interface to ensure schema parameers are set before loading target.
- Error checking for flowgraphs with duplicated edges.
- Added `-ext` to `sc-show` command to control what file is opened when multiple files are available.
- Tools:

  - OpenROAD - added flags to control antenna repairs: ['tool', 'openroad', 'task', 'route', 'var', 'ant_check'] and ['tool', 'openroad', 'task', 'route', 'var', 'ant_repair']; added clock buffer selection option from the library with ['library', lib, 'option', 'openroad_cts_clock_buffer']


### SiliconCompiler 0.11.1 (2023-05-03)

**Major:**

- Revamped documentation for better readability and navigability.

**Minor:**

- Fixed handling when loading schemas from JSON to ensure values are normalized correctly.
- When a tool fails, the last 10 lines of the log is printed when ['option', 'quiet'] is set to aid in debugging.
- Updated server/client to use python tarfile module instead of spawning subprocesses.
- Implemented python linting.
- Tools:

  - OpenROAD - implemented snapping to sites or manufacturing grid for component placement via ['tool', 'openroad', 'task', 'floorplan', 'var', 'ifp_snap_strategy'] and
    added ability to select SDC IO buffer for automatic constraint generation via ['tool', 'openroad', 'task', 'floorplan', 'var', 'sdc_buffer'].
  - yosys - fixed invalid keypath access when logiclib is incorrectly specified.


### SiliconCompiler 0.11.0 (2023-04-17)

**Major:**

- `sc-issue` added as command line application to support sharing runnable testcases.
- Removed the requirement that the initial task of the flowgraph be called 'import' and the final task be called 'export'.
- Fully implemented `.node()` to take in a task module, simplifying the construction of a flowgraph and removing its dependence on ['option', 'scpath'].

**Minor:**

- ['tool', tool, version, 'sbom'] added to be able to track a tools [SBOM](https://en.wikipedia.org/wiki/Software_supply_chain).
- `.hash_files()` updated to honor the 'hash' field for the file parameters.
- `.calc_yield()`, `.calc_area()`, `.calc_dpw()` updated to new schema parameters.


### SiliconCompiler 0.10.2 (2023-04-04)

**Major:**

- Support for Python 3.11
- Building arm64 wheels for surelog

**Minor:**

- Tools:

  - general - deployed docker based CI with automatic tool building and testing
  - klayout - support for OAS stream files via ['tool', 'klayout', 'task', 'export', 'var', 'stream'] = 'oas', better detection of missing layout cells
  - yosys - support for controlling buffer insertion via ['tool', 'yosys', 'task', 'syn_asic', 'var', 'add_buffers'] = 'True'/'False'
  - openroad - correct handling of INF timing in metrics
- Improve memory recording to account for child processes
- General documentation cleanup


### SiliconCompiler 0.10.1 (2023-03-11)

**Major:**

- Adding `._record_metric()` for tool drivers to use when recording metrics to ensure they honor the schema units and record the source of the metric at the same time.

**Minor:**

- Improved error handling and messaging for remote jobs.
- Fixed HTML summary report and PNG summary image not getting rebuilt when calling `.summary()`
- Updated `.summary()` table to display units and format numbers accordingly.


### SiliconCompiler 0.10.0 (2023-03-08)

**Major:**

- Schema overhauled (see [schema documentation](https://docs.siliconcompiler.com/en/stable/reference_manual/schema.html) for details):

  - Added ability to override certain schema parameters on a per-step/index basis.
  - Added step and index to schema access methods.
  - Expanded constraints category to include component and pin placement.
  - Cleaned up parameters which were duplicated in other categories.
  - Implemented ['input', ...] and ['output', ...] filesets along with `.input()` and `.output()` helper functions
- Added tasks to tools prevent step name from getting used for task identification.
- Implemented `.use()` in favor of `.load_pdk()`, `.load_flow()`, etc. to take in Python modules instead of strings.
- Changed libraries, flows, checklists, and pdks to explicitly return a particular class object.
- Generate a summary PNG.
- Removed Floorplanning API.
- Added support for custom macros and scripts in the remote workflow.

**Minor:**

- Updated OpenROAD scripts to support a hierarchical flow.
- Updated Yosys scripts to better support hierarchy.
- Improved auto documentation generation.
- Updated pdk and library settings to provide additional corners where available.
- Updated documentation, including Installation, Quickstart Guide and Tutorials.
- Added Fmax as a first-order metric to the Schema


### SiliconCompiler 0.9.6 (2022-10-03)

**Major:**

- Fixed bug that causes tool setup information to be lost when running a flow in multiple chunks using a steplist.

**Minor:**

- Fixed old schema references in Yosys synthesis strategy scripts.
- Updated error message for missing file requirements.
- Updated OpenROAD scripts to handle multiple LEF files.
- Updated KLayout driver to use batch mode flag and capture more warnings.
- Updated Verilator driver to implement ['option', 'trace], ['option', 'warningoff'], and provide passthroughs for CFLAGS and LDFLAGS.
- Removed support for 'extraopts' passthrough in Verilator driver.
- Updated version of Surelog bundled with wheels distribution.


### SiliconCompiler 0.9.5 (2022-09-12)

**Minor:**

- Schema: Added ['tool', <tool>, 'prescript'/'postscript', <step>, <index>] to support user-supplied pre- and post-scripts for script-based tools.
- Schema: Added ['tool', <tool>, 'file', <step>, <index>] passthrough parameter.
- Added runtime logic to terminate tools that do not exit on their own after a job is interrupted with ctrl-c.
- Fixed KLayout show bugs.
- Fixed issue building SC in editable mode using newer versions of Pip/setuptools.


### SiliconCompiler 0.9.4 (2022-08-25)

**Major:**

- Changed `run()` logic to not reset metrics to zero.

  - `summary()` will only display metrics that have been explicitly set.

**Minor:**

- Schema: Changed ['constraint', <scenario>, 'libcorner'] from scalar to list.
- Added support for --latches option in GHDL driver.
- Added `:keypath:` directive to distributed Sphinx extensions.
- Added reports and final manifest to `archive()` outputs.
- Fixed bug where `job` argument to `find_files()` was not handled properly.
- Fixed pin sizes and PDN vias in Caravel wrapper example.
- Updated flow scripts to support newer version of OpenROAD.
- Updated version of Surelog bundled with wheels distribution.


### SiliconCompiler 0.9.3 (2022-08-01)

**Major:**

- Added basic editing functionality for signoff checklists in HTML report.
- Changed file collection behavior:

  - For local runs, inputs are not copied into import/ at all.
  - For remote runs, inputs are copied into import/0/inputs/ only, not outputs/.
- Implemented ['option', 'entrypoint'], allowing users to specify an alternative top-level.
- Implemented support for "pure Python" tools.

  - A `run()` method inside a tool setup file will be run instead of an executable.

**Minor:**

- Changed `run()` behavior to read metrics from all leaf tasks.
- Fixed implementation of ['option', 'jobincr'].
- Fixed bug causing exception on `summary()` for machines with a default encoding other than UTF-8.
- Fixed logfile reading logic to gracefully handle invalid characters.
- Improved error messages for some common issues.


### SiliconCompiler 0.9.2 (2022-07-08)

**Major:**

- Schema: Added ['option', 'flowcontinue'] to control whether flow continues when a tool reports errors.

  - This used to be controlled by ['tool', <tool>, 'continue'], but this parameter is meant to feed directly into tools (rather than controlling the SC runtime).
- Schema: Added ['option', 'continue'] parameter to control whether errors in the Python API are fatal.

  - The default value makes errors fatal, setting this parameter to True reverts to the old behavior.
- Added VPR-based FPGA bitstream generation flow.
- Added logic to set errors and warnings metrics based on ['tool', <tool>, 'regex', ...] matches. This reduces tool driver boilerplate and makes the metrics consistent with the generated regex match files.

**Minor:**

- Changed default technology target for `sc` app.
- Changed KLayout show script to always use a dark background.
- Changed `check_manifest()` to allow tool tasks to have multiple inputs (behaving as if they were merged with a "join" builtin).
- Changed `check_manifest()` to return True on success rather than 0 (the previous behavior didn't match the documentation).
- Changed Yosys and OpenROAD tool drivers to make them easier to use in flows with alternate step names.
- Changed GHDL tool driver to allow additional CLI options via ['tool', <tool>, 'var', ..., 'extraopts'].
- Removed return codes from `post_process()`.


### SiliconCompiler 0.9.1 (2022-06-21)

**Major:**

- Added input filetype inference based on file extension (restores functionality lost in 0.9.0).
- Added manifest tree viewer to HTML report.
- Added simulator exe compilation support to Verilator.
- Improved TCL manifest generation:

  - Fixed escaping of special characters and whitespace.
  - Fixed insertion of "$env" in filepaths.
  - Changed tuple printing to be TCL list instead of tuple-like string.

**Minor:**

- Schema: Added tool CLI arguments to ['record', ...] schema.
- Changed create_cmdline() switchlist parameter to accept switch names as specified on command line.
- Changed setup module docs generator to be packaged with SC.
- Changed HTML report to be self-contained.
- Fixed CSV manifest generation.


### SiliconCompiler 0.9.0 (2022-05-19)

**Major:**

- Schema: Reorganized entire schema! Changes summarized below:

  - Cleaned and consolidated top-level organization, most parameters are now nested.
  - Moved build configuration options underneath ['option', ...].
  - Added ['output', ...] to store pointers to flow outputs.
  - Added ['model', ...] to store pointers to design abstractions (timing libraries, layouts, etc).
  - Added ['datasheet', ...] to store information about design's interface.
  - Added ['unit', ...]  to store user driven SI units specification (temp,voltage, etc)
  - Renamed ['eda', ...] to ['tool', ...]
  - Renamed ['mcmm', ...] to ['constraint', ...]
  - Replaced ['source'], ['constraint'], and ['read', ...] with more flexible ['input', <filetype>] to supply input files.
  - Added support for storing multiple PDKs in schema and selecting which one to use for run (analogous to flows).
  - Change ['flowgraph'] to support modular flow composition
  - Added support for package management ['depgrah'].
  - Added checklist support.
  - Removed special ['library', ...] keypaths. All libraries are now created as Chip objects, and have their full config imported into a parent chip's schema.
- Added 'sup' packaging utility
- Added ability to configure stdout and stderr redirection on a per-tool basis (thanks to @suppamax for implementing).
- Added flexible tool version checking based on PEP-440 standard, now enabled by default.
- Added 'clean' feature for cleaning up intermediate tool outputs.
- Added 'resume' feature for restarting failed flows (for debugging).
- Added automatic capture of peak memory usage (adds dependency on [psutil](https://psutil.readthedocs.io/en/latest/)).
- Changed ['design'] to be a required parameter for instantiating a Chip.
- Changed error behavior to consistently raise exceptions rather than exit.
- Removed tool script copy feature, so now all EDA scripts are run from the reference directory.

**Minor:**

- Schema: Added ability to store per-parameter designer notes.
- Added offline wheels distribution.
- Added `read_lef()` function to help with PDK bring-up.
- Added environment variables to replay scripts.
- Added LVS/DRC signoff flow and top-level GDS stream out flow.
- Added native support for Sky130 I/O library, along with Heartbeat + padring example.
- Changed internals to minimize SC performance overhead with large flowgraphs.
- Changed task runtime tracking to distinguish between time spent in tool and total time.
- Fixed breakpoints to work more consistently across tools.

Note: Since there was no public release of version 0.8.0, this list summarizes all changes since 0.7.0.


### SiliconCompiler 0.7.0 (2022-03-02)

**Major:**

- Schema: Added ability to specify environment variables on a per-tool, per-task basis.
- Schema: Added per-tool 'techmap' parameter to library schema.
- Added browser-viewable report generation to core.summary().

**Minor:**

- Schema: Added filetypes to library schema: 'def', 'gerber', 'netlist', 'model' category.
- Schema: Added 'stackup' key to library lef/gds parameters.
- Schema: Changed 'pdk' and 'stackup' library parameters to lists.
- Schema: Added 'dir' passthrough to library schema.
- Schema: Added 'nodisplay' option to schema to better support headless jobs.
- Schema: Added 'licensefile' to package parameters to support non-standard licenses.
- Schema: Added 'gerber' to read schema.
- Schema: Added several cell categories to library schema.
- Changed how PDK-specific Yosys and OpenROAD parameters are driven to avoid hardcoding process info in tool drivers.
- Fixed step ordering bug in core.summary().
- Fixed bug with how 'arg', 'index' is handled.
- Fixed small bugs in automatic documentation generation.
- Added core.check_filepaths() helper.


### SiliconCompiler 0.6.0 (2022-02-11)

**Major:**

- Schema: Added 'flow' key to flowgraph to enable multi-flow targets.
- Schema: Added 'flow' parameter to enable selection between flows in flowgraph.
- Schema: Changed '_' separated tuple target to a single 'module' load target.
- Schema: Added 'regex' for grep like functionality.
- Schema: Changed metal grid to use PDK metal name as the major key.
- Schema: Added 'tool' key to PDK settings to avoid tool file conflicts.
- Schema: Added 'units' parameter to enable tech agnostic SDC.
- Schema: Added ability to specify tricky apr setup files on a per tool basis (tracks, taps, vias, antenna, etc).
- Schema: Added checklist functionality
- Added core.grep function
- Added core.check_logfile function to core API to emulate grep behavior
- Added core.load_{target, flow, lib, pdk} functions to core API in place of target()
- Added asap7 target
- Added docker support for basic RTL2GDS tool chain
- Removed core.target() function

**Minor:**

- Schema: Changed lib 'driver' to move into cells (consistency)
- Schema: Added site symmetry to avoid full lef parser.
- Schema: Changed tool version switch to a list
- Schema: Changed 'asic', 'targetlib' to 'asic', 'logiclib' for clarity.
- Schema: Changed 'eda, 'report' parameter guideline to always use 'metric' as keyword
- Schema: Added -skip_check option to speed up new target bringup
- Schema: Added -skip_step option to enable skipping specific steps
- Schema: Added 'pdk', ['file', 'directory', 'variable'] parameters to enable tool-specific PDK setups.
- Schema: Changed cell types to be hardcoded (tapcell, buf, clkbuf, etc) to avoid fragmentation.


### SiliconCompiler 0.4.1 (2022-01-06)

**Minor:**

- Fix bug in Yosys parameter requirements spec that made check_manifest() too strict


### SiliconCompiler 0.4.0 (2022-01-05)

**Major:**

- Schema: Add 'tool' key to PDK fields
- Schema: Remove unneeded 'record' keys
- Implement automatic record-keeping
- Implement checks that flow make sense in terms of file I/O and that required files resolve
- Allow importing multiple files with the same basename

**Minor:**

- Automatically configure KLayout path on macOS
- Allow importing multiple files with the same basename
- Implement -I CLI switch for include directory


### SiliconCompiler 0.3.1 (2021-12-21)

**Minor:**

- Fix sc-show on Windows.


### SiliconCompiler 0.3.0 (2021-12-21)

**Major:**

- Schema: add 'read' section.
- Schema: Add alternate frontend support.

**Minor:**

- Fix old version of Surelog bundled with wheels


### SiliconCompiler 0.1.1 (2021-12-08)

**Minor:**

- Fix: Prevent sc-show crash when PDK files are not found.
- Fix: Ensure sc-show can find KLayout executable on Windows


### SiliconCompiler 0.1.0 (2021-12-03)

**Major:**

- First public release!!!


---

Source: https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html

## Schema Changes

All notable changes to the SiliconCompiler **schema version** (`schemaversion`)
are documented here. The schema version follows [semver](https://semver.org).

The current version is defined in `siliconcompiler/schema/_metadata.py`. It lived in
`schema_cfg.py` (as `SCHEMA_VERSION`) prior to 0.52.0, and moved to
`schema/_metadata.py` during the 0.51.5 → 0.52.0 transition.

Entries describe the actual schema/parameter changes for each version (derived
from the code diffs, not the commit messages). Dates are the git commit dates of
the version bump. Version numbering was not strictly linear during early
development, so a few dates are non-monotonic relative to the semver ordering.


### 0.57.2 -- 2026-09-28

- Changed `tool,<tool>,task,<task>,require` from `[str]` to `{str}` so
  duplicate keypaths added via `Task.add_required_key()` are deduplicated by
  the schema itself rather than accumulating as repeated list entries.


### 0.57.1 -- 2026-08-10

- Added `csv` to the accepted values of `tool,<tool>,task,<task>,format`
  (`<json,tcl,yaml>` → `<csv,json,tcl,yaml>`). The CSV writer already existed in
  `write_task_manifest` but could never be selected through the schema.


### 0.57.0 -- 2026-07-21

- Removed the standalone `Schematic` schema class (`schematic,*` section) and its
  top-level API; schematic capture is a design-entry concern that belongs outside
  the build tool.


### 0.56.0 -- 2026-07-07

- Added value ranges/limits to numeric schema types via a new `NodeRangeType`
  and `int<...>`/`float<...>` type syntax (e.g. `int<0..100>`, `float<0.0..1.0>`,
  open-ended `int<0..>`); `str<...>` is treated as an enum. Ranges are validated
  on set and encoded into the serialized type string.


### 0.55.0 -- 2026-07-01

- Changed the global-value key from `'global'` to `'*'` to avoid name conflicts,
  with legacy read support for older manifests.


### 0.54.0 -- 2026-01-09

- Removed the standalone library schema; `LibrarySchema`/`ToolLibrarySchema` now
  derive from `Design` -- everything is a design.


### 0.53.1 -- 2026-01-06

- Added the `physicalonly` cell type to ASIC library cells to better support
  LVS/LEC netlist generation.


### 0.53.0 -- 2025-12-01

- Separated timing **mode** information from **scenario** information in the
  constraints schema to make multi-mode timing easier to work with.


### 0.52.1 -- 2025-10-31

- Moved libraries into a separate class to avoid extra dependency evaluations.


### 0.52.0 -- 2025-10-01

- Renamed the `package` field to `dataroot` throughout path parameters and the
  `find_files`/`check_filepaths` APIs.
- Version definition moved from `schema_cfg.py` to `schema/_metadata.py`.


### 0.51.5 -- 2025-08-29

- Removed the legacy `schema_cfg.py` setup and updated the schema version flag;
  no substantive parameter change.


### 0.51.4 -- 2025-06-02

- Switched the tool schema import to a temporary placeholder (`ToolSchemaTmp`)
  during the class migration; records now capture microsecond-resolution
  start/end times.


### 0.51.3 -- 2025-05-16

- Replaced inline FPGA and PDK parameter definitions with insertion of the
  separate `FPGASchema` and `PDKSchema` modules; simplified the schematic/fpga
  section signatures.


### 0.51.2 -- 2025-05-13

- Removed the `schema_task()` function and all task-related definitions; tool
  task definitions moved to a dedicated `ToolSchema` class, with scope fixes.


### 0.51.1 -- 2025-05-09

- Removed all PDK-related definitions from `schema_cfg.py` (migrated to the
  separate `PDKSchema` module); fixed flowgraph scope.


### 0.51.0 -- 2025-05-05

- Major architecture refactor: moved from the flat `scparam` dictionary model to
  a `Parameter`-based object model with `EditableSchema`, `Scope`, and `PerNode`
  enums. PDK, FPGA, and tool definitions began migrating out to separate schema
  modules.


### 0.50.0 -- 2025-02-21

- Reduced `constraint,pin` dimensions from three (width, length, height) to two
  (width, height) -- a pin sits on a 2D surface.
- Renamed `constraint,component` `height` to `zheight`; made component
  `rotation` per-node; simplified the `substrate` reference.


### 0.49.0 -- 2025-02-10

- Advanced-packaging update: `datasheet,package,<name>,footprint` changed from
  string to `file`; added a `3dmodel` file parameter.
- Added `constraint,component,<name>,substrate` and `side`
  (enum: left/right/front/back/top/bottom); renamed component `height` to
  `zheight`.
- Reworked package pin metrics (e.g. `pitch` → `pinpitch`) and pin signal
  mapping.


### 0.48.6 -- 2024-12-20

- Added the `quiet` value to the `option,loglevel` enum.


### 0.48.5 -- 2024-12-09

- Added `record,pythonversion` and `record,pythonpackage` (list of installed
  packages); made `record,remoteid` non-per-node.


### 0.48.4 -- 2024-11-05

- Added metrics `macroarea`, `padcellarea`, and `stdcellarea`.


### 0.48.3 -- 2024-11-05

- Added back the `datasheet,package,<name>,footprint` parameter (as a `file`).
- Corrected version numbering: adding schema parameters only bumps the patch
  digit (`0.0.X`). This reverted an erroneous 0.49.0 bump made on 2024-11-04.


### 0.48.2 -- 2024-09-18

- Added `defvalue='R0'` to the component rotation parameter and reorganized its
  enum, with expanded documentation.


### 0.48.1 -- 2024-09-17

- Added `unit='nm'` to `pdk,<name>,node`; changed
  `datasheet,package,pin,<pinnumber>,loc` unit from `mm` to `um`; used keypaths
  to cross-link keys in the docs.


### 0.48.0 -- 2024-09-15

- Restructured the schematic parameters into a hierarchical form.
- Changed `constraint,component,<name>,rotation` from float to an 18-value enum
  (R0/R90/R180/R270 plus mirror variants); removed the separate `flip`
  parameter; moved origin handling to `datasheet,package,<name>,anchor`.


### 0.47.0 -- 2024-09-06

- Added a schematic/netlist section: `component,<name>,model`, `pin,<name>,dir`,
  `net,<name>,connect`, plus `hierchar` and `buschar`.


### 0.46.0 -- 2024-09-06

- Added `constraint,component,<name>,origin`, default `(0.0, 0.0)` -- supports
  changing the default origin from center to the lower-left corner for packaging
  and board design.


### 0.45.1 -- 2024-09-05

- Cleaned up short-help strings and capitalization (no substantive parameter
  change).


### 0.45.0 -- 2024-09-04

- Restructured datasheet package pins into a hierarchical
  `pin,<pinnumber>,{shape,width,length,loc,name}` form, replacing the flat
  `pinshape`/`pinwidth`/`pinlength`/`pinloc`/`netname`/`portname` keys.


### 0.44.5 -- 2024-09-03

- Changed `constraint,component,<name>,placement` and
  `constraint,pin,<name>,placement` from `(float,float,float)` to
  `(float,float)`.


### 0.44.4 -- 2024-08-27

- Removed the `option,target` parameter (targets now loaded by the app).


### 0.44.3 -- 2024-08-09

- Added `datasheet,package,<name>,portname` (net name is not always the port
  name); added `copy=True` to file/dir parameters (tool task file/dir/scripts
  and `option` file/dir/idir/ydir/vlib).


### 0.44.2 -- 2024-07-29

- Lowercased the `option,loglevel` enum
  (`info/warning/error/critical/debug`, default `info`), separating it from
  Python logger levels.


### 0.44.1 -- 2024-07-26

- Added `record,toolexitcode` (per-node int); removed `option,copyall`.


### 0.44.0 -- 2024-07-25

- Renamed `record,exitstatus` to `record,status` and expanded its enum with
  `queued`, `running`, and `timeout` states.


### 0.43.1 -- 2024-07-23

- Removed `option,frontend`; made `option,entrypoint` per-node optional.


### 0.43.0 -- 2024-07-22

- Moved runtime info into the record: removed flowgraph `status`/`select`; added
  `record,exitstatus` (enum) and `record,inputnode` (`[(str,str)]`, per-node).


### 0.42.7 -- 2024-07-19

- Changed the `require` default from `None` to `False` across parameters and
  dropped the mode-specific `require` markers (`'all'`/`'asic'`/`'fpga'`);
  removed `option,mode`.


### 0.42.6 -- 2024-07-09

- Help-text/shorthelp refinements for datasheet package pin parameters (no
  substantive parameter change).


### 0.42.5 -- 2024-07-08

- Added `output` to the task `stdout`/`stderr` destination enum
  (`log/output/none`); removed the `jobinput` key.


### 0.42.4 -- 2024-07-08

- Removed FPGA resource/board parameters and several PDK parameters
  (`thickness`, `density`); combined `hscribe`/`vscribe` into `scribe`
  (`(float,float)`); renamed PDK `directory` → `dir`; restructured PDK `doc` by
  `doctype`; removed several option/task flags; removed ASIC cell types
  `delay`/`clkdelay`/`clkinv`/`clkicg`.


### 0.42.3 -- 2024-07-08

- Changed `option,scheduler,msgevent` from a string to an enum list
  (`all/summary/begin/end/timeout/fail`).


### 0.42.2 -- 2024-07-08

- Removed the task `keep` parameter and `option,resume`; changed `option,clean`
  semantics to "start a job from the beginning".


### 0.42.1 -- 2024-07-07

- Removed `option,showtool,<filetype>`.


### 0.42.0 -- 2024-07-07

- Breaking cleanup: removed the `unit,*` section, `pdk,<name>,lambda`,
  `option,uselambda`, flowgraph `timeout`, and assorted FPGA/PDK/option
  parameters; renamed `option,cache` → `option,cachedir` and PDK `directory` →
  `dir`.


### 0.41.1 -- 2024-07-05

- Added metrics `drcs`, `holdskew`, `setupskew`, and `inverters` (split from
  `buffers`); removed `dozepower`, `idlepower`, and `sleeppower`.


### 0.41.0 -- 2024-07-03

- Restructured `datasheet,package` to be indexed by package `name`, merging the
  standard and generation parameters and folding per-pin package data under the
  package hierarchy.


### 0.40.8 -- 2024-07-03

- Merged the datasheet standard and generation parameters; removed
  `datasheet,partnumber`, `datasheet,abstraction`, and `datasheet,io,<name>,gen`;
  refined the IO `arch` enum.


### 0.40.7 -- 2024-07-02

- Added `docker` to the `option,scheduler,name` enum (docker-based running).


### 0.40.6 -- 2024-05-30

- Renamed `option,scheduler,maxconcurrency` → `option,scheduler,maxnodes`; added
  directory-hash (`filehash`) support.


### 0.40.5 -- 2024-05-28

- Added `option,scheduler,maxconcurrency` (max concurrent local jobs).


### 0.40.4 -- 2024-04-21

- Added the `metric,logicdepth` parameter.


### 0.40.3 -- 2024-03-14

- Added FPGA resource parameters `fpga,<partname>,resources,{registers,dsps,brams}`.


### 0.40.2 -- 2024-03-05

- Added `option,library` (per-node list) for soft libraries.


### 0.40.1 -- 2024-02-28

- Added datasheet top-level parameters (`partnumber`, `type`, `series`,
  `manufacturer`, `grade`, `qual`, `trl`, `status`, `fmax`, `ops`, `iobw`,
  `iocount`, `ram`, `peakpower`, etc.); corrected several switch help strings.


### 0.40.0 -- 2023-12-18

- First standardized datasheet metrics: restructured `datasheet` into
  hierarchical `processor,<name>,*`, `io,<name>,*`, `fpga,<name>,*`, and
  `package,<name>,*` (with `pincount`, `drawing`) namespaces.


### 0.39.0 -- 2023-11-17

- Added `option,cache`; removed `option,scpath`; reworked the package parameters
  (`package,version/description/keyword/license/organization`, `package,doc,*`,
  contact fields).


### 0.38.0 -- 2023-11-02

- Added a `dependency,<dep>,{path,commitid,name}` section (later reconciled with
  the package schema).


### 0.37.2 -- 2023-11-02

- Removed `option,registry` and the entire `package,*` section (name, version,
  description, keyword, doc, license, organization, contact, ...).


### 0.37.1 -- 2023-10-26

- Removed the flowgraph node `valid` flag; added `option,prune` (`[(str,str)]`).


### 0.37.0 -- 2023-09-20

- Replaced `option,steplist`/`option,skipstep`/`option,indexlist` with
  `option,from` and `option,to`.


### 0.36.0 -- 2023-08-30

- Moved job IDs into the core schema and removed the `skipstep` option;
  restructured FPGA `<partname>` (added `file,*`/`var,*`) and datasheet
  package/pin parameters.


### 0.35.0 -- 2023-08-03

- Cosmetic/FPGA-prep changes: removed `fpga,arch`; added `fpga,<family>,lutsize`;
  moved FPGA `vendor` under `<partname>`; added `record,remoteid`.


### 0.34.7 -- 2023-08-09

- Reworked datasheet pin/mechanical parameters: renamed
  `datasheet,pin,*,signal` ↔ `interface`, changed `map` to be indexed by `<bump>`
  as `(float,float)` in `um`.


### 0.34.6 -- 2023-08-08

- Fixed examples in the record portion of the schema (no substantive parameter
  change).


### 0.34.5 -- 2023-07-29

- Fixed a typo in a switch flag (no substantive parameter change).


### 0.34.4 -- 2023-07-27

- Fixed typos in schema help strings (no substantive parameter change).


### 0.34.3 -- 2023-06-13

- Fixed a `constraint,net,<name>,shield` switch-name typo (documentation only).


### 0.34.2 -- 2023-06-09

- Changed `tool,<tool>,format` to an enum (`json`/`tcl`/`yaml`).


### 0.34.1 -- 2023-06-09

- Fixed CLI switch quoting (no substantive parameter change).


### 0.34.0 -- 2023-05-19

- Restructured node value storage (nested `default,default,value`); added
  file-node metadata (`date`, `author`, `filehash`); changed timing `voltage`
  to per-pin (`constraint,timing,<scenario>,voltage,<pin>`); changed
  `option,credentials` from `[file]` to `file`.


### 0.33.0 -- 2023-05-17

- Added `tool,task,dir` (user-supplied directories mapped to keys); added pin
  voltage support to constraints; made the credentials file a single file.


### 0.32.0 -- 2023-04-12

- Whitespace/formatting cleanup (no substantive parameter change).


### 0.31.0 -- 2023-04-01

- Added SBOM traceability and made scheduler options
  (`cores/memory/queue/defer/options/msgevent/msgcontact`) per-node optional.


### 0.30.0 -- 2023-04-07

- Added a copy flag to directory parameters.


### 0.29.0 -- 2023-03-30

- Added task-module support; improved switch handling and help strings.


### 0.28.0 -- 2023-03-06

- Added the `metric,fmax` parameter.


### 0.27.0 -- 2023-02-24

- Removed the `signature` field from parameter metadata; renamed `nodefield` to
  `node`.


### 0.26.0 -- 2023-02-21

- Put the global value into the same dict as per-node values: removed the
  separate `value`/`set`/`filehash`/`date`/`author` fields, renamed `nodevalue`
  to `nodefield`.


### 0.25.0 -- 2023-02-20

- Added `option,strict`; made many scheduler/constraint parameters per-node
  optional.


### 0.24.0 -- 2023-02-13

- Added back the `option,dir` parameter.


### 0.23.0 -- 2023-02-10

- Removed step/index from task parameters (warningoff, continue, regex, option,
  var, env, file, input, output, stdout, stderr, require, report, refdir,
  script, prescript, postscript, keep); made `tool` path/version/licenseserver
  per-node optional.


### 0.22.0 -- 2023-02-02

- Flattened metrics from `metric,<step>,<index>,<item>` to `metric,<item>` with
  `pernode='required'`; removed `arg,pdk` and `arg,flow`.


### 0.21.0 -- 2023-01-31

- Renamed `option,bkpt` to `option,breakpoint`.


### 0.20.0 -- 2023-01-27

- Replaced `option,jobscheduler`/`msgevent`/`msgcontact` with an
  `option,scheduler,*` subgroup (`name/cores/memory/queue/defer/options/msgevent/msgcontact`); added `option,timeout`.


### 0.19.0 -- 2023-01-27

- Added `option,nice`, `option,var,<key>`, `option,file,<key>`; removed the
  per-tool `asic,{file,dir,var}` parameters.


### 0.18.0 -- 2023-01-26

- Removed the `server,*` section (cores, memory, queue, nice, timeout,
  interactive, defer).


### 0.17.0 -- 2023-01-25

- Added job-scheduler management via a `server,*` section
  (cores/memory/queue/nice/timeout/interactive/defer); removed `option,nice`.


### 0.16.1 -- 2023-01-21

- Removed the PDK layer `grid` section and `asic` layer/footprint parameters
  (`rclayer`, `vpinlayer`, `hpinlayer`, `pgmetal`, footprint alias/symmetry/size);
  added `asic,site,<libarch>` and `option,nice`.


### 0.15.0 -- 2023-01-25

- Added the `enum` type and switched mode/loglevel/status to enums; added
  `pdk,<name>,{minlayer,maxlayer},<stackup>`, `option,uselambda`,
  `constraint,pin,<name>,{side,order}`, and several
  `constraint,net,<name>,*` parameters.


### 0.14.0 -- 2023-01-22

- Moved ASIC constraints into the common `constraint` group (renaming
  `diearea` → `outline`, adding `corearea`/`coremargin`/`density`/`aspectratio`);
  made net `maxlayer`/`minlayer` per-net.


### 0.13.0 -- 2023-01-22

- Moved `lambda` from top-level into `pdk,<name>,lambda`; removed duplicate
  `asic,pdk`/`asic,stackup` and assorted `asic` max* parameters; moved stackup to
  options.


### 0.12.0 -- 2023-01-18

- Added `datasheet,<design>,footprint` and `flowgraph,<flow>,<step>,<index>,task`.


### 0.11.0 -- 2023-01-15

- Added the tool/task split (`schema_task()` hierarchy); reworked input/output
  parameters to `[item, fileset, filetype]`; removed the early
  `lambda`/`schematic`/`layout` sections.


### 0.10.0 -- 2023-01-01

- Added an initial unified layout/schematic structure (`schematic,*` and
  `layout,*` groups covering components, pins, nets, outline, footprint) plus a
  top-level `lambda`.


### 0.9.0 -- 2022-08-31

- Initial schema object.


---

Source: https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/machine_readable.html

## Machine-readable documentation

Three files are published alongside this site for programs rather than people:
editor tooling, validators, scripts, and code assistants answering questions about
SiliconCompiler. They hold the same content as the pages you are reading, in forms
that do not require parsing HTML.

| File | Format | Contents |
| --- | --- | --- |
| [llms.txt](https://docs.siliconcompiler.com/en/latest/llms.txt) | Markdown | The current API, the names that no longer exist, where a new module belongs, and a linked index of every page on this site. Small enough to fetch speculatively. Follows the [llmstxt.org](https://llmstxt.org) convention. |
| [llms-full.txt](https://docs.siliconcompiler.com/en/latest/llms-full.txt) | Markdown | The full text of every hand-written page on this site in one file, with cross-references resolved to absolute URLs. The generated reference is linked rather than included. |
| [schema.json](https://docs.siliconcompiler.com/en/latest/schema.json) | JSON | Every parameter of every documented schema class, keyed by [keypath](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-keypath). |


### Versions

The files are generated during each documentation build, so the copy served from
a version describes that version:

```text
https://docs.siliconcompiler.com/en/stable/llms.txt     # current release
https://docs.siliconcompiler.com/en/latest/llms.txt     # development branch
https://docs.siliconcompiler.com/en/v0.38.3/llms.txt    # a specific release
```

This matters more for SiliconCompiler than it would for most projects: the API
changed substantially at v0.35.0, so a file describing "the current API" is only
meaningful next to a version. Prefer `stable` unless you specifically want
unreleased behaviour.


### The schema dump

`schema.json` is organised by class, then by keypath, with keypath segments
joined by commas -- the same notation as the [Schema Reference](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#schema) and
as a `get()` call. `default` appears as a literal segment where the schema
accepts an arbitrary name:

```json
{
  "sc_version": "0.38.3",
  "schemaversion": "0.57.1",
  "classes": {
    "ASIC": {
      "description": "The ASIC class extends the base Project class ...",
      "parameters": {
        "option,fileset": {
          "type": "[str]",
          "scope": "global",
          "pernode": "never",
          "shorthelp": "Option: Selected design filesets",
          "help": "List of filesets to use from the selected design library",
          "defvalue": []
        },
        "tool,default,task,default,warningoff": {"...": "..."}
      }
    }
  }
}
```

The classes covered are the ones documented in the [Schema Reference](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#schema), and the per-parameter fields are the ones defined at the top of that
page. The per-node value tree is omitted, because it describes one populated
project rather than the schema; `defvalue` carries the default.

Two version numbers appear at the top level, and they are independent:
`sc_version` is the package release and `schemaversion` is the schema's own
semver, which is what a [manifest](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-manifest) records. [Schema Changes](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#schema-changelog) tracks the latter.

> **Note**
> These files are a convenience, not a stable API. The content tracks the
> documentation, so it changes when the documentation changes. If you are
> building something that depends on the schema long-term, pin a version in the
> URL and read [Schema Changes](https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/schema_changelog.html#schema-changelog) before moving.


---

Source: https://docs.siliconcompiler.com/en/latest/reference_manual/appendix/dashboard_how_to_guide.html

## Dashboard

To start, ensure you install the dashboard dependencies by running:

```bash
pip install siliconcompiler[dashboard]
```

At this point, you should have the dashboard in your environment.

Then, run the command:

```bash
python3 -m siliconcompiler.apps.utils.dashboard -cfg <path to manifest>
```

You can specify the port by adding a port flag.
If you don't provide one, the port will default an auto selected one or to 8501:

```bash
python3 -m siliconcompiler.apps.utils.dashboard -cfg <path to manifest> -port <port number>
```

And/or you can include extra projects by adding one or multiple `-graph_cfg` flags.
The name of the [manifest](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-manifest) is optional.
If you don't provide one, the name will default to the path to manifest:

```bash
python3 -m siliconcompiler.apps.utils.dashboard -cfg <path to manifest> -graph_cfg <manifest name> <path to manifest> -graph_cfg <manifest name> <path to manifest>
```


### Header

In the header, you can select any of the projects that are part of the history of the project loaded in and any of the other projects loaded in through the `-graph_cfg` flag (see arrow below).


### Metrics Tab

You will load into the metrics tab similar to the one below upon running [dashboard](https://docs.siliconcompiler.com/en/latest/reference_manual/apps.html#app-dashboard).


#### Metrics Section

The metrics section displays an overview of each value for each metric tracked for each node.
Click "Transpose" to switch the axes (arrow A in image below).

You may use the "Select Parameter" expander to specify certain nodes and/or metrics (arrow C and D in image below).
Click "Apply" to make those changes (arrow B in image below). If you don't specify any nodes and/or metrics,
all of the nodes and/or metrics will be shown.


#### Flowgraph Section

The [flowgraph](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-flowgraph) section displays the data dependencies for each
[node](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-flowgraph-node).
Nodes are color-coded based on
their task status.
Green means task status is a success, red means task status is a failure,
and yellow means task status is pending.
Currently, task status should never be yellow because you
cannot view the dashboard while the build is not done.
This is functionality we hope to add.
Paths that are part of the 'winning path' will have bolded edges.

To activate the flowgraph, click on it once.
This allows you to interact with the flowgraph.
You can drag nodes around, pan the view, and zoom in/out.
You can also click nodes to select
them for the Node Information Section.
You can see a node is selected by it becoming bolded
(in the image below, that's floorplan0). Double clicking nodes will send you to a blank html page.
We are aware of this bug.


#### Node Information Section

Below is the node information section.
It consists of three subsections - node metrics, node details, and node files.

You can select a node using the "Select Node" expander as seen with arrow's A and B below.
Click "Apply" to make the change.


##### Node Metrics Subsection

The node metrics subsection consists of all of not `None` values recorded for each of the metrics recorded for the selected node.


##### Node Details Subsection

The node details subsection consists of all of the characteristics about this node that are not reflected in the metrics section.


##### Node Files Subsection

The node files subsection consists of all of the files for a given node that are in the build directory.

Selecting a node will display a list of the metrics that the file informs below the file tree.
In the picture below, no metrics can be found in the floorplan.log file.


### File Viewer Tab

The selected node you clicked in the Node Information Section will appear here.
The header is the name of the file selected.
You can download the file by clicking the download button (as by the arrow in the image below).

If no file is selected, the error message below will be displayed telling you to select a file first.


### Manifest Tab

The next tab you can select is the manifest tab.
This displays the manifest after it has been filtered through to make it more readable.
More specifically, if the [pernode](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#term-pernode) value of the leaf of the Schema is [pernode](https://docs.siliconcompiler.com/en/latest/reference_manual/schema.html#term-pernode) is "never", the value of the leaf
is the value of the leaf['node']['*']['*']['value']. If there is no value for that, then
it is the value of the leaf['node']['default']['default']['value']. Outside of that,
the nodes will be concatenated, or if the step and index is [default](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-default) and [default](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-default)
or "*" and "*", the node will be [default](https://docs.siliconcompiler.com/en/latest/user_guide/glossary.html#term-default) or "global", respectively.

To view the manifest, click the arrow on the dictionary (arrow A). The search bars will return partial matches for either
the keys (arrow B in image below) or the values (arrow C in image below). Press enter to search.
If you do not want to search, delete any text in the search bars and press enter.
You may download the JSON as you view it at any point (arrow D in image below). The name of the file generated is "manifest.json".
You can view the raw manifest by clicking the checkbox to the right of the search bar (arrow E in image below).


### Display Preview Tab

This displays the preview image of the project if there is one in the directory (example given below). If not, this tab will not be included.


### Graphs Tab

This tab is meant to make comparisons between nodes for a given metric across many projects.

At the top of the panel, select which runs/jobs to include for all the graphs (arrow A in image below). These are the runs
from the project's history and the runs included with the `-graph_cfg` flag.

Move the slider to add more graphs or remove old ones (arrow B in image below). Removing old graphs will remove them in the reverse order in which they were added.

For each graph, you must select one metric (show in image below). A random metric will be preselected.
Click 'Apply' to see the changes.

You may select any amount of nodes (show in image below). A random node will be preselected.
If you select 0 nodes, a blank graph will appear.
Click 'Apply' to see the changes.

Sometimes nodes may not have values for a metric, in which case they will not be included in the graph.
In the image below, import0 is not in the legend.

Sometimes nodes that are in the legend are not visible on the graph.
What has happened is that they have the exact same values as some other node.
Consider deselecting other nodes in this case.
In the image below, cts0 is barely visible on the graph.


---

Source: https://docs.siliconcompiler.com/en/latest/development_guide/contribution.html

## Contributing to SiliconCompiler

SiliconCompiler is built for community collaboration.
Our goal is to support hundreds of PDKs, tools, and flows, which is only possible with help from contributors like you.
This guide outlines the process for adding a new module to the project.

Contributing a **module** -- a tool driver, flow, target, PDK or library -- is
what most of this page covers. If you are here to improve the
**documentation** instead, skip to Improving the documentation.


### Before You Begin: The Ground Rules

- **Check for Existing Modules:** Before starting, please browse the repository to see if a module for your target tool or PDK already exists.
- **Permissions and NDAs:** Ensure you have the right to contribute the code and that it does not violate any Non-Disclosure Agreements (NDAs) or copyrights. As a general rule, new PDK modules should be contributed by the foundry, and tool modules by the tool's authors or maintainers.


### The Contribution Workflow in 4 Steps


#### Step 1: Set Up Your Development Environment

First, clone the official SiliconCompiler repository to your local machine and install it in editable mode. This allows your local changes to be immediately reflected when you run tests.

```bash
# Clone the repository
git clone https://github.com/siliconcompiler/siliconcompiler.git
cd siliconcompiler

# Install in editable mode
pip install -e .
```


#### Step 2: Decide Where Your Module Belongs

Not every module belongs in this repository. Before writing any code, find your
case in the table below -- putting a module in the wrong place is the most common
reason a contribution has to be restarted.

| What you have | Where it goes | How to build it |
| --- | --- | --- |
| An **open-source PDK** or standard cell library | The [lambdapdk](https://github.com/siliconcompiler/lambdapdk) package | Contribute it to `lambdapdk`, which is where every open PDK SiliconCompiler ships lives. See [Defining a PDK](https://docs.siliconcompiler.com/en/latest/development_guide/pdks.html#dev-pdks) and [Defining a Library](https://docs.siliconcompiler.com/en/latest/development_guide/libraries.html#dev-libraries) for how to write one. |
| A **closed or proprietary PDK**, or IP you cannot publish | Your own `pip`-installable package | Never commit foundry data here. [Packaging an External Library](https://docs.siliconcompiler.com/en/latest/development_guide/external_libraries.html#dev-external-libraries) covers the package layout, licensing, and how to reference foundry decks out-of-band through environment-variable dataroots. |
| A **tool driver, flow, or target** | In-tree, under `siliconcompiler/` | Continue with Step 3 below. |

> **Note**
> PDK modules should generally be contributed by the foundry, and tool modules
> by the tool's authors or maintainers. If your PDK is under NDA, the second row
> is the path you want -- it is designed so that foundry data never enters a
> published package.


#### Step 3: Create Your New Module File

This step applies to tools, flows, and targets, which live in this repository.
Using existing modules as a reference, place your new Python file in the matching
directory:

```text
siliconcompiler/
├── flows/
│   ├── asicflow.py
│   └── your_flow.py    <--
├── targets/
│   ├── skywater130_demo.py
│   └── your_target.py  <--
└── tools/
    ├── openroad/
    │   └── openroad.py
    └── your_tool/
        └── your_tool.py  <--
```

If you are building a library or PDK as its own package, the layout is different
and is described in [Packaging an External Library](https://docs.siliconcompiler.com/en/latest/development_guide/external_libraries.html#dev-external-libraries).


#### Step 4: Submit Your Contribution

Once you have created and tested your module, you are ready to submit it for review.

Please read our [CONTRIBUTING.md](https://github.com/siliconcompiler/siliconcompiler/blob/main/CONTRIBUTING.md) guide on GitHub.
It contains essential information about our pull request process, coding standards, and how to format your commit messages.


### Improving the documentation

Documentation changes follow the same pull request process as code. What is
particular to the docs is where things live, and a few conventions a green build
will not enforce for you:

- The site is built with Sphinx from `docs/`.
  [docs/README.md](https://github.com/siliconcompiler/siliconcompiler/blob/main/docs/README.md)
  is the reference for building it locally, the directory layout, and the
  writing conventions. Read it before your first documentation change.
- **Most reference pages are generated** from the source tree at build time --
  the schema, the pre-defined module catalogues, the CLI app reference and the
  tool install matrix. Changing one of those means changing the generator or the
  docstring behind it, not the `.rst`.
- **Warnings are errors.** The build passes `-W --keep-going`, so a broken
  cross-reference fails it rather than shipping.
- `tests/docs/` checks what a strict build cannot: prose that is valid
  reStructuredText but links somewhere other than the author intended, and pages
  that have drifted out of a reader's reach.

The process itself -- branches, tests, and the lint gates every pull request is
checked against -- is in
[CONTRIBUTING.md](https://github.com/siliconcompiler/siliconcompiler/blob/main/CONTRIBUTING.md).