8. Flows directory

8.1. asicflow

A configurable ASIC compilation flow.

The ‘asicflow’ includes the stages below. The steps syn, floorplan, physyn, place, cts, route, and dfm have minimizataion associated with them. To view the flowgraph, see the .png file.

  • import: Sources are collected and packaged for compilation

  • syn: Translates RTL to netlist using Yosys

  • floorplan: Floorplanning

  • physyn: Physical Synthesis

  • place: Global and detailed placement

  • cts: Clock tree synthesis

  • route: Global and detailed routing

  • dfm: Metal fill, atenna fixes and any other post routing steps

  • export: Export design from APR tool and merge with library GDS

  • sta: Static timing analysis (signoff)

  • lvs: Layout versus schematic check (signoff)

  • drc: Design rule check (signoff)

The syn, physyn, place, cts, route steps supports per process options that can be set up by setting the ‘arg, flow,’<step>_np’ arg to a value > 1, as detailed below:

  • syn_np : Number of parallel synthesis jobs to launch

  • floorplan_np : Number of parallel floorplan jobs to launch

  • physyn_np : Number of parallel physical synthesis jobs to launch

  • place_np : Number of parallel place jobs to launch

  • cts_np : Number of parallel clock tree synthesis jobs to launch

  • route_np : Number of parallel routing jobs to launch

Setup file: asicflow.py

../_images/asicflow.svg

8.1.1. Configuration

8.1.1.1. asicflow

Keypath

Value

['flowgraph', 'asicflow', 'import', '0', 'tool']

surelog

['flowgraph', 'asicflow', 'syn', '0', 'input']

('import', '0')

['flowgraph', 'asicflow', 'syn', '0', 'goal', 'errors']

0

['flowgraph', 'asicflow', 'syn', '0', 'tool']

yosys

['flowgraph', 'asicflow', 'syn', '1', 'input']

('import', '0')

['flowgraph', 'asicflow', 'syn', '1', 'goal', 'errors']

0

['flowgraph', 'asicflow', 'syn', '1', 'tool']

yosys

['flowgraph', 'asicflow', 'syn', '2', 'input']

('import', '0')

['flowgraph', 'asicflow', 'syn', '2', 'goal', 'errors']

0

['flowgraph', 'asicflow', 'syn', '2', 'tool']

yosys

['flowgraph', 'asicflow', 'synmin', '0', 'input']

  • ('syn', '0')
  • ('syn', '1')
  • ('syn', '2')

['flowgraph', 'asicflow', 'synmin', '0', 'tool']

minimum

['flowgraph', 'asicflow', 'floorplan', '0', 'input']

('synmin', '0')

['flowgraph', 'asicflow', 'floorplan', '0', 'weight', 'cellarea']

1.0

['flowgraph', 'asicflow', 'floorplan', '0', 'weight', 'peakpower']

1.0

['flowgraph', 'asicflow', 'floorplan', '0', 'weight', 'leakagepower']

1.0

['flowgraph', 'asicflow', 'floorplan', '0', 'goal', 'errors']

0

['flowgraph', 'asicflow', 'floorplan', '0', 'goal', 'setupwns']

0

['flowgraph', 'asicflow', 'floorplan', '0', 'goal', 'setuptns']

0

['flowgraph', 'asicflow', 'floorplan', '0', 'tool']

openroad

['flowgraph', 'asicflow', 'floorplan', '1', 'input']

('synmin', '0')

['flowgraph', 'asicflow', 'floorplan', '1', 'weight', 'cellarea']

1.0

['flowgraph', 'asicflow', 'floorplan', '1', 'weight', 'peakpower']

1.0

['flowgraph', 'asicflow', 'floorplan', '1', 'weight', 'leakagepower']

1.0

['flowgraph', 'asicflow', 'floorplan', '1', 'goal', 'errors']

0

['flowgraph', 'asicflow', 'floorplan', '1', 'goal', 'setupwns']

0

['flowgraph', 'asicflow', 'floorplan', '1', 'goal', 'setuptns']

0

['flowgraph', 'asicflow', 'floorplan', '1', 'tool']

openroad

['flowgraph', 'asicflow', 'floorplan', '2', 'input']

('synmin', '0')

['flowgraph', 'asicflow', 'floorplan', '2', 'weight', 'cellarea']

1.0

['flowgraph', 'asicflow', 'floorplan', '2', 'weight', 'peakpower']

1.0

['flowgraph', 'asicflow', 'floorplan', '2', 'weight', 'leakagepower']

1.0

['flowgraph', 'asicflow', 'floorplan', '2', 'goal', 'errors']

0

['flowgraph', 'asicflow', 'floorplan', '2', 'goal', 'setupwns']

0

['flowgraph', 'asicflow', 'floorplan', '2', 'goal', 'setuptns']

0

['flowgraph', 'asicflow', 'floorplan', '2', 'tool']

openroad

['flowgraph', 'asicflow', 'floorplanmin', '0', 'input']

  • ('floorplan', '0')
  • ('floorplan', '1')
  • ('floorplan', '2')

['flowgraph', 'asicflow', 'floorplanmin', '0', 'tool']

minimum

['flowgraph', 'asicflow', 'physyn', '0', 'input']

('floorplanmin', '0')

['flowgraph', 'asicflow', 'physyn', '0', 'weight', 'cellarea']

1.0

['flowgraph', 'asicflow', 'physyn', '0', 'weight', 'peakpower']

1.0

['flowgraph', 'asicflow', 'physyn', '0', 'weight', 'leakagepower']

1.0

['flowgraph', 'asicflow', 'physyn', '0', 'goal', 'errors']

0

['flowgraph', 'asicflow', 'physyn', '0', 'goal', 'setupwns']

0

['flowgraph', 'asicflow', 'physyn', '0', 'goal', 'setuptns']

0

['flowgraph', 'asicflow', 'physyn', '0', 'tool']

openroad

['flowgraph', 'asicflow', 'physyn', '1', 'input']

('floorplanmin', '0')

['flowgraph', 'asicflow', 'physyn', '1', 'weight', 'cellarea']

1.0

['flowgraph', 'asicflow', 'physyn', '1', 'weight', 'peakpower']

1.0

['flowgraph', 'asicflow', 'physyn', '1', 'weight', 'leakagepower']

1.0

['flowgraph', 'asicflow', 'physyn', '1', 'goal', 'errors']

0

['flowgraph', 'asicflow', 'physyn', '1', 'goal', 'setupwns']

0

['flowgraph', 'asicflow', 'physyn', '1', 'goal', 'setuptns']

0

['flowgraph', 'asicflow', 'physyn', '1', 'tool']

openroad

['flowgraph', 'asicflow', 'physyn', '2', 'input']

('floorplanmin', '0')

['flowgraph', 'asicflow', 'physyn', '2', 'weight', 'cellarea']

1.0

['flowgraph', 'asicflow', 'physyn', '2', 'weight', 'peakpower']

1.0

['flowgraph', 'asicflow', 'physyn', '2', 'weight', 'leakagepower']

1.0

['flowgraph', 'asicflow', 'physyn', '2', 'goal', 'errors']

0

['flowgraph', 'asicflow', 'physyn', '2', 'goal', 'setupwns']

0

['flowgraph', 'asicflow', 'physyn', '2', 'goal', 'setuptns']

0

['flowgraph', 'asicflow', 'physyn', '2', 'tool']

openroad

['flowgraph', 'asicflow', 'physynmin', '0', 'input']

  • ('physyn', '0')
  • ('physyn', '1')
  • ('physyn', '2')

['flowgraph', 'asicflow', 'physynmin', '0', 'tool']

minimum

['flowgraph', 'asicflow', 'place', '0', 'input']

('physynmin', '0')

['flowgraph', 'asicflow', 'place', '0', 'weight', 'cellarea']

1.0

['flowgraph', 'asicflow', 'place', '0', 'weight', 'peakpower']

1.0

['flowgraph', 'asicflow', 'place', '0', 'weight', 'leakagepower']

1.0

['flowgraph', 'asicflow', 'place', '0', 'goal', 'errors']

0

['flowgraph', 'asicflow', 'place', '0', 'goal', 'setupwns']

0

['flowgraph', 'asicflow', 'place', '0', 'goal', 'setuptns']

0

['flowgraph', 'asicflow', 'place', '0', 'tool']

openroad

['flowgraph', 'asicflow', 'place', '1', 'input']

('physynmin', '0')

['flowgraph', 'asicflow', 'place', '1', 'weight', 'cellarea']

1.0

['flowgraph', 'asicflow', 'place', '1', 'weight', 'peakpower']

1.0

['flowgraph', 'asicflow', 'place', '1', 'weight', 'leakagepower']

1.0

['flowgraph', 'asicflow', 'place', '1', 'goal', 'errors']

0

['flowgraph', 'asicflow', 'place', '1', 'goal', 'setupwns']

0

['flowgraph', 'asicflow', 'place', '1', 'goal', 'setuptns']

0

['flowgraph', 'asicflow', 'place', '1', 'tool']

openroad

['flowgraph', 'asicflow', 'place', '2', 'input']

('physynmin', '0')

['flowgraph', 'asicflow', 'place', '2', 'weight', 'cellarea']

1.0

['flowgraph', 'asicflow', 'place', '2', 'weight', 'peakpower']

1.0

['flowgraph', 'asicflow', 'place', '2', 'weight', 'leakagepower']

1.0

['flowgraph', 'asicflow', 'place', '2', 'goal', 'errors']

0

['flowgraph', 'asicflow', 'place', '2', 'goal', 'setupwns']

0

['flowgraph', 'asicflow', 'place', '2', 'goal', 'setuptns']

0

['flowgraph', 'asicflow', 'place', '2', 'tool']

openroad

['flowgraph', 'asicflow', 'placemin', '0', 'input']

  • ('place', '0')
  • ('place', '1')
  • ('place', '2')

['flowgraph', 'asicflow', 'placemin', '0', 'tool']

minimum

['flowgraph', 'asicflow', 'cts', '0', 'input']

('placemin', '0')

['flowgraph', 'asicflow', 'cts', '0', 'weight', 'cellarea']

1.0

['flowgraph', 'asicflow', 'cts', '0', 'weight', 'peakpower']

1.0

['flowgraph', 'asicflow', 'cts', '0', 'weight', 'leakagepower']

1.0

['flowgraph', 'asicflow', 'cts', '0', 'goal', 'errors']

0

['flowgraph', 'asicflow', 'cts', '0', 'goal', 'setupwns']

0

['flowgraph', 'asicflow', 'cts', '0', 'goal', 'setuptns']

0

['flowgraph', 'asicflow', 'cts', '0', 'tool']

openroad

['flowgraph', 'asicflow', 'cts', '1', 'input']

('placemin', '0')

['flowgraph', 'asicflow', 'cts', '1', 'weight', 'cellarea']

1.0

['flowgraph', 'asicflow', 'cts', '1', 'weight', 'peakpower']

1.0

['flowgraph', 'asicflow', 'cts', '1', 'weight', 'leakagepower']

1.0

['flowgraph', 'asicflow', 'cts', '1', 'goal', 'errors']

0

['flowgraph', 'asicflow', 'cts', '1', 'goal', 'setupwns']

0

['flowgraph', 'asicflow', 'cts', '1', 'goal', 'setuptns']

0

['flowgraph', 'asicflow', 'cts', '1', 'tool']

openroad

['flowgraph', 'asicflow', 'cts', '2', 'input']

('placemin', '0')

['flowgraph', 'asicflow', 'cts', '2', 'weight', 'cellarea']

1.0

['flowgraph', 'asicflow', 'cts', '2', 'weight', 'peakpower']

1.0

['flowgraph', 'asicflow', 'cts', '2', 'weight', 'leakagepower']

1.0

['flowgraph', 'asicflow', 'cts', '2', 'goal', 'errors']

0

['flowgraph', 'asicflow', 'cts', '2', 'goal', 'setupwns']

0

['flowgraph', 'asicflow', 'cts', '2', 'goal', 'setuptns']

0

['flowgraph', 'asicflow', 'cts', '2', 'tool']

openroad

['flowgraph', 'asicflow', 'ctsmin', '0', 'input']

  • ('cts', '0')
  • ('cts', '1')
  • ('cts', '2')

['flowgraph', 'asicflow', 'ctsmin', '0', 'tool']

minimum

['flowgraph', 'asicflow', 'route', '0', 'input']

('ctsmin', '0')

['flowgraph', 'asicflow', 'route', '0', 'weight', 'cellarea']

1.0

['flowgraph', 'asicflow', 'route', '0', 'weight', 'peakpower']

1.0

['flowgraph', 'asicflow', 'route', '0', 'weight', 'leakagepower']

1.0

['flowgraph', 'asicflow', 'route', '0', 'goal', 'errors']

0

['flowgraph', 'asicflow', 'route', '0', 'goal', 'setupwns']

0

['flowgraph', 'asicflow', 'route', '0', 'goal', 'setuptns']

0

['flowgraph', 'asicflow', 'route', '0', 'tool']

openroad

['flowgraph', 'asicflow', 'route', '1', 'input']

('ctsmin', '0')

['flowgraph', 'asicflow', 'route', '1', 'weight', 'cellarea']

1.0

['flowgraph', 'asicflow', 'route', '1', 'weight', 'peakpower']

1.0

['flowgraph', 'asicflow', 'route', '1', 'weight', 'leakagepower']

1.0

['flowgraph', 'asicflow', 'route', '1', 'goal', 'errors']

0

['flowgraph', 'asicflow', 'route', '1', 'goal', 'setupwns']

0

['flowgraph', 'asicflow', 'route', '1', 'goal', 'setuptns']

0

['flowgraph', 'asicflow', 'route', '1', 'tool']

openroad

['flowgraph', 'asicflow', 'route', '2', 'input']

('ctsmin', '0')

['flowgraph', 'asicflow', 'route', '2', 'weight', 'cellarea']

1.0

['flowgraph', 'asicflow', 'route', '2', 'weight', 'peakpower']

1.0

['flowgraph', 'asicflow', 'route', '2', 'weight', 'leakagepower']

1.0

['flowgraph', 'asicflow', 'route', '2', 'goal', 'errors']

0

['flowgraph', 'asicflow', 'route', '2', 'goal', 'setupwns']

0

['flowgraph', 'asicflow', 'route', '2', 'goal', 'setuptns']

0

['flowgraph', 'asicflow', 'route', '2', 'tool']

openroad

['flowgraph', 'asicflow', 'routemin', '0', 'input']

  • ('route', '0')
  • ('route', '1')
  • ('route', '2')

['flowgraph', 'asicflow', 'routemin', '0', 'tool']

minimum

['flowgraph', 'asicflow', 'dfm', '0', 'input']

('routemin', '0')

['flowgraph', 'asicflow', 'dfm', '0', 'weight', 'cellarea']

1.0

['flowgraph', 'asicflow', 'dfm', '0', 'weight', 'peakpower']

1.0

['flowgraph', 'asicflow', 'dfm', '0', 'weight', 'leakagepower']

1.0

['flowgraph', 'asicflow', 'dfm', '0', 'goal', 'errors']

0

['flowgraph', 'asicflow', 'dfm', '0', 'goal', 'setupwns']

0

['flowgraph', 'asicflow', 'dfm', '0', 'goal', 'setuptns']

0

['flowgraph', 'asicflow', 'dfm', '0', 'tool']

openroad

['flowgraph', 'asicflow', 'export', '0', 'input']

('dfm', '0')

['flowgraph', 'asicflow', 'export', '0', 'tool']

klayout

8.1.1.2. showtool

Keypath

Value

['option', 'showtool', 'def']

klayout

['option', 'showtool', 'gds']

klayout

8.2. asictopflow

A flow for stitching together hardened blocks without doing any automated place-and-route.

This flow generates a GDS and a netlist for passing to a verification/signoff flow.

Setup file: asictopflow.py

../_images/asictopflow.svg

8.2.1. Configuration

8.2.1.1. asictopflow

Keypath

Value

['flowgraph', 'asictopflow', 'import', '0', 'goal', 'errors']

0

['flowgraph', 'asictopflow', 'import', '0', 'tool']

surelog

['flowgraph', 'asictopflow', 'syn', '0', 'input']

('import', '0')

['flowgraph', 'asictopflow', 'syn', '0', 'goal', 'errors']

0

['flowgraph', 'asictopflow', 'syn', '0', 'tool']

yosys

['flowgraph', 'asictopflow', 'export', '0', 'input']

('import', '0')

['flowgraph', 'asictopflow', 'export', '0', 'goal', 'errors']

0

['flowgraph', 'asictopflow', 'export', '0', 'tool']

klayout

['flowgraph', 'asictopflow', 'merge', '0', 'input']

  • ('export', '0')
  • ('syn', '0')

['flowgraph', 'asictopflow', 'merge', '0', 'goal', 'errors']

0

['flowgraph', 'asictopflow', 'merge', '0', 'tool']

join

8.2.1.2. showtool

Keypath

Value

['option', 'showtool', 'def']

klayout

['option', 'showtool', 'gds']

klayout

8.3. dvflow

A configurable constrained random stimulus DV flow.

The verification pipeline includes the followins teps:

  • import: Sources are collected and packaged for compilation

  • compile: RTL sources are compiled into object form (once)

  • testgen: A random seed is used to generate a unique test

  • refsim: A golden trace of test is generated using a reference sim.

  • sim: Compiled RTL is exercised using generated test

  • compare: The outputs of the sim and refsim are compared

  • signoff: Parallel verification pipelines are merged and checked

The dvflow can be parametrized using a single ‘np’ flowarg parameter. Setting ‘np’ > 1 results in multiple independent verificaiton pipelines to be launched.

Setup file: dvflow.py

../_images/dvflow.svg

8.3.1. Configuration

8.3.1.1. dvflow

Keypath

Value

['flowgraph', 'dvflow', 'import', '0', 'tool']

verilator

['flowgraph', 'dvflow', 'compile', '0', 'input']

('import', '0')

['flowgraph', 'dvflow', 'compile', '0', 'tool']

verilator

['flowgraph', 'dvflow', 'testgen', '0', 'input']

('compile', '0')

['flowgraph', 'dvflow', 'testgen', '0', 'tool']

verilator

['flowgraph', 'dvflow', 'refsim', '0', 'input']

('testgen', '0')

['flowgraph', 'dvflow', 'refsim', '0', 'tool']

verilator

['flowgraph', 'dvflow', 'sim', '0', 'input']

('refsim', '0')

['flowgraph', 'dvflow', 'sim', '0', 'tool']

verilator

['flowgraph', 'dvflow', 'compare', '0', 'input']

('sim', '0')

['flowgraph', 'dvflow', 'compare', '0', 'tool']

verilator

['flowgraph', 'dvflow', 'signoff', '0', 'input']

('compare', '0')

['flowgraph', 'dvflow', 'signoff', '0', 'tool']

verify

8.4. fpgaflow

A configurable FPGA compilation flow.

The ‘fpgaflow’ module is a configurable FPGA flow with support for open source and commercial tool flows. The fpgaflow relies on the FPGA partname to determine which design tools to use for RTL to bitstream generation. All flows go through a common design import step that collects all source files from disk before proceeding. The implementation pipeline and tools used depend on the FPGA device being targeted. The following step convention is recommended for tools.

  • import: Sources are collected and packaged for compilation

  • syn: Synthesize RTL into an device specific netlist

  • apr: FPGA specific placement and routing step

  • bitstream: Bitstream generation

  • program: Program the device

Some FPGA target flows have a single ‘compile’ step that combines the syn, apr, and bitstream steps.

The fpgaflow can be configured througthe following schema parameters

Schema keypaths:

  • [‘fpga’, ‘partname’]: Used to select partname to vendor and tool flow

  • [‘fpga’, ‘program’]: Used to turn on/off HW programming step

Setup file: fpgaflow.py

../_images/fpgaflow.svg

8.4.1. Configuration

8.4.1.1. fpgaflow

Keypath

Value

['flowgraph', 'fpgaflow', 'import', '0', 'weight', 'luts']

1.0

['flowgraph', 'fpgaflow', 'import', '0', 'weight', 'dsps']

1.0

['flowgraph', 'fpgaflow', 'import', '0', 'weight', 'brams']

1.0

['flowgraph', 'fpgaflow', 'import', '0', 'weight', 'peakpower']

1.0

['flowgraph', 'fpgaflow', 'import', '0', 'weight', 'leakagepower']

1.0

['flowgraph', 'fpgaflow', 'import', '0', 'weight', 'registers']

1.0

['flowgraph', 'fpgaflow', 'import', '0', 'weight', 'pins']

1.0

['flowgraph', 'fpgaflow', 'import', '0', 'goal', 'errors']

0

['flowgraph', 'fpgaflow', 'import', '0', 'goal', 'warnings']

0

['flowgraph', 'fpgaflow', 'import', '0', 'goal', 'drvs']

0

['flowgraph', 'fpgaflow', 'import', '0', 'goal', 'unconstrained']

0

['flowgraph', 'fpgaflow', 'import', '0', 'goal', 'holdwns']

0

['flowgraph', 'fpgaflow', 'import', '0', 'goal', 'holdtns']

0

['flowgraph', 'fpgaflow', 'import', '0', 'goal', 'holdpaths']

0

['flowgraph', 'fpgaflow', 'import', '0', 'goal', 'setupwns']

0

['flowgraph', 'fpgaflow', 'import', '0', 'goal', 'setuptns']

0

['flowgraph', 'fpgaflow', 'import', '0', 'goal', 'setuppaths']

0

['flowgraph', 'fpgaflow', 'import', '0', 'tool']

surelog

['flowgraph', 'fpgaflow', 'syn', '0', 'input']

('import', '0')

['flowgraph', 'fpgaflow', 'syn', '0', 'weight', 'luts']

1.0

['flowgraph', 'fpgaflow', 'syn', '0', 'weight', 'dsps']

1.0

['flowgraph', 'fpgaflow', 'syn', '0', 'weight', 'brams']

1.0

['flowgraph', 'fpgaflow', 'syn', '0', 'weight', 'peakpower']

1.0

['flowgraph', 'fpgaflow', 'syn', '0', 'weight', 'leakagepower']

1.0

['flowgraph', 'fpgaflow', 'syn', '0', 'weight', 'registers']

1.0

['flowgraph', 'fpgaflow', 'syn', '0', 'weight', 'pins']

1.0

['flowgraph', 'fpgaflow', 'syn', '0', 'goal', 'errors']

0

['flowgraph', 'fpgaflow', 'syn', '0', 'goal', 'warnings']

0

['flowgraph', 'fpgaflow', 'syn', '0', 'goal', 'drvs']

0

['flowgraph', 'fpgaflow', 'syn', '0', 'goal', 'unconstrained']

0

['flowgraph', 'fpgaflow', 'syn', '0', 'goal', 'holdwns']

0

['flowgraph', 'fpgaflow', 'syn', '0', 'goal', 'holdtns']

0

['flowgraph', 'fpgaflow', 'syn', '0', 'goal', 'holdpaths']

0

['flowgraph', 'fpgaflow', 'syn', '0', 'goal', 'setupwns']

0

['flowgraph', 'fpgaflow', 'syn', '0', 'goal', 'setuptns']

0

['flowgraph', 'fpgaflow', 'syn', '0', 'goal', 'setuppaths']

0

['flowgraph', 'fpgaflow', 'syn', '0', 'tool']

yosys

['flowgraph', 'fpgaflow', 'apr', '0', 'input']

('syn', '0')

['flowgraph', 'fpgaflow', 'apr', '0', 'weight', 'luts']

1.0

['flowgraph', 'fpgaflow', 'apr', '0', 'weight', 'dsps']

1.0

['flowgraph', 'fpgaflow', 'apr', '0', 'weight', 'brams']

1.0

['flowgraph', 'fpgaflow', 'apr', '0', 'weight', 'peakpower']

1.0

['flowgraph', 'fpgaflow', 'apr', '0', 'weight', 'leakagepower']

1.0

['flowgraph', 'fpgaflow', 'apr', '0', 'weight', 'registers']

1.0

['flowgraph', 'fpgaflow', 'apr', '0', 'weight', 'pins']

1.0

['flowgraph', 'fpgaflow', 'apr', '0', 'goal', 'errors']

0

['flowgraph', 'fpgaflow', 'apr', '0', 'goal', 'warnings']

0

['flowgraph', 'fpgaflow', 'apr', '0', 'goal', 'drvs']

0

['flowgraph', 'fpgaflow', 'apr', '0', 'goal', 'unconstrained']

0

['flowgraph', 'fpgaflow', 'apr', '0', 'goal', 'holdwns']

0

['flowgraph', 'fpgaflow', 'apr', '0', 'goal', 'holdtns']

0

['flowgraph', 'fpgaflow', 'apr', '0', 'goal', 'holdpaths']

0

['flowgraph', 'fpgaflow', 'apr', '0', 'goal', 'setupwns']

0

['flowgraph', 'fpgaflow', 'apr', '0', 'goal', 'setuptns']

0

['flowgraph', 'fpgaflow', 'apr', '0', 'goal', 'setuppaths']

0

['flowgraph', 'fpgaflow', 'apr', '0', 'tool']

nextpnr

['flowgraph', 'fpgaflow', 'bitstream', '0', 'input']

('apr', '0')

['flowgraph', 'fpgaflow', 'bitstream', '0', 'weight', 'luts']

1.0

['flowgraph', 'fpgaflow', 'bitstream', '0', 'weight', 'dsps']

1.0

['flowgraph', 'fpgaflow', 'bitstream', '0', 'weight', 'brams']

1.0

['flowgraph', 'fpgaflow', 'bitstream', '0', 'weight', 'peakpower']

1.0

['flowgraph', 'fpgaflow', 'bitstream', '0', 'weight', 'leakagepower']

1.0

['flowgraph', 'fpgaflow', 'bitstream', '0', 'weight', 'registers']

1.0

['flowgraph', 'fpgaflow', 'bitstream', '0', 'weight', 'pins']

1.0

['flowgraph', 'fpgaflow', 'bitstream', '0', 'goal', 'errors']

0

['flowgraph', 'fpgaflow', 'bitstream', '0', 'goal', 'warnings']

0

['flowgraph', 'fpgaflow', 'bitstream', '0', 'goal', 'drvs']

0

['flowgraph', 'fpgaflow', 'bitstream', '0', 'goal', 'unconstrained']

0

['flowgraph', 'fpgaflow', 'bitstream', '0', 'goal', 'holdwns']

0

['flowgraph', 'fpgaflow', 'bitstream', '0', 'goal', 'holdtns']

0

['flowgraph', 'fpgaflow', 'bitstream', '0', 'goal', 'holdpaths']

0

['flowgraph', 'fpgaflow', 'bitstream', '0', 'goal', 'setupwns']

0

['flowgraph', 'fpgaflow', 'bitstream', '0', 'goal', 'setuptns']

0

['flowgraph', 'fpgaflow', 'bitstream', '0', 'goal', 'setuppaths']

0

['flowgraph', 'fpgaflow', 'bitstream', '0', 'tool']

icepack

8.5. lintflow

A configurable RTL linting flow.

Setup file: lintflow.py

../_images/lintflow.svg

8.5.1. Configuration

8.5.1.1. lintflow

Keypath

Value

['flowgraph', 'lintflow', 'import', '0', 'tool']

surelog

['flowgraph', 'lintflow', 'lint', '0', 'input']

('import', '0')

['flowgraph', 'lintflow', 'lint', '0', 'tool']

verilator

['flowgraph', 'lintflow', 'export', '0', 'input']

('lint', '0')

['flowgraph', 'lintflow', 'export', '0', 'tool']

nop

8.6. signoffflow

A flow for running LVS/DRC signoff on a GDS layout.

Inputs must be passed to this flow as follows:

chip.set('input', 'gds', '<path-to-layout>.gds')
chip.set('input', 'netlist', '<path-to-netlist>.vg')

Setup file: signoffflow.py

../_images/signoffflow.svg

8.6.1. Configuration

8.6.1.1. signoffflow

Keypath

Value

['flowgraph', 'signoffflow', 'import', '0', 'goal', 'errors']

0

['flowgraph', 'signoffflow', 'import', '0', 'tool']

nop

['flowgraph', 'signoffflow', 'extspice', '0', 'input']

('import', '0')

['flowgraph', 'signoffflow', 'extspice', '0', 'goal', 'errors']

0

['flowgraph', 'signoffflow', 'extspice', '0', 'tool']

magic

['flowgraph', 'signoffflow', 'drc', '0', 'input']

('import', '0')

['flowgraph', 'signoffflow', 'drc', '0', 'goal', 'errors']

0

['flowgraph', 'signoffflow', 'drc', '0', 'tool']

magic

['flowgraph', 'signoffflow', 'lvs', '0', 'input']

('extspice', '0')

['flowgraph', 'signoffflow', 'lvs', '0', 'goal', 'errors']

0

['flowgraph', 'signoffflow', 'lvs', '0', 'tool']

netgen

['flowgraph', 'signoffflow', 'signoff', '0', 'input']

  • ('lvs', '0')
  • ('drc', '0')

['flowgraph', 'signoffflow', 'signoff', '0', 'goal', 'errors']

0

['flowgraph', 'signoffflow', 'signoff', '0', 'tool']

join

8.6.1.2. showtool

Keypath

Value

['option', 'showtool', 'def']

klayout

['option', 'showtool', 'gds']

klayout