12. Targets directory

12.1. asap7_demo

Demonstration target for compiling ASICs with ASAP7 and the open-source asicflow.

Setup file: asap7_demo.py

12.1.4. Configuration

Keypath	Value
`['asic', 'stackup']`	`10M`
`['asic', 'logiclib']`	`asap7sc7p5t_rvt`
`['asic', 'delaymodel']`	`nldm`
`['asic', 'minlayer']`	`m2`
`['asic', 'maxlayer']`	`m7`
`['asic', 'maxfanout']`	`64`
`['asic', 'maxlength']`	`1000`
`['asic', 'maxcap']`	`2e-13`
`['asic', 'maxslew']`	`2e-10`
`['asic', 'rclayer', 'clk']`	`m5`
`['asic', 'rclayer', 'data']`	`m3`
`['asic', 'vpinlayer']`	`m5`
`['asic', 'hpinlayer']`	`m4`
`['asic', 'density']`	`10`
`['asic', 'coremargin']`	`0.27`
`['asic', 'aspectratio']`	`1`
`['constraint', 'worst', 'libcorner']`	`typical`
`['constraint', 'worst', 'pexcorner']`	`typical`
`['constraint', 'worst', 'mode']`	`func`
`['constraint', 'worst', 'check']`	`setup` `hold`
`['option', 'mode']`	`asic`
`['option', 'target']`	`asap7_demo`
`['option', 'flow']`	`asicflow`
`['option', 'pdk']`	`asap7`
`['option', 'optmode']`	`O0`
`['option', 'frontend']`	`verilog`
`['option', 'loglevel']`	`INFO`
`['option', 'builddir']`	`build`
`['option', 'jobname']`	`job0`
`['option', 'showtool', 'def']`	`klayout`
`['option', 'showtool', 'gds']`	`klayout`

12.2. fpgaflow_demo

Demonstration target for running the open-source fpgaflow.

Setup file: fpgaflow_demo.py

12.2.1. Flows

fpgaflow

12.2.2. Configuration

Keypath	Value
`['option', 'mode']`	`fpga`
`['option', 'target']`	`fpgaflow_demo`
`['option', 'flow']`	`fpgaflow`
`['option', 'optmode']`	`O0`
`['option', 'frontend']`	`verilog`
`['option', 'loglevel']`	`INFO`
`['option', 'builddir']`	`build`
`['option', 'jobname']`	`job0`

12.3. freepdk45_demo

Demonstration target for compiling ASICs with FreePDK45 and the open-source asicflow.

Setup file: freepdk45_demo.py

12.3.1. Flows

12.3.2. PDK

freepdk45

12.3.3. Libraries

nangate45

12.3.4. Configuration

Keypath	Value
`['asic', 'stackup']`	`10M`
`['asic', 'pdk']`	`freepdk45`
`['asic', 'logiclib']`	`nangate45`
`['asic', 'delaymodel']`	`nldm`
`['asic', 'minlayer']`	`m1`
`['asic', 'maxlayer']`	`m10`
`['asic', 'maxfanout']`	`64`
`['asic', 'maxlength']`	`1000`
`['asic', 'maxcap']`	`2e-13`
`['asic', 'maxslew']`	`2e-10`
`['asic', 'rclayer', 'clk']`	`m5`
`['asic', 'rclayer', 'data']`	`m3`
`['asic', 'vpinlayer']`	`m2`
`['asic', 'hpinlayer']`	`m3`
`['asic', 'density']`	`10`
`['asic', 'coremargin']`	`1.9`
`['asic', 'aspectratio']`	`1`
`['constraint', 'worst', 'libcorner']`	`typical`
`['constraint', 'worst', 'pexcorner']`	`typical`
`['constraint', 'worst', 'mode']`	`func`
`['constraint', 'worst', 'check']`	`setup` `hold`
`['option', 'mode']`	`asic`
`['option', 'target']`	`freepdk45_demo`
`['option', 'flow']`	`asicflow`
`['option', 'pdk']`	`freepdk45`
`['option', 'optmode']`	`O0`
`['option', 'frontend']`	`verilog`
`['option', 'loglevel']`	`INFO`
`['option', 'builddir']`	`build`
`['option', 'jobname']`	`job0`
`['option', 'showtool', 'def']`	`klayout`
`['option', 'showtool', 'gds']`	`klayout`

12.4. skywater130_demo

Demonstration target for compiling ASICs with Skywater130 and the open-source asicflow.

Setup file: skywater130_demo.py

12.4.1. Flows

12.4.2. PDK

skywater130

12.4.3. Libraries

sky130hd

12.4.4. Configuration

Keypath	Value
`['asic', 'stackup']`	`5M1LI`
`['asic', 'logiclib']`	`sky130hd`
`['asic', 'delaymodel']`	`nldm`
`['asic', 'minlayer']`	`m1`
`['asic', 'maxlayer']`	`m5`
`['asic', 'maxfanout']`	`5`
`['asic', 'maxlength']`	`21000`
`['asic', 'maxcap']`	`1.532e-13`
`['asic', 'maxslew']`	`1.5e-09`
`['asic', 'rclayer', 'clk']`	`m5`
`['asic', 'rclayer', 'data']`	`m3`
`['asic', 'vpinlayer']`	`m2`
`['asic', 'hpinlayer']`	`m3`
`['asic', 'density']`	`10`
`['asic', 'coremargin']`	`4.6`
`['asic', 'aspectratio']`	`1`
`['constraint', 'worst', 'libcorner']`	`typical`
`['constraint', 'worst', 'pexcorner']`	`typical`
`['constraint', 'worst', 'mode']`	`func`
`['constraint', 'worst', 'check']`	`setup` `hold`
`['option', 'mode']`	`asic`
`['option', 'target']`	`skywater130_demo`
`['option', 'flow']`	`asicflow`
`['option', 'pdk']`	`skywater130`
`['option', 'optmode']`	`O0`
`['option', 'frontend']`	`verilog`
`['option', 'loglevel']`	`INFO`
`['option', 'builddir']`	`build`
`['option', 'jobname']`	`job0`
`['option', 'showtool', 'def']`	`klayout`
`['option', 'showtool', 'gds']`	`klayout`