12. Targets directory

12.1. asap7_demo

Demonstration target for compiling ASICs with ASAP7 and the open-source asicflow.

Keypath	Value
`['asic', 'logiclib']`	`asap7sc7p5t_rvt`
`['asic', 'delaymodel']`	`nldm`
`['constraint', 'timing', 'worst', 'libcorner']`	`typical`
`['constraint', 'timing', 'worst', 'pexcorner']`	`typical`
`['constraint', 'timing', 'worst', 'mode']`	`func`
`['constraint', 'timing', 'worst', 'check']`	`setup` `hold`
`['constraint', 'coremargin']`	`0.27`
`['constraint', 'density']`	`10.0`
`['constraint', 'aspectratio']`	`1.0`
`['option', 'mode']`	`asic`
`['option', 'pdk']`	`asap7`
`['option', 'stackup']`	`10M`
`['option', 'flow']`	`asicflow`
`['option', 'optmode']`	`O0`
`['option', 'frontend']`	`verilog`
`['option', 'loglevel']`	`INFO`
`['option', 'builddir']`	`build`
`['option', 'jobname']`	`job0`
`['option', 'showtool', 'gds']`	`klayout`
`['option', 'showtool', 'lef']`	`klayout`
`['option', 'showtool', 'def']`	`openroad`
`['option', 'showtool', 'odb']`	`openroad`
`['option', 'scheduler', 'msgevent']`	`NONE`

Demonstration target for running the open-source fpgaflow.

Demonstration target for compiling ASICs with FreePDK45 and the open-source asicflow.

Keypath	Value
`['asic', 'logiclib']`	`nangate45`
`['asic', 'delaymodel']`	`nldm`
`['constraint', 'timing', 'worst', 'libcorner']`	`typical`
`['constraint', 'timing', 'worst', 'pexcorner']`	`typical`
`['constraint', 'timing', 'worst', 'mode']`	`func`
`['constraint', 'timing', 'worst', 'check']`	`setup` `hold`
`['constraint', 'coremargin']`	`1.9`
`['constraint', 'density']`	`10.0`
`['constraint', 'aspectratio']`	`1.0`
`['option', 'mode']`	`asic`
`['option', 'pdk']`	`freepdk45`
`['option', 'stackup']`	`10M`
`['option', 'flow']`	`asicflow`
`['option', 'optmode']`	`O0`
`['option', 'frontend']`	`verilog`
`['option', 'loglevel']`	`INFO`
`['option', 'builddir']`	`build`
`['option', 'jobname']`	`job0`
`['option', 'showtool', 'gds']`	`klayout`
`['option', 'showtool', 'lef']`	`klayout`
`['option', 'showtool', 'def']`	`openroad`
`['option', 'showtool', 'odb']`	`openroad`
`['option', 'scheduler', 'msgevent']`	`NONE`

Demonstration target for compiling ASICs with Skywater130 and the open-source asicflow.

Keypath	Value
`['asic', 'logiclib']`	`sky130hd`
`['asic', 'delaymodel']`	`nldm`
`['constraint', 'timing', 'worst', 'libcorner']`	`typical`
`['constraint', 'timing', 'worst', 'pexcorner']`	`typical`
`['constraint', 'timing', 'worst', 'mode']`	`func`
`['constraint', 'timing', 'worst', 'check']`	`setup` `hold`
`['constraint', 'coremargin']`	`4.6`
`['constraint', 'density']`	`10.0`
`['constraint', 'aspectratio']`	`1.0`
`['option', 'mode']`	`asic`
`['option', 'pdk']`	`skywater130`
`['option', 'stackup']`	`5M1LI`
`['option', 'flow']`	`asicflow`
`['option', 'optmode']`	`O0`
`['option', 'frontend']`	`verilog`
`['option', 'loglevel']`	`INFO`
`['option', 'builddir']`	`build`
`['option', 'jobname']`	`job0`
`['option', 'showtool', 'gds']`	`klayout`
`['option', 'showtool', 'lef']`	`klayout`
`['option', 'showtool', 'def']`	`openroad`
`['option', 'showtool', 'odb']`	`openroad`
`['option', 'scheduler', 'msgevent']`	`NONE`