9. Tools directory
9.1. bambu
Setup file: bambu.py
Keypath |
Value |
bambu |
|
--version |
|
>=0.9.6 |
|
|
<design>.v |
|
input,hll,c |
|
tools/bambu |
|
2 |
9.2. bluespec
Bluespec is a high-level hardware description language. It has a variety of advanced features including a powerful type system that can prevent errors prior to synthesis time, and its most distinguishing feature, Guarded Atomic Actions, allow you to define hardware components in a modular manner based on their invariants, and let the compiler pick a scheduler.
Documentation: https://github.com/B-Lang-org/bsc#documentation
Sources: https://github.com/B-Lang-org/bsc
Installation: https://github.com/B-Lang-org/bsc#download
Setup file: bluespec.py
Keypath |
Value |
bsc |
|
-v |
|
>=2021.07 |
|
|
<design>.v |
|
input,hll,bsv |
|
tools/bluespec |
|
2 |
9.3. chisel
Chisel is a hardware design language that facilitates advanced circuit generation and design reuse for both ASIC and FPGA digital logic designs. Chisel adds hardware construction primitives to the Scala programming language, providing designers with the power of a modern programming language to write complex, parameterizable circuit generators that produce synthesizable Verilog.
Documentation: https://www.chisel-lang.org/chisel3/docs/introduction.html
Sources: https://github.com/chipsalliance/chisel3
Installation: The Chisel plugin relies on having the Scala Build Tool (sbt) installed. Instructions: https://www.scala-sbt.org/download.html.
Setup file: chisel.py
Keypath |
Value |
sbt |
|
--version |
|
>=1.5.5 |
|
|
"runMain SCDriver --module <design> -o ../outputs/<design>.v" |
|
<design>.v |
|
tools/chisel |
|
|
|
2 |
9.4. genfasm
To-Do: Add details here
Setup file: genfasm.py
Keypath |
Value |
genfasm |
|
0.0 |
|
|
|
|
2 |
9.5. ghdl
GHDL is an open-source analyzer, compiler, simulator and (experimental) synthesizer for VHDL. It allows you to analyse and elaborate sources for generating machine code from your design. Native program execution is the only way for high speed simulation.
Documentation: https://ghdl.readthedocs.io/en/latest
Sources: https://github.com/ghdl/ghdl
Installation: https://github.com/ghdl/ghdl
Setup file: ghdl.py
9.6. icarus
Icarus is a verilog simulator with full support for Verilog IEEE-1364. Icarus can simulate synthesizable as well as behavioral Verilog.
Documentation: http://iverilog.icarus.com
Sources: https://github.com/steveicarus/iverilog.git
Installation: https://github.com/steveicarus/iverilog.git
Setup file: icarus.py
Keypath |
Value |
iverilog |
|
-V |
|
>=10.3 |
|
|
-o outputs/<design>.vvp |
|
input,rtl,verilog |
|
2 |
9.7. icepack
Icepack converts an ASCII bitstream file to a .bin file for the ICE40 FPGA.
Documentation: http://bygone.clairexen.net/icestorm/
Sources: https://github.com/YosysHQ/icestorm
Installation: https://github.com/YosysHQ/icestorm
Setup file: icepack.py
9.8. klayout
Klayout is a production grade viewer and editor of GDSII and Oasis data with customizable Python and Ruby interfaces.
Documentation: https://www.klayout.de
Sources: https://github.com/KLayout/klayout
Installation: https://www.klayout.de/build.html
Setup file: klayout.py
Keypath |
Value |
klayout |
|
|
|
>=0.27.6 |
|
json |
|
|
(WARNING|warning) |
|
ERROR |
|
true |
|
/home/docs/checkouts/readthedocs.org/user_builds/siliconcompiler/checkouts/latest/siliconcompiler:/home/docs/checkouts/readthedocs.org/user_builds/siliconcompiler/checkouts/latest/docs:/home/docs/checkouts/readthedocs.org/user_builds/siliconcompiler/envs/latest/lib/python37.zip:/home/docs/checkouts/readthedocs.org/user_builds/siliconcompiler/envs/latest/lib/python3.7:/home/docs/checkouts/readthedocs.org/user_builds/siliconcompiler/envs/latest/lib/python3.7/lib-dynload:/home/docs/.pyenv/versions/3.7.9/lib/python3.7:/home/docs/checkouts/readthedocs.org/user_builds/siliconcompiler/envs/latest/lib/python3.7/site-packages:/home/docs/checkouts/readthedocs.org/user_builds/siliconcompiler/checkouts/latest/docs/_ext:/home/docs/checkouts/readthedocs.org/user_builds/siliconcompiler/envs/latest/lib/python3.7/site-packages/siliconcompiler |
|
tools/klayout |
9.9. magic
Magic is a chip layout viewer, editor, and circuit verifier with built in DRC and LVS engines.
Documentation: http://opencircuitdesign.com/magic/userguide.html
Installation: https://github.com/RTimothyEdwards/magic
Sources: https://github.com/RTimothyEdwards/magic
Setup file: magic.py
Keypath |
Value |
magic |
|
--version |
|
>=8.3.196 |
|
tcl |
|
|
^Error |
|
warning |
|
|
<design>.gds |
|
|
reports/<design>.drc |
tools/magic |
|
sc_magic.tcl |
|
4 |
|
|
^Error |
|
warning |
|
|
|
<design>.gds |
|
tools/magic |
|
sc_magic.tcl |
|
4 |
9.10. netgen
Netgen is a tool for comparing netlists. By comparing a Verilog netlist with one extracted from a circuit layout, it can be used to perform LVS verification.
Documentation: http://www.opencircuitdesign.com/netgen/
Installation: https://github.com/RTimothyEdwards/netgen
Sources: https://github.com/RTimothyEdwards/netgen
Setup file: netgen.py
Keypath |
Value |
netgen |
|
-batch |
|
>=1.5.192 |
|
tcl |
|
|
^Warning: |
|
|
|
|
|
log |
|
errors |
|
lvs.errors |
|
reports/<design>.lvs.out |
|
reports/<design>.lvs.out |
tools/netgen |
|
sc_lvs.tcl |
|
|
4 |
9.11. nextpnr
nextpnr is a vendor neutral FPGA place and route tool with support for the ICE40, ECP5, and Nexus devices from Lattice.
Documentation: https://github.com/YosysHQ/nextpnr
Sources: https://github.com/YosysHQ/nextpnr
Installation: https://github.com/YosysHQ/nextpnr
Setup file: nextpnr.py
Keypath |
Value |
nextpnr-ice40 |
|
--version |
|
>=0.2 |
|
|
|
<design>_netlist.json |
|
|
<design>.asc |
9.12. openfpgaloader
The OpenFPGALoader is a universal utility for programming FPGAs. Compatible with many boards, cables and FPGA from major manufacturers (Xilinx, Altera/Intel, Lattice, Gowin, Efinix, Anlogic). openFPGALoader works on Linux, Windows and macOS.
Documentation: https://github.com/trabucayre/openFPGALoader
Sources: https://github.com/trabucayre/openFPGALoader
Installation: https://github.com/trabucayre/openFPGALoader
Status: SC integration WIP
Setup file: openfpgaloader.py
Keypath |
Value |
openfpgaloader |
|
--Version |
|
0.5.0 |
|
|
inputs<design>.bit |
9.13. openroad
OpenROAD is an automated physical design platform for integrated circuit design with a complete set of features needed to translate a synthesized netlist to a tapeout ready GDSII.
Documentation: https://openroad.readthedocs.io/
Sources: https://github.com/The-OpenROAD-Project/OpenROAD
Installation: https://github.com/The-OpenROAD-Project/OpenROAD
Setup file: openroad.py
9.14. surelog
Surelog is a SystemVerilog pre-processor, parser, elaborator, and UHDM compiler that provdes IEEE design and testbench C/C++ VPI and a Python AST API.
Documentation: https://github.com/chipsalliance/Surelog
Sources: https://github.com/chipsalliance/Surelog
Installation: https://github.com/chipsalliance/Surelog
Setup file: surelog.py
Keypath |
Value |
surelog |
|
/home/docs/checkouts/readthedocs.org/user_builds/siliconcompiler/envs/latest/lib/python3.7/site-packages/siliconcompiler/tools/surelog/bin |
|
--version |
|
>=1.13 |
|
|
^\[WRN: |
|
^\[(ERR|FTL|SNT): |
|
-nocache |
9.15. sv2v
sv2v converts SystemVerilog (IEEE 1800-2017) to Verilog (IEEE 1364-2005), with an emphasis on supporting synthesizable language constructs. The primary goal of this project is to create a completely free and open-source tool for converting SystemVerilog to Verilog. While methods for performing this conversion already exist, they generally either rely on commercial tools, or are limited in scope.
Documentation: https://github.com/zachjs/sv2v
Sources: https://github.com/zachjs/sv2v
Installation: https://github.com/zachjs/sv2v
Setup file: sv2v.py
Keypath |
Value |
sv2v |
|
--numeric-version |
|
>=0.0.9 |
|
|
|
|
<design>.v |
|
<design>.v |
|
4 |
9.16. template
Tool description
Documentation:https:// Sources: https:// Installation: https://
Setup file: template.py
9.17. verilator
Verilator is a free and open-source software tool which converts Verilog (a hardware description language) to a cycle-accurate behavioral model in C++ or SystemC.
9.17.1. Steps supported
import
Preprocesses and pickles Verilog sources. Takes in a set of Verilog source
files supplied via ['input', 'verilog', ...] and reads the following
parameters:
Outputs a single Verilog file in outputs/<design>.v.
lint
Lints Verilog source. Takes in a single pickled Verilog file from
inputs/<design>.v and produces no outputs. Results of linting can be
programatically queried using errors/warnings metrics.
compile
Compiles Verilog and C/C++ sources into an executable. Takes in a single
pickled Verilog file from inputs/<design>.v and a set of C/C++ sources
from ['input', 'c', ...]. Outputs an executable in
outputs/<design>.vexe.
This step supports using the ['option', 'trace'] parameter to enable
Verilator’s --trace flag.
For all steps, this driver runs Verilator using the -sv switch to enable
parsing a subset of SystemVerilog features. All steps also support using
['option', 'relax'] to make warnings nonfatal.
Documentation: https://verilator.org/guide/latest
Sources: https://github.com/verilator/verilator
Installation: https://verilator.org/guide/latest/install.html
Setup file: verilator.py
Keypath |
Value |
verilator |
|
--version |
|
>=4.028 |
|
|
^\%Warning |
|
^\%Error |
|
|
|
2 |
|
|
|
<design>.v |
|
input,rtl,verilog |
9.18. vivado
Vivado is an FPGA programming tool suite from Xilinx used to program Xilinx devices.
Documentation: https://www.xilinx.com/products/design-tools/vivado.html
Setup file: vivado.py
9.19. vpr
VPR (Versatile Place and Route) is an open source CAD tool designed for the exploration of new FPGA architectures and CAD algorithms, at the packing, placement and routing phases of the CAD flow. VPR takes, as input, a description of an FPGA architecture along with a technology-mapped user circuit. It then performs packing, placement, and routing to map the circuit onto the FPGA. The output of VPR includes the FPGA configuration needed to implement the circuit and statistics about the final mapped design (eg. critical path delay, area, etc).
Documentation: https://docs.verilogtorouting.org/en/latest
Sources: https://github.com/verilog-to-routing/vtr-verilog-to-routing
Installation: https://github.com/verilog-to-routing/vtr-verilog-to-routing
Setup file: vpr.py
Keypath |
Value |
vpr |
|
0.0 |
|
|
|
|
|
2 |
9.20. xyce
Xyce is a high performance SPICE-compatible circuit simulator capable capable of solving extremely large circuit problems by supporting large-scale parallel computing platforms. It also supports serial execution on all common desktop platforms, and small-scale parallel runs on Unix-like systems.
Documentation: https://xyce.sandia.gov/documentation
Sources: https://github.com/Xyce/Xyce
Installation: https://xyce.sandia.gov/documentation/BuildingGuide.html
Status: SC integration WIP
Setup file: xyce.py
Keypath |
Value |
xyce |
|
0.0 |
|
|
2 |
9.21. yosys
Yosys is a framework for RTL synthesis that takes synthesizable Verilog-2005 design and converts it to BLIF, EDIF, BTOR, SMT, Verilog netlist etc. The tool supports logical synthesis and tech mapping to ASIC standard cell libraries, FPGA architectures. In addition it has built in formal methods for property and equivalence checking.
Documentation: http://www.clifford.at/yosys/documentation.html
Sources: https://github.com/YosysHQ/yosys
Installation: https://github.com/YosysHQ/yosys
Setup file: yosys.py