9. Tools directory

9.1. bambu

Setup file: bambu.py

Keypath

Value

['tool', 'bambu', 'exe']

bambu

['tool', 'bambu', 'vswitch']

--version

['tool', 'bambu', 'version']

>=0.9.6

['tool', 'bambu', 'output', 'import', '0']

<design>.v

['tool', 'bambu', 'require', 'import', '0']

input,c

['tool', 'bambu', 'refdir', 'import', '0']

tools/bambu

['tool', 'bambu', 'threads', 'import', '0']

2

9.2. bluespec

Bluespec is a high-level hardware description language. It has a variety of advanced features including a powerful type system that can prevent errors prior to synthesis time, and its most distinguishing feature, Guarded Atomic Actions, allow you to define hardware components in a modular manner based on their invariants, and let the compiler pick a scheduler.

Documentation: https://github.com/B-Lang-org/bsc#documentation

Sources: https://github.com/B-Lang-org/bsc

Installation: https://github.com/B-Lang-org/bsc#download

Setup file: bluespec.py

Keypath

Value

['tool', 'bluespec', 'exe']

bsc

['tool', 'bluespec', 'vswitch']

-v

['tool', 'bluespec', 'version']

>=2021.07

['tool', 'bluespec', 'output', 'import', '0']

<design>.v

['tool', 'bluespec', 'require', 'import', '0']

input,bsv

['tool', 'bluespec', 'refdir', 'import', '0']

tools/bluespec

['tool', 'bluespec', 'threads', 'import', '0']

2

9.3. chisel

Chisel is a hardware design language that facilitates advanced circuit generation and design reuse for both ASIC and FPGA digital logic designs. Chisel adds hardware construction primitives to the Scala programming language, providing designers with the power of a modern programming language to write complex, parameterizable circuit generators that produce synthesizable Verilog.

Documentation: https://www.chisel-lang.org/chisel3/docs/introduction.html

Sources: https://github.com/chipsalliance/chisel3

Installation: The Chisel plugin relies on having the Scala Build Tool (sbt) installed. Instructions: https://www.scala-sbt.org/download.html.

Setup file: chisel.py

Keypath

Value

['tool', 'chisel', 'exe']

sbt

['tool', 'chisel', 'vswitch']

--version

['tool', 'chisel', 'version']

>=1.5.5

['tool', 'chisel', 'option', 'import', '0']

"runMain SCDriver --module <design> -o ../outputs/<design>.v"

['tool', 'chisel', 'output', 'import', '0']

<design>.v

['tool', 'chisel', 'refdir', 'import', '0']

tools/chisel

['tool', 'chisel', 'keep', 'import', '0']

  • build.sbt
  • SCDriver.scala

['tool', 'chisel', 'threads', 'import', '0']

2

9.4. genfasm

To-Do: Add details here

Setup file: genfasm.py

Keypath

Value

['tool', 'genfasm', 'exe']

genfasm

['tool', 'genfasm', 'version']

0.0

['tool', 'genfasm', 'option', 'apr', <index>]

  • inputs/<design>.blif
  • --net_file inputs/<design>.net
  • --place_file inputs/<design>.place
  • --route_file inputs/<design>.route

['tool', 'genfasm', 'threads', 'apr', <index>]

2

9.5. ghdl

GHDL is an open-source analyzer, compiler, simulator and (experimental) synthesizer for VHDL. It allows you to analyse and elaborate sources for generating machine code from your design. Native program execution is the only way for high speed simulation.

Documentation: https://ghdl.readthedocs.io/en/latest

Sources: https://github.com/ghdl/ghdl

Installation: https://github.com/ghdl/ghdl

Setup file: ghdl.py

Keypath

Value

['tool', 'ghdl', 'exe']

ghdl

['tool', 'ghdl', 'vswitch']

--version

['tool', 'ghdl', 'version']

>=2.0.0-dev

['tool', 'ghdl', 'option', 'import', <index>]

['tool', 'ghdl', 'output', 'import', <index>]

<design>.v

['tool', 'ghdl', 'stdout', 'import', <index>, 'destination']

output

['tool', 'ghdl', 'stdout', 'import', <index>, 'suffix']

v

['tool', 'ghdl', 'require', 'import', <index>]

input,vhdl

['tool', 'ghdl', 'threads', 'import', <index>]

4

9.6. icarus

Icarus is a verilog simulator with full support for Verilog IEEE-1364. Icarus can simulate synthesizable as well as behavioral Verilog.

Documentation: http://iverilog.icarus.com

Sources: https://github.com/steveicarus/iverilog.git

Installation: https://github.com/steveicarus/iverilog.git

Setup file: icarus.py

Keypath

Value

['tool', 'icarus', 'exe']

iverilog

['tool', 'icarus', 'vswitch']

-V

['tool', 'icarus', 'version']

>=10.3

['tool', 'icarus', 'option', 'run', <index>]

['tool', 'icarus', 'require', 'run', <index>]

input,verilog

['tool', 'icarus', 'threads', 'run', <index>]

2

9.7. icepack

Icepack converts an ASCII bitstream file to a .bin file for the ICE40 FPGA.

Documentation: http://bygone.clairexen.net/icestorm/

Sources: https://github.com/YosysHQ/icestorm

Installation: https://github.com/YosysHQ/icestorm

Setup file: icepack.py

Keypath

Value

['tool', 'icepack', 'exe']

icepack

['tool', 'icepack', 'option', 'bitstream', <index>]

['tool', 'icepack', 'input', 'bitstream', <index>]

<design>.asc

['tool', 'icepack', 'output', 'bitstream', <index>]

<design>.bit

9.8. klayout

Klayout is a production grade viewer and editor of GDSII and Oasis data with customizable Python and Ruby interfaces.

Documentation: https://www.klayout.de

Sources: https://github.com/KLayout/klayout

Installation: https://www.klayout.de/build.html

Setup file: klayout.py

Keypath

Value

['tool', 'klayout', 'exe']

klayout

['tool', 'klayout', 'vswitch']

  • -zz
  • -v

['tool', 'klayout', 'version']

>=0.27.6

['tool', 'klayout', 'format']

json

['tool', 'klayout', 'regex', 'export', <index>, 'warnings']

(WARNING|warning)

['tool', 'klayout', 'regex', 'export', <index>, 'errors']

ERROR

['tool', 'klayout', 'option', 'export', <index>]

  • -b
  • -r

['tool', 'klayout', 'var', 'export', <index>, 'timestamps']

true

['tool', 'klayout', 'input', 'export', <index>]

<design>.def

['tool', 'klayout', 'output', 'export', <index>]

<design>.gds

['tool', 'klayout', 'require', 'export', <index>]

  • asic,logiclib
  • asic,stackup
  • pdk,freepdk45,layermap,klayout,def,gds,10M
  • library,nangate45,model,layout,gds,10M
  • library,nangate45,model,layout,lef,10M

['tool', 'klayout', 'refdir', 'export', <index>]

tools/klayout

['tool', 'klayout', 'script', 'export', <index>]

klayout_export.py

9.9. magic

Magic is a chip layout viewer, editor, and circuit verifier with built in DRC and LVS engines.

Documentation: http://opencircuitdesign.com/magic/userguide.html

Installation: https://github.com/RTimothyEdwards/magic

Sources: https://github.com/RTimothyEdwards/magic

Setup file: magic.py

Keypath

Value

['tool', 'magic', 'exe']

magic

['tool', 'magic', 'vswitch']

--version

['tool', 'magic', 'version']

>=8.3.196

['tool', 'magic', 'format']

tcl

['tool', 'magic', 'regex', 'drc', <index>, 'errors']

^Error

['tool', 'magic', 'regex', 'drc', <index>, 'warnings']

warning

['tool', 'magic', 'regex', 'extspice', <index>, 'errors']

^Error

['tool', 'magic', 'regex', 'extspice', <index>, 'warnings']

warning

['tool', 'magic', 'option', 'drc', <index>]

  • -noc
  • -dnull

['tool', 'magic', 'option', 'extspice', <index>]

  • -noc
  • -dnull

['tool', 'magic', 'input', 'drc', <index>]

<design>.gds

['tool', 'magic', 'input', 'extspice', <index>]

<design>.gds

['tool', 'magic', 'output', 'extspice', <index>]

<design>.spice

['tool', 'magic', 'report', 'drc', <index>, 'drvs']

reports/<design>.drc

['tool', 'magic', 'refdir', 'drc', <index>]

tools/magic

['tool', 'magic', 'refdir', 'extspice', <index>]

tools/magic

['tool', 'magic', 'script', 'drc', <index>]

sc_magic.tcl

['tool', 'magic', 'script', 'extspice', <index>]

sc_magic.tcl

['tool', 'magic', 'threads', 'drc', <index>]

4

['tool', 'magic', 'threads', 'extspice', <index>]

4

9.10. netgen

Netgen is a tool for comparing netlists. By comparing a Verilog netlist with one extracted from a circuit layout, it can be used to perform LVS verification.

Documentation: http://www.opencircuitdesign.com/netgen/

Installation: https://github.com/RTimothyEdwards/netgen

Sources: https://github.com/RTimothyEdwards/netgen

Setup file: netgen.py

Keypath

Value

['tool', 'netgen', 'exe']

netgen

['tool', 'netgen', 'vswitch']

-batch

['tool', 'netgen', 'version']

>=1.5.192

['tool', 'netgen', 'format']

tcl

['tool', 'netgen', 'regex', 'lvs', <index>, 'warnings']

^Warning:

['tool', 'netgen', 'option', 'lvs', <index>]

  • -batch
  • source

['tool', 'netgen', 'input', 'lvs', <index>]

  • <design>.spice
  • <design>.vg

['tool', 'netgen', 'stderr', 'lvs', <index>, 'destination']

log

['tool', 'netgen', 'stderr', 'lvs', <index>, 'suffix']

errors

['tool', 'netgen', 'report', 'lvs', <index>, 'errors']

lvs.errors

['tool', 'netgen', 'report', 'lvs', <index>, 'drvs']

reports/<design>.lvs.out

['tool', 'netgen', 'report', 'lvs', <index>, 'warnings']

reports/<design>.lvs.out

['tool', 'netgen', 'refdir', 'lvs', <index>]

tools/netgen

['tool', 'netgen', 'script', 'lvs', <index>]

sc_lvs.tcl

['tool', 'netgen', 'threads', 'lvs', <index>]

4

9.11. nextpnr

nextpnr is a vendor neutral FPGA place and route tool with support for the ICE40, ECP5, and Nexus devices from Lattice.

Documentation: https://github.com/YosysHQ/nextpnr

Sources: https://github.com/YosysHQ/nextpnr

Installation: https://github.com/YosysHQ/nextpnr

Setup file: nextpnr.py

Keypath

Value

['tool', 'nextpnr', 'exe']

nextpnr-ice40

['tool', 'nextpnr', 'vswitch']

--version

['tool', 'nextpnr', 'version']

>=0.2

['tool', 'nextpnr', 'option', <apr>, <index>]

['tool', 'nextpnr', 'input', <apr>, <index>]

<design>_netlist.json

['tool', 'nextpnr', 'output', <apr>, <index>]

<design>.asc

9.12. openfpgaloader

The OpenFPGALoader is a universal utility for programming FPGAs. Compatible with many boards, cables and FPGA from major manufacturers (Xilinx, Altera/Intel, Lattice, Gowin, Efinix, Anlogic). openFPGALoader works on Linux, Windows and macOS.

Documentation: https://github.com/trabucayre/openFPGALoader

Sources: https://github.com/trabucayre/openFPGALoader

Installation: https://github.com/trabucayre/openFPGALoader

Status: SC integration WIP

Setup file: openfpgaloader.py

Keypath

Value

['tool', 'openfpgaloader', 'exe']

openfpgaloader

['tool', 'openfpgaloader', 'vswitch']

--Version

['tool', 'openfpgaloader', 'version']

0.5.0

['tool', 'openfpgaloader', 'option', 'program', '0']

inputs<design>.bit

9.13. openroad

OpenROAD is an automated physical design platform for integrated circuit design with a complete set of features needed to translate a synthesized netlist to a tapeout ready GDSII.

Documentation:https://github.com/The-OpenROAD-Project/OpenROAD

Sources: https://github.com/The-OpenROAD-Project/OpenROAD

Installation: https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts

Setup file: openroad.py

Keypath

Value

['tool', 'openroad', 'exe']

openroad

['tool', 'openroad', 'vswitch']

-version

['tool', 'openroad', 'version']

>=v2.0-3394

['tool', 'openroad', 'format']

tcl

['tool', 'openroad', 'regex', <step>, <index>, 'warnings']

^\[WARNING

['tool', 'openroad', 'regex', <step>, <index>, 'errors']

^\[ERROR

['tool', 'openroad', 'option', <step>, <index>]

-no_init -exit

['tool', 'openroad', 'var', <step>, <index>, 'place_density']

0.3

['tool', 'openroad', 'var', <step>, <index>, 'pad_global_place']

2

['tool', 'openroad', 'var', <step>, <index>, 'pad_detail_place']

1

['tool', 'openroad', 'var', <step>, <index>, 'macro_place_halo']

  • 22.4
  • 15.12

['tool', 'openroad', 'var', <step>, <index>, 'macro_place_channel']

  • 18.8
  • 19.95

['tool', 'openroad', 'require', <step>, <index>]

  • asic,logiclib
  • asic,stackup
  • pdk,freepdk45,aprtech,openroad,10M,10t,lef
  • library,nangate45,model,timing,nldm,typical
  • library,nangate45,model,layout,lef,10M
  • tool,openroad,var,<step>,<index>,place_density
  • tool,openroad,var,<step>,<index>,pad_global_place
  • tool,openroad,var,<step>,<index>,pad_detail_place
  • tool,openroad,var,<step>,<index>,macro_place_halo
  • tool,openroad,var,<step>,<index>,macro_place_channel

['tool', 'openroad', 'report', <step>, <index>, 'cellarea']

<step>.log

['tool', 'openroad', 'report', <step>, <index>, 'totalarea']

<step>.log

['tool', 'openroad', 'report', <step>, <index>, 'utilization']

<step>.log

['tool', 'openroad', 'report', <step>, <index>, 'setuptns']

<step>.log

['tool', 'openroad', 'report', <step>, <index>, 'setupwns']

<step>.log

['tool', 'openroad', 'report', <step>, <index>, 'setupslack']

<step>.log

['tool', 'openroad', 'report', <step>, <index>, 'wirelength']

<step>.log

['tool', 'openroad', 'report', <step>, <index>, 'vias']

<step>.log

['tool', 'openroad', 'report', <step>, <index>, 'peakpower']

<step>.log

['tool', 'openroad', 'report', <step>, <index>, 'leakagepower']

<step>.log

['tool', 'openroad', 'refdir', <step>, <index>]

tools/openroad

['tool', 'openroad', 'script', <step>, <index>]

sc_apr.tcl

['tool', 'openroad', 'threads', <step>, <index>]

2

9.14. surelog

Surelog is a SystemVerilog pre-processor, parser, elaborator, and UHDM compiler that provdes IEEE design and testbench C/C++ VPI and a Python AST API.

Documentation: https://github.com/chipsalliance/Surelog

Sources: https://github.com/chipsalliance/Surelog

Installation: https://github.com/chipsalliance/Surelog

Setup file: surelog.py

Keypath

Value

['tool', 'surelog', 'exe']

surelog

['tool', 'surelog', 'path']

/home/docs/checkouts/readthedocs.org/user_builds/siliconcompiler/envs/latest/lib/python3.7/site-packages/siliconcompiler/tools/surelog/bin

['tool', 'surelog', 'vswitch']

--version

['tool', 'surelog', 'version']

>=1.13

['tool', 'surelog', 'regex', 'import', '0', 'warnings']

^\[WRN:

['tool', 'surelog', 'regex', 'import', '0', 'errors']

^\[(ERR|FTL|SNT):

['tool', 'surelog', 'option', 'import', '0']

  • -parse
  • -nocache

['tool', 'surelog', 'output', 'import', '0']

<design>.v

['tool', 'surelog', 'require', 'import', '0']

input,verilog

['tool', 'surelog', 'threads', 'import', '0']

2

9.15. sv2v

sv2v converts SystemVerilog (IEEE 1800-2017) to Verilog (IEEE 1364-2005), with an emphasis on supporting synthesizable language constructs. The primary goal of this project is to create a completely free and open-source tool for converting SystemVerilog to Verilog. While methods for performing this conversion already exist, they generally either rely on commercial tools, or are limited in scope.

Documentation: https://github.com/zachjs/sv2v

Sources: https://github.com/zachjs/sv2v

Installation: https://github.com/zachjs/sv2v

Setup file: sv2v.py

Keypath

Value

['tool', 'sv2v', 'exe']

sv2v

['tool', 'sv2v', 'vswitch']

--numeric-version

['tool', 'sv2v', 'version']

>=0.0.9

['tool', 'sv2v', 'option', <step>, <index>]

  • inputs/<design>.v
  • --write=outputs/<design>.v

['tool', 'sv2v', 'input', <step>, <index>]

<design>.v

['tool', 'sv2v', 'output', <step>, <index>]

<design>.v

['tool', 'sv2v', 'threads', <step>, <index>]

4

9.16. template

Tool description

Documentation:https:// Sources: https:// Installation: https://

Setup file: template.py

Keypath

Value

['tool', 'template', 'vswitch']

-version

['tool', 'template', 'version']

v2.0

['tool', 'template', 'format']

tcl

['tool', 'template', 'option', <step>, <index>]

['tool', 'template', 'refdir', <step>, <index>]

['tool', 'template', 'script', <step>, <index>]

['tool', 'template', 'threads', <step>, <index>]

2

9.17. verilator

Verilator is a free and open-source software tool which converts Verilog (a hardware description language) to a cycle-accurate behavioral model in C++ or SystemC.

9.17.1. Steps supported

import

Preprocesses and pickles Verilog sources. Takes in a set of Verilog source files supplied via ['input', 'verilog'] and reads the following parameters:

Outputs a single Verilog file in outputs/<design>.v.

lint

Lints Verilog source. Takes in a single pickled Verilog file from inputs/<design>.v and produces no outputs. Results of linting can be programatically queried using errors/warnings metrics.

compile

Compiles Verilog and C/C++ sources into an executable. Takes in a single pickled Verilog file from inputs/<design>.v and a set of C/C++ sources from ['input', 'c']. Outputs an executable in outputs/<design>.vexe.

This steps accepts a restricted set of CLI switches in ['tool', 'verilator', 'var', <step>, <index>, 'extraopts'] that are passed through directly to Verilator. Currently supported switches include:

  • --trace

For all steps, this driver runs Verilator using the -sv switch to enable parsing a subset of SystemVerilog features. All steps also support using ['option', 'relax'] to make warnings nonfatal.

Documentation: https://verilator.org/guide/latest

Sources: https://github.com/verilator/verilator

Installation: https://verilator.org/guide/latest/install.html

Setup file: verilator.py

Keypath

Value

['tool', 'verilator', 'exe']

verilator

['tool', 'verilator', 'vswitch']

--version

['tool', 'verilator', 'version']

>=4.028

['tool', 'verilator', 'regex', 'import', <index>, 'warnings']

^\%Warning

['tool', 'verilator', 'regex', 'import', <index>, 'errors']

^\%Error

['tool', 'verilator', 'option', 'import', <index>]

  • -sv
  • --top-module <design>
  • --lint-only
  • --debug

['tool', 'verilator', 'output', 'import', <index>]

<design>.v

['tool', 'verilator', 'require', 'import', <index>]

input,verilog

['tool', 'verilator', 'threads', 'import', <index>]

2

9.18. vivado

Vivado is an FPGA programming tool suite from Xilinx used to program Xilinx devices.

Documentation: https://www.xilinx.com/products/design-tools/vivado.html

Setup file: vivado.py

Keypath

Value

['tool', 'vivado', 'exe']

vivado

['tool', 'vivado', 'vswitch']

-version

['tool', 'vivado', 'vendor']

xilinx

['tool', 'vivado', 'version']

0

['tool', 'vivado', 'option', 'compile', <index>]

-mode batch -source

['tool', 'vivado', 'refdir', 'compile', <index>]

tools/vivado

['tool', 'vivado', 'script', 'compile', <index>]

/compile.tcl

['tool', 'vivado', 'threads', 'compile', <index>]

2

9.19. vpr

VPR (Versatile Place and Route) is an open source CAD tool designed for the exploration of new FPGA architectures and CAD algorithms, at the packing, placement and routing phases of the CAD flow. VPR takes, as input, a description of an FPGA architecture along with a technology-mapped user circuit. It then performs packing, placement, and routing to map the circuit onto the FPGA. The output of VPR includes the FPGA configuration needed to implement the circuit and statistics about the final mapped design (eg. critical path delay, area, etc).

Documentation: https://docs.verilogtorouting.org/en/latest

Sources: https://github.com/verilog-to-routing/vtr-verilog-to-routing

Installation: https://github.com/verilog-to-routing/vtr-verilog-to-routing

Setup file: vpr.py

Keypath

Value

['tool', 'vpr', 'exe']

vpr

['tool', 'vpr', 'version']

0.0

['tool', 'vpr', 'option', 'apr', <index>]

  • inputs/<design>.blif
  • --num_workers 2

['tool', 'vpr', 'output', 'apr', <index>]

  • <design>.net
  • <design>.place
  • <design>.route
  • vpr_stdout.log

['tool', 'vpr', 'threads', 'apr', <index>]

2

9.20. xyce

Xyce is a high performance SPICE-compatible circuit simulator capable capable of solving extremely large circuit problems by supporting large-scale parallel computing platforms. It also supports serial execution on all common desktop platforms, and small-scale parallel runs on Unix-like systems.

Documentation: https://xyce.sandia.gov/documentation

Sources: https://github.com/Xyce/Xyce

Installation: https://xyce.sandia.gov/documentation/BuildingGuide.html

Status: SC integration WIP

Setup file: xyce.py

Keypath

Value

['tool', 'xyce', 'exe']

xyce

['tool', 'xyce', 'version']

0.0

['tool', 'xyce', 'threads', 'spice', <index>]

2

9.21. yosys

Yosys is a framework for RTL synthesis that takes synthesizable Verilog-2005 design and converts it to BLIF, EDIF, BTOR, SMT, Verilog netlist etc. The tool supports logical synthesis and tech mapping to ASIC standard cell libraries, FPGA architectures. In addition it has built in formal methods for property and equivalence checking.

Documentation: http://www.clifford.at/yosys/documentation.html

Sources: https://github.com/YosysHQ/yosys

Installation: https://github.com/YosysHQ/yosys

Setup file: yosys.py

Keypath

Value

['tool', 'yosys', 'exe']

yosys

['tool', 'yosys', 'vswitch']

--version

['tool', 'yosys', 'version']

>=0.13

['tool', 'yosys', 'format']

tcl

['tool', 'yosys', 'regex', 'syn', <index>, 'warnings']

Warning:

['tool', 'yosys', 'regex', 'syn', <index>, 'errors']

^ERROR

['tool', 'yosys', 'option', 'syn', <index>]

-c

['tool', 'yosys', 'input', 'syn', <index>]

<design>.v

['tool', 'yosys', 'output', 'syn', <index>]

  • <design>.vg
  • <design>_netlist.json
  • <design>.blif

['tool', 'yosys', 'require', 'syn', <index>]

fpga,partname

['tool', 'yosys', 'report', 'syn', <index>, 'errors']

syn.log

['tool', 'yosys', 'report', 'syn', <index>, 'warnings']

syn.log

['tool', 'yosys', 'report', 'syn', <index>, 'drvs']

syn.log

['tool', 'yosys', 'report', 'syn', <index>, 'coverage']

syn.log

['tool', 'yosys', 'report', 'syn', <index>, 'security']

syn.log

['tool', 'yosys', 'report', 'syn', <index>, 'luts']

syn.log

['tool', 'yosys', 'report', 'syn', <index>, 'dsps']

syn.log

['tool', 'yosys', 'report', 'syn', <index>, 'brams']

syn.log

['tool', 'yosys', 'report', 'syn', <index>, 'cellarea']

syn.log

['tool', 'yosys', 'report', 'syn', <index>, 'cells']

syn.log

['tool', 'yosys', 'report', 'syn', <index>, 'registers']

syn.log

['tool', 'yosys', 'report', 'syn', <index>, 'buffers']

syn.log

['tool', 'yosys', 'report', 'syn', <index>, 'nets']

syn.log

['tool', 'yosys', 'report', 'syn', <index>, 'pins']

syn.log

['tool', 'yosys', 'refdir', 'syn', <index>]

tools/yosys

['tool', 'yosys', 'script', 'syn', <index>]

sc_syn.tcl