Using Commercial Tools#

SiliconCompiler drives commercial EDA tools as well as open-source ones – the flowgraph does not care which tool a task wraps. What differs is how you get the driver.

Important

Read this first, because the capability tables do not say it. Vivado is the only commercial tool whose driver ships in this repository. Drivers for the Synopsys, Cadence and Siemens tools exist and are in use, but cannot be distributed publicly: a tool driver encodes command lines, script structure and flow knowledge that vendor agreements cover.

So “supported” means the integration exists, not that pip install gives it to you. If you need one of those, ask on Discussions – that is the honest route, and it is a conversation about access rather than something the docs can settle.

Everything else you can drive yourself, using the same mechanisms the built-in drivers use.

Vivado, end to end#

examples/heartbeat targets a Xilinx Artix-7 alongside its ASIC flows:

def fpga(N: Optional[str] = None):
    """Runs the FPGA implementation flow for the Heartbeat design.

    This flow targets a Xilinx Artix-7 FPGA (xc7a100tcsg324) and generates
    a bitstream that can be programmed onto the device.

    Args:
        N (str, optional): The value for the Verilog parameter 'N'.
            Defaults to None, which uses the value set in the design schema.
    """
    # Create a project instance for an FPGA flow.
    project = FPGA()

    # Instantiate and configure the design.
    hb = HeartbeatDesign()
    project.set_design(hb)

    # Add the RTL and FPGA constraint filesets.
    project.add_fileset("rtl")
    project.add_fileset("fpga.xc7a100tcsg324")
    # Specify the Xilinx implementation flow.
    project.set_flow(FPGAXilinxFlow())

    # Configure the specific FPGA part details.
    fpga = FPGADevice("xc7")
    fpga.set_partname("xc7a100tcsg324")
    project.set_fpga(fpga)

    # Optionally override the 'N' parameter.
    if N is not None:
        hb.set_param("N", N, fileset="rtl")

    # Run the FPGA flow (synthesis, place, route, bitstream generation).
    project.run()
    project.summary()

cd examples/heartbeat
smake fpga

FPGAXilinxFlow is the standard Vivado pipeline. SiliconCompiler runs vivado in batch mode, so it has to be on your PATH and your licence has to work – test that outside SiliconCompiler first, because a licence failure surfaces as a tool error in <step>.log rather than as anything more helpful.

Injecting Tcl around a tool#

The most common commercial-tool request is not a new driver at all: it is “I need to run my own Tcl at a specific point” – a vendor-specific constraint, an in-house checking script, an extra report.

Every task takes a pre- and post-script, so you do not have to fork the driver:

from siliconcompiler.tools.vivado.syn_fpga import SynthesisTask

task = SynthesisTask.find_task(project)
task.add_prescript("scripts/my_setup.tcl")     # before the tool's own script
task.add_postscript("scripts/my_reports.tcl")  # after it

The scripts are sourced by the tool in its own interpreter, with the tool’s state already loaded – so a post-script sees the elaborated or placed design and can report on it. Both are per-node, so step=/index= narrows them to one point in the flow:

task.add_postscript("scripts/check.tcl", step="synthesis")

That is the answer to “how do I get my Tcl between synthesis and implementation”: attach it to the step it belongs after.

Writing a driver#

For a tool with no driver at all, a task class is the unit of work. Building a Tool is the reference; the shape is four optional methods:

Method	Does
`setup()`	Declares what the task needs and produces – inputs, outputs, required files, the tool and version
`pre_process()`	Runs before the tool: stage files, generate a script
`runtime_options()`	Builds the command line
`post_process()`	Reads the tool’s reports and records metrics

post_process() is the one people underestimate. A driver that runs a tool but records no metrics gives you a build you cannot gate on – no checklist can check it, and the summary table has nothing to show. Read an existing driver before writing yours; the OpenROAD and Yosys ones are the most complete.

Keeping it private#

A driver for a licensed tool usually cannot go in this repository, and it does not need to. Package it as your own pip-installable module and register it through entry points – Packaging an External Library covers the layout, the pyproject.toml, a proprietary licence identifier, and the environment-variable dataroot pattern for reference data that must not enter a wheel.

Where does my module go? is the one-page version of that decision.