7. Tools directory
7.1. bambu
The primary objective of the PandA project is to develop a usable framework that will enable the research of new ideas in the HW-SW Co-Design field.
The PandA framework includes methodologies supporting the research on high-level synthesis of hardware accelerators, on parallelism extraction for embedded systems, on hardware/software partitioning and mapping, on metrics for performance estimation of embedded software applications and on dynamic reconfigurable devices.
Documentation: https://github.com/ferrandi/PandA-bambu
Sources: https://github.com/ferrandi/PandA-bambu
Installation: https://panda.dei.polimi.it/?page_id=88
Setup file: bambu.py
Keypath |
Value |
bambu |
|
--version |
|
>=0.9.6 |
7.1.1. import
Performs high level synthesis to generate a verilog output
Setup file: import.py
7.1.1.1. Configuration
Keypath |
Value |
|
|
|
|
tools/bambu |
|
2 |
7.2. bluespec
Bluespec is a high-level hardware description language. It has a variety of advanced features including a powerful type system that can prevent errors prior to synthesis time, and its most distinguishing feature, Guarded Atomic Actions, allow you to define hardware components in a modular manner based on their invariants, and let the compiler pick a scheduler.
Documentation: https://github.com/B-Lang-org/bsc#documentation
Sources: https://github.com/B-Lang-org/bsc
Installation: https://github.com/B-Lang-org/bsc#download
Setup file: bluespec.py
Keypath |
Value |
bsc |
|
-v |
|
>=2021.07 |
7.2.1. import
Performs high level synthesis to generate a verilog output
Setup file: import.py
7.2.1.1. Configuration
Keypath |
Value |
|
|
|
|
tools/bluespec |
|
2 |
7.3. chisel
Chisel is a hardware design language that facilitates advanced circuit generation and design reuse for both ASIC and FPGA digital logic designs. Chisel adds hardware construction primitives to the Scala programming language, providing designers with the power of a modern programming language to write complex, parameterizable circuit generators that produce synthesizable Verilog.
Documentation: https://www.chisel-lang.org/chisel3/docs/introduction.html
Sources: https://github.com/chipsalliance/chisel
Installation: The Chisel plugin relies on having the Scala Build Tool (sbt) installed. Instructions: https://www.scala-sbt.org/download.html.
Setup file: chisel.py
Keypath |
Value |
sbt |
|
--version |
|
>=1.5.5 |
7.3.1. import
Performs high level synthesis to generate a verilog output
Setup file: import.py
7.3.1.1. Configuration
Keypath |
Value |
"runMain SCDriver --module <design> -o ../outputs/<design>.v" |
|
|
|
tools/chisel |
|
|
|
2 |
7.4. genfasm
Generate a FSAM file from the output of VPR
Documentation: https://docs.verilogtorouting.org/en/latest/utils/fasm/
Sources: https://github.com/verilog-to-routing/vtr-verilog-to-routing/tree/master/utils/fasm
Setup file: genfasm.py
Keypath |
Value |
genfasm |
|
0.0 |
7.4.1. bitstream
Generates a bitstream
Setup file: bitstream.py
7.4.1.1. Configuration
Keypath |
Value |
|
|
2 |
7.5. ghdl
GHDL is an open-source analyzer, compiler, simulator and (experimental) synthesizer for VHDL. It allows you to analyse and elaborate sources for generating machine code from your design. Native program execution is the only way for high speed simulation.
Documentation: https://ghdl.readthedocs.io/en/latest
Sources: https://github.com/ghdl/ghdl
Installation: https://github.com/ghdl/ghdl
Setup file: ghdl.py
Keypath |
Value |
ghdl |
|
--version |
|
>=2.0.0-dev |
7.5.1. import
Imports VHDL and converts it to verilog
Setup file: import.py
7.5.1.1. Configuration
Keypath |
Value |
|
|
<design>.v |
|
output |
|
v |
|
|
|
2 |
7.6. icarus
Icarus is a verilog simulator with full support for Verilog IEEE-1364. Icarus can simulate synthesizable as well as behavioral Verilog.
Documentation: https://steveicarus.github.io/iverilog/
Sources: https://github.com/steveicarus/iverilog
Installation: https://github.com/steveicarus/iverilog
Setup file: icarus.py
Keypath |
Value |
iverilog |
|
-V |
|
>=10.3 |
7.6.1. compile
Compile the input verilog into a vvp file that can be simulated.
Setup file: compile.py
7.6.1.1. Configuration
Keypath |
Value |
-o outputs/<design>.vvp |
|
|
|
2 |
7.7. icepack
Icepack converts an ASCII bitstream file to a .bin file for the ICE40 FPGA.
Documentation: https://clifford.at/icestorm
Sources: https://github.com/YosysHQ/icestorm
Installation: https://github.com/YosysHQ/icestorm
Setup file: icepack.py
Keypath |
Value |
icepack |
7.7.1. bitstream
Generate a bitstream for the ICE40 FPGA
Setup file: bitstream.py
7.7.1.1. Configuration
Keypath |
Value |
|
|
<design>.asc |
|
<design>.bit |
7.8. klayout
Klayout is a production grade viewer and editor of GDSII and Oasis data with customizable Python and Ruby interfaces.
Documentation: https://www.klayout.de
Sources: https://github.com/KLayout/klayout
Installation: https://www.klayout.de/build.html
Setup file: klayout.py
Keypath |
Value |
klayout |
|
|
|
>=0.27.6 |
|
json |
7.8.1. export
Generate a GDSII file from an input DEF file
Setup file: export.py
Built using target: freepdk45_demo
7.8.1.1. Configuration
Keypath |
Value |
(WARNING|warning) |
|
ERROR |
|
|
|
true |
|
true |
|
|
4096 |
|
4096 |
<design>.def |
|
<design>.gds |
|
|
|
tools/klayout |
|
klayout_export.py |
7.8.1.2. Variables
Parameters |
Help |
Export GDSII with timestamps |
|
true/false: true will cause KLayout to generate a screenshot of the layout |
|
List of layers to hide |
|
Screenshot horizontal resolution in pixels |
|
Screenshot vertical resolution in pixels |
7.8.2. screenshot
Generate a PNG file from a layout file
Setup file: screenshot.py
Built using target: freepdk45_demo
7.8.2.1. Configuration
Keypath |
Value |
|
(WARNING|warning) |
|
ERROR |
|
|
|
<path> |
|
true |
|
4096 |
|
4096 |
<design>.png |
|
tool,klayout,task,screenshot,var,show_filepath |
|
tools/klayout |
|
klayout_show.py |
7.8.2.2. Variables
Parameters |
Help |
File to open |
|
true/false: true will cause kLayout to exit when complete |
|
List of layers to hide |
|
File type to look for in the inputs |
|
Horizontal resolution in pixels |
|
Vertical resolution in pixels |
7.8.3. show
Show a layout in kLayout
Setup file: show.py
Built using target: freepdk45_demo
7.8.3.1. Configuration
Keypath |
Value |
(WARNING|warning) |
|
ERROR |
|
|
|
<path> |
|
false |
|
tool,klayout,task,show,var,show_filepath |
|
tools/klayout |
|
klayout_show.py |
7.8.3.2. Variables
Parameters |
Help |
File to open |
|
true/false: true will cause kLayout to exit when complete |
|
List of layers to hide |
|
File type to look for in the inputs |
7.9. magic
Magic is a chip layout viewer, editor, and circuit verifier with built in DRC and LVS engines.
Documentation: http://opencircuitdesign.com/magic/userguide.html
Installation: https://github.com/RTimothyEdwards/magic
Sources: https://github.com/RTimothyEdwards/magic
Setup file: magic.py
Keypath |
Value |
magic |
|
--version |
|
>=8.3.196 |
|
tcl |
7.9.1. drc
Perform DRC checks
Setup file: drc.py
Built using target: freepdk45_demo
7.9.1.1. Configuration
Keypath |
Value |
^Error |
|
warning |
|
|
|
<design>.gds |
|
tools/magic |
|
sc_magic.tcl |
|
2 |
7.9.2. extspice
Extract spice netlists from a GDS file for simulation use
Setup file: extspice.py
Built using target: freepdk45_demo
7.9.2.1. Configuration
Keypath |
Value |
^Error |
|
warning |
|
|
|
<design>.gds |
|
<design>.spice |
|
tools/magic |
|
sc_magic.tcl |
|
2 |
7.10. netgen
Netgen is a tool for comparing netlists. By comparing a Verilog netlist with one extracted from a circuit layout, it can be used to perform LVS verification.
Documentation: http://www.opencircuitdesign.com/netgen/
Installation: https://github.com/RTimothyEdwards/netgen
Sources: https://github.com/RTimothyEdwards/netgen
Setup file: netgen.py
Keypath |
Value |
netgen |
|
-batch |
|
>=1.5.192 |
|
tcl |
7.10.1. lvs
Perform LVS on the supplied netlists
Setup file: lvs.py
7.10.1.1. Configuration
Keypath |
Value |
^Warning: |
|
|
|
|
|
errors |
|
tools/netgen |
|
sc_lvs.tcl |
|
2 |
7.11. nextpnr
nextpnr is a vendor neutral FPGA place and route tool with support for the ICE40, ECP5, and Nexus devices from Lattice.
Documentation: https://github.com/YosysHQ/nextpnr
Sources: https://github.com/YosysHQ/nextpnr
Installation: https://github.com/YosysHQ/nextpnr
Setup file: nextpnr.py
Keypath |
Value |
nextpnr-ice40 |
|
--version |
|
>=0.2 |
7.11.1. apr
Perform automated place and route on FPGAs
Setup file: apr.py
7.11.1.1. Configuration
Keypath |
Value |
|
|
<design>_netlist.json |
|
<design>.asc |
7.12. openfpgaloader
The OpenFPGALoader is a universal utility for programming FPGAs. Compatible with many boards, cables and FPGA from major manufacturers (Xilinx, Altera/Intel, Lattice, Gowin, Efinix, Anlogic). openFPGALoader works on Linux, Windows and macOS.
Documentation: https://github.com/trabucayre/openFPGALoader
Sources: https://github.com/trabucayre/openFPGALoader
Installation: https://github.com/trabucayre/openFPGALoader
Status: SC integration WIP
Setup file: openfpgaloader.py
Keypath |
Value |
openfpgaloader |
|
--Version |
|
0.5.0 |
7.13. openroad
OpenROAD is an automated physical design platform for integrated circuit design with a complete set of features needed to translate a synthesized netlist to a tapeout ready GDSII.
Documentation: https://openroad.readthedocs.io/
Sources: https://github.com/The-OpenROAD-Project/OpenROAD
Installation: https://github.com/The-OpenROAD-Project/OpenROAD
Setup file: openroad.py
Keypath |
Value |
openroad |
|
-version |
|
>=v2.0-7069 |
|
tcl |
7.13.1. cts
Perform clock tree synthesis and timing repair
Setup file: cts.py
Built using target: asap7_demo
7.13.1.1. Configuration
7.13.1.2. Variables
Parameters |
Help |
list of timing corners to use |
|
list of parasitic extraction corners to use |
|
corner to use for power analysis |
|
global placement density (0.0 - 1.0) |
|
global placement cell padding in number of sites |
|
detailed placement cell padding in number of sites |
|
macro halo to use when performing automated macro placement ([x, y] in microns) |
|
macro channel to use when performing automated macro placement ([x, y] in microns) |
|
list of default vias to use for detail routing |
|
list of layers to treat as unidirectional regardless of what the tech lef specifies |
|
maximum distance between tie high/low cells in microns |
|
true/false, when true enables power grid generation |
|
true/false, when true global placement will consider the routability of the design |
|
true/false, when true global placement will consider the timing performance of the design |
|
true/false, when true the detailed placement optimization will be performed |
|
maximum cell movement in detailed placement optimization in microns, 0 will result in the tool default maximum displacement |
|
maximum cell movement in detailed placement in microns, 0 will result in the tool default maximum displacement |
|
maximum distance between buffers during clock tree synthesis in microns |
|
clusting distance to use during clock tree synthesis in microns |
|
number of instances in a cluster to use during clock tree synthesis |
|
perform level balancing in clock tree synthesis |
|
maximum number of repair iterations to use during antenna repairs |
|
adds a margin to the antenna ratios (0 - 100) |
|
true, false, when true perform pin access before global routing |
|
maximum number of iterations to use in flobal routing when attempting to solve overflow |
|
macro extension distance in number of gcells, this can be useful when the detailed router needs additional space to avoid DRCs |
|
true/false, when true allow global routing to finish with congestion |
|
true/false, when true allow global routing to finish with overflow |
|
minimum layer to use for global routing of signals |
|
maximum layer to use for global routing of signals |
|
minimum layer to use for global routing of clock nets |
|
maximum layer to use for global routing of clock nets |
|
true/false, when true turns off via generation in detailed router and only uses the specified tech vias |
|
false or value, when set this specifies to the detailed router the specific process node |
|
false or value, TODO |
|
false or value, TODO |
|
false or value, TODO |
|
true/false, when true performs a via ripup step after detailed routing to remove power vias that are causing DRC violations |
|
specifies the margin to apply when performing setup repair in library timing units |
|
specifies the margin to apply when performing hold repair in library timing units |
|
specifies the amount of margin to apply to max slew repairs in percent (0 - 100) |
|
specifies the amount of margin to apply to max capacitance repairs in percent (0 - 100) |
|
true/false, when true enables adding buffers to the input ports |
|
true/false, when true enables adding buffers to the output ports |
|
timing derating factor to use for hold corners |
|
timing derating factor to use for setup corners |
|
true/false, when true enables adding fill, if enabled by the PDK, to the design |
|
true/false, when true enables IR drop analysis |
|
list of “tool key level” to enable debugging of OpenROAD |
7.13.1.3. Files
Parameters |
Help |
tap cell insertion script |
|
file used to specify the parasitics for estimation |
|
list of files to use for power grid generation |
|
list of files to use for specifying global connections |
|
script to generate a padring using ICeWall in OpenROAD |
|
script constrain pin placement |
7.13.2. dfm
Design for manufacturing step will insert fill if specified
Setup file: dfm.py
Built using target: asap7_demo
7.13.2.1. Configuration
7.13.2.2. Variables
Parameters |
Help |
list of timing corners to use |
|
list of parasitic extraction corners to use |
|
corner to use for power analysis |
|
global placement density (0.0 - 1.0) |
|
global placement cell padding in number of sites |
|
detailed placement cell padding in number of sites |
|
macro halo to use when performing automated macro placement ([x, y] in microns) |
|
macro channel to use when performing automated macro placement ([x, y] in microns) |
|
list of default vias to use for detail routing |
|
list of layers to treat as unidirectional regardless of what the tech lef specifies |
|
maximum distance between tie high/low cells in microns |
|
true/false, when true enables power grid generation |
|
true/false, when true global placement will consider the routability of the design |
|
true/false, when true global placement will consider the timing performance of the design |
|
true/false, when true the detailed placement optimization will be performed |
|
maximum cell movement in detailed placement optimization in microns, 0 will result in the tool default maximum displacement |
|
maximum cell movement in detailed placement in microns, 0 will result in the tool default maximum displacement |
|
maximum distance between buffers during clock tree synthesis in microns |
|
clusting distance to use during clock tree synthesis in microns |
|
number of instances in a cluster to use during clock tree synthesis |
|
perform level balancing in clock tree synthesis |
|
maximum number of repair iterations to use during antenna repairs |
|
adds a margin to the antenna ratios (0 - 100) |
|
true, false, when true perform pin access before global routing |
|
maximum number of iterations to use in flobal routing when attempting to solve overflow |
|
macro extension distance in number of gcells, this can be useful when the detailed router needs additional space to avoid DRCs |
|
true/false, when true allow global routing to finish with congestion |
|
true/false, when true allow global routing to finish with overflow |
|
minimum layer to use for global routing of signals |
|
maximum layer to use for global routing of signals |
|
minimum layer to use for global routing of clock nets |
|
maximum layer to use for global routing of clock nets |
|
true/false, when true turns off via generation in detailed router and only uses the specified tech vias |
|
false or value, when set this specifies to the detailed router the specific process node |
|
false or value, TODO |
|
false or value, TODO |
|
false or value, TODO |
|
true/false, when true performs a via ripup step after detailed routing to remove power vias that are causing DRC violations |
|
specifies the margin to apply when performing setup repair in library timing units |
|
specifies the margin to apply when performing hold repair in library timing units |
|
specifies the amount of margin to apply to max slew repairs in percent (0 - 100) |
|
specifies the amount of margin to apply to max capacitance repairs in percent (0 - 100) |
|
true/false, when true enables adding buffers to the input ports |
|
true/false, when true enables adding buffers to the output ports |
|
timing derating factor to use for hold corners |
|
timing derating factor to use for setup corners |
|
true/false, when true enables adding fill, if enabled by the PDK, to the design |
|
true/false, when true enables IR drop analysis |
|
list of “tool key level” to enable debugging of OpenROAD |
7.13.2.3. Files
Parameters |
Help |
tap cell insertion script |
|
file used to specify the parasitics for estimation |
|
list of files to use for power grid generation |
|
list of files to use for specifying global connections |
|
script to generate a padring using ICeWall in OpenROAD |
|
script constrain pin placement |
7.13.3. export
Generate abstract views (LEF), timing libraries (liberty files), circuit descriptions (CDL), and parasitic annotation files (SPEF)
Setup file: export.py
Built using target: asap7_demo
7.13.3.1. Configuration
7.13.3.2. Variables
Parameters |
Help |
list of timing corners to use |
|
list of parasitic extraction corners to use |
|
corner to use for power analysis |
|
global placement density (0.0 - 1.0) |
|
global placement cell padding in number of sites |
|
detailed placement cell padding in number of sites |
|
macro halo to use when performing automated macro placement ([x, y] in microns) |
|
macro channel to use when performing automated macro placement ([x, y] in microns) |
|
list of default vias to use for detail routing |
|
list of layers to treat as unidirectional regardless of what the tech lef specifies |
|
maximum distance between tie high/low cells in microns |
|
true/false, when true enables power grid generation |
|
true/false, when true global placement will consider the routability of the design |
|
true/false, when true global placement will consider the timing performance of the design |
|
true/false, when true the detailed placement optimization will be performed |
|
maximum cell movement in detailed placement optimization in microns, 0 will result in the tool default maximum displacement |
|
maximum cell movement in detailed placement in microns, 0 will result in the tool default maximum displacement |
|
maximum distance between buffers during clock tree synthesis in microns |
|
clusting distance to use during clock tree synthesis in microns |
|
number of instances in a cluster to use during clock tree synthesis |
|
perform level balancing in clock tree synthesis |
|
maximum number of repair iterations to use during antenna repairs |
|
adds a margin to the antenna ratios (0 - 100) |
|
true, false, when true perform pin access before global routing |
|
maximum number of iterations to use in flobal routing when attempting to solve overflow |
|
macro extension distance in number of gcells, this can be useful when the detailed router needs additional space to avoid DRCs |
|
true/false, when true allow global routing to finish with congestion |
|
true/false, when true allow global routing to finish with overflow |
|
minimum layer to use for global routing of signals |
|
maximum layer to use for global routing of signals |
|
minimum layer to use for global routing of clock nets |
|
maximum layer to use for global routing of clock nets |
|
true/false, when true turns off via generation in detailed router and only uses the specified tech vias |
|
false or value, when set this specifies to the detailed router the specific process node |
|
false or value, TODO |
|
false or value, TODO |
|
false or value, TODO |
|
true/false, when true performs a via ripup step after detailed routing to remove power vias that are causing DRC violations |
|
specifies the margin to apply when performing setup repair in library timing units |
|
specifies the margin to apply when performing hold repair in library timing units |
|
specifies the amount of margin to apply to max slew repairs in percent (0 - 100) |
|
specifies the amount of margin to apply to max capacitance repairs in percent (0 - 100) |
|
true/false, when true enables adding buffers to the input ports |
|
true/false, when true enables adding buffers to the output ports |
|
timing derating factor to use for hold corners |
|
timing derating factor to use for setup corners |
|
true/false, when true enables adding fill, if enabled by the PDK, to the design |
|
true/false, when true enables IR drop analysis |
|
list of “tool key level” to enable debugging of OpenROAD |
|
true/false, when true enables writing the CDL file for the design |
7.13.3.3. Files
Parameters |
Help |
tap cell insertion script |
|
file used to specify the parasitics for estimation |
|
list of files to use for power grid generation |
|
list of files to use for specifying global connections |
|
script to generate a padring using ICeWall in OpenROAD |
|
script constrain pin placement |
7.13.4. floorplan
Perform floorplanning, pin placements, macro placements and power grid generation
Setup file: floorplan.py
Built using target: asap7_demo
7.13.4.1. Configuration
7.13.4.2. Variables
Parameters |
Help |
list of timing corners to use |
|
list of parasitic extraction corners to use |
|
corner to use for power analysis |
|
global placement density (0.0 - 1.0) |
|
global placement cell padding in number of sites |
|
detailed placement cell padding in number of sites |
|
macro halo to use when performing automated macro placement ([x, y] in microns) |
|
macro channel to use when performing automated macro placement ([x, y] in microns) |
|
list of default vias to use for detail routing |
|
list of layers to treat as unidirectional regardless of what the tech lef specifies |
|
maximum distance between tie high/low cells in microns |
|
true/false, when true enables power grid generation |
|
true/false, when true global placement will consider the routability of the design |
|
true/false, when true global placement will consider the timing performance of the design |
|
true/false, when true the detailed placement optimization will be performed |
|
maximum cell movement in detailed placement optimization in microns, 0 will result in the tool default maximum displacement |
|
maximum cell movement in detailed placement in microns, 0 will result in the tool default maximum displacement |
|
maximum distance between buffers during clock tree synthesis in microns |
|
clusting distance to use during clock tree synthesis in microns |
|
number of instances in a cluster to use during clock tree synthesis |
|
perform level balancing in clock tree synthesis |
|
maximum number of repair iterations to use during antenna repairs |
|
adds a margin to the antenna ratios (0 - 100) |
|
true, false, when true perform pin access before global routing |
|
maximum number of iterations to use in flobal routing when attempting to solve overflow |
|
macro extension distance in number of gcells, this can be useful when the detailed router needs additional space to avoid DRCs |
|
true/false, when true allow global routing to finish with congestion |
|
true/false, when true allow global routing to finish with overflow |
|
minimum layer to use for global routing of signals |
|
maximum layer to use for global routing of signals |
|
minimum layer to use for global routing of clock nets |
|
maximum layer to use for global routing of clock nets |
|
true/false, when true turns off via generation in detailed router and only uses the specified tech vias |
|
false or value, when set this specifies to the detailed router the specific process node |
|
false or value, TODO |
|
false or value, TODO |
|
false or value, TODO |
|
true/false, when true performs a via ripup step after detailed routing to remove power vias that are causing DRC violations |
|
specifies the margin to apply when performing setup repair in library timing units |
|
specifies the margin to apply when performing hold repair in library timing units |
|
specifies the amount of margin to apply to max slew repairs in percent (0 - 100) |
|
specifies the amount of margin to apply to max capacitance repairs in percent (0 - 100) |
|
true/false, when true enables adding buffers to the input ports |
|
true/false, when true enables adding buffers to the output ports |
|
timing derating factor to use for hold corners |
|
timing derating factor to use for setup corners |
|
true/false, when true enables adding fill, if enabled by the PDK, to the design |
|
true/false, when true enables IR drop analysis |
|
list of “tool key level” to enable debugging of OpenROAD |
7.13.4.3. Files
Parameters |
Help |
tap cell insertion script |
|
file used to specify the parasitics for estimation |
|
list of files to use for power grid generation |
|
list of files to use for specifying global connections |
|
script to insert the padring |
|
script constrain pin placement |
7.13.5. physyn
Not implemented yet
Setup file: physyn.py
Built using target: asap7_demo
7.13.5.1. Configuration
7.13.5.2. Variables
Parameters |
Help |
list of timing corners to use |
|
list of parasitic extraction corners to use |
|
corner to use for power analysis |
|
global placement density (0.0 - 1.0) |
|
global placement cell padding in number of sites |
|
detailed placement cell padding in number of sites |
|
macro halo to use when performing automated macro placement ([x, y] in microns) |
|
macro channel to use when performing automated macro placement ([x, y] in microns) |
|
list of default vias to use for detail routing |
|
list of layers to treat as unidirectional regardless of what the tech lef specifies |
|
maximum distance between tie high/low cells in microns |
|
true/false, when true enables power grid generation |
|
true/false, when true global placement will consider the routability of the design |
|
true/false, when true global placement will consider the timing performance of the design |
|
true/false, when true the detailed placement optimization will be performed |
|
maximum cell movement in detailed placement optimization in microns, 0 will result in the tool default maximum displacement |
|
maximum cell movement in detailed placement in microns, 0 will result in the tool default maximum displacement |
|
maximum distance between buffers during clock tree synthesis in microns |
|
clusting distance to use during clock tree synthesis in microns |
|
number of instances in a cluster to use during clock tree synthesis |
|
perform level balancing in clock tree synthesis |
|
maximum number of repair iterations to use during antenna repairs |
|
adds a margin to the antenna ratios (0 - 100) |
|
true, false, when true perform pin access before global routing |
|
maximum number of iterations to use in flobal routing when attempting to solve overflow |
|
macro extension distance in number of gcells, this can be useful when the detailed router needs additional space to avoid DRCs |
|
true/false, when true allow global routing to finish with congestion |
|
true/false, when true allow global routing to finish with overflow |
|
minimum layer to use for global routing of signals |
|
maximum layer to use for global routing of signals |
|
minimum layer to use for global routing of clock nets |
|
maximum layer to use for global routing of clock nets |
|
true/false, when true turns off via generation in detailed router and only uses the specified tech vias |
|
false or value, when set this specifies to the detailed router the specific process node |
|
false or value, TODO |
|
false or value, TODO |
|
false or value, TODO |
|
true/false, when true performs a via ripup step after detailed routing to remove power vias that are causing DRC violations |
|
specifies the margin to apply when performing setup repair in library timing units |
|
specifies the margin to apply when performing hold repair in library timing units |
|
specifies the amount of margin to apply to max slew repairs in percent (0 - 100) |
|
specifies the amount of margin to apply to max capacitance repairs in percent (0 - 100) |
|
true/false, when true enables adding buffers to the input ports |
|
true/false, when true enables adding buffers to the output ports |
|
timing derating factor to use for hold corners |
|
timing derating factor to use for setup corners |
|
true/false, when true enables adding fill, if enabled by the PDK, to the design |
|
true/false, when true enables IR drop analysis |
|
list of “tool key level” to enable debugging of OpenROAD |
7.13.5.3. Files
Parameters |
Help |
tap cell insertion script |
|
file used to specify the parasitics for estimation |
|
list of files to use for power grid generation |
|
list of files to use for specifying global connections |
|
script to generate a padring using ICeWall in OpenROAD |
|
script constrain pin placement |
7.13.6. place
Perform global and detail placements along with design violation repairs
Setup file: place.py
Built using target: asap7_demo
7.13.6.1. Configuration
7.13.6.2. Variables
Parameters |
Help |
list of timing corners to use |
|
list of parasitic extraction corners to use |
|
corner to use for power analysis |
|
global placement density (0.0 - 1.0) |
|
global placement cell padding in number of sites |
|
detailed placement cell padding in number of sites |
|
macro halo to use when performing automated macro placement ([x, y] in microns) |
|
macro channel to use when performing automated macro placement ([x, y] in microns) |
|
list of default vias to use for detail routing |
|
list of layers to treat as unidirectional regardless of what the tech lef specifies |
|
maximum distance between tie high/low cells in microns |
|
true/false, when true enables power grid generation |
|
true/false, when true global placement will consider the routability of the design |
|
true/false, when true global placement will consider the timing performance of the design |
|
true/false, when true the detailed placement optimization will be performed |
|
maximum cell movement in detailed placement optimization in microns, 0 will result in the tool default maximum displacement |
|
maximum cell movement in detailed placement in microns, 0 will result in the tool default maximum displacement |
|
maximum distance between buffers during clock tree synthesis in microns |
|
clusting distance to use during clock tree synthesis in microns |
|
number of instances in a cluster to use during clock tree synthesis |
|
perform level balancing in clock tree synthesis |
|
maximum number of repair iterations to use during antenna repairs |
|
adds a margin to the antenna ratios (0 - 100) |
|
true, false, when true perform pin access before global routing |
|
maximum number of iterations to use in flobal routing when attempting to solve overflow |
|
macro extension distance in number of gcells, this can be useful when the detailed router needs additional space to avoid DRCs |
|
true/false, when true allow global routing to finish with congestion |
|
true/false, when true allow global routing to finish with overflow |
|
minimum layer to use for global routing of signals |
|
maximum layer to use for global routing of signals |
|
minimum layer to use for global routing of clock nets |
|
maximum layer to use for global routing of clock nets |
|
true/false, when true turns off via generation in detailed router and only uses the specified tech vias |
|
false or value, when set this specifies to the detailed router the specific process node |
|
false or value, TODO |
|
false or value, TODO |
|
false or value, TODO |
|
true/false, when true performs a via ripup step after detailed routing to remove power vias that are causing DRC violations |
|
specifies the margin to apply when performing setup repair in library timing units |
|
specifies the margin to apply when performing hold repair in library timing units |
|
specifies the amount of margin to apply to max slew repairs in percent (0 - 100) |
|
specifies the amount of margin to apply to max capacitance repairs in percent (0 - 100) |
|
true/false, when true enables adding buffers to the input ports |
|
true/false, when true enables adding buffers to the output ports |
|
timing derating factor to use for hold corners |
|
timing derating factor to use for setup corners |
|
true/false, when true enables adding fill, if enabled by the PDK, to the design |
|
true/false, when true enables IR drop analysis |
|
list of “tool key level” to enable debugging of OpenROAD |
7.13.6.3. Files
Parameters |
Help |
tap cell insertion script |
|
file used to specify the parasitics for estimation |
|
list of files to use for power grid generation |
|
list of files to use for specifying global connections |
|
script to generate a padring using ICeWall in OpenROAD |
|
script constrain pin placement |
7.13.7. route
Performs filler insertion, global routing, antenna repair, and detailed routing
Setup file: route.py
Built using target: asap7_demo
7.13.7.1. Configuration
7.13.7.2. Variables
Parameters |
Help |
list of timing corners to use |
|
list of parasitic extraction corners to use |
|
corner to use for power analysis |
|
global placement density (0.0 - 1.0) |
|
global placement cell padding in number of sites |
|
detailed placement cell padding in number of sites |
|
macro halo to use when performing automated macro placement ([x, y] in microns) |
|
macro channel to use when performing automated macro placement ([x, y] in microns) |
|
list of default vias to use for detail routing |
|
list of layers to treat as unidirectional regardless of what the tech lef specifies |
|
maximum distance between tie high/low cells in microns |
|
true/false, when true enables power grid generation |
|
true/false, when true global placement will consider the routability of the design |
|
true/false, when true global placement will consider the timing performance of the design |
|
true/false, when true the detailed placement optimization will be performed |
|
maximum cell movement in detailed placement optimization in microns, 0 will result in the tool default maximum displacement |
|
maximum cell movement in detailed placement in microns, 0 will result in the tool default maximum displacement |
|
maximum distance between buffers during clock tree synthesis in microns |
|
clusting distance to use during clock tree synthesis in microns |
|
number of instances in a cluster to use during clock tree synthesis |
|
perform level balancing in clock tree synthesis |
|
maximum number of repair iterations to use during antenna repairs |
|
adds a margin to the antenna ratios (0 - 100) |
|
true, false, when true perform pin access before global routing |
|
maximum number of iterations to use in flobal routing when attempting to solve overflow |
|
macro extension distance in number of gcells, this can be useful when the detailed router needs additional space to avoid DRCs |
|
true/false, when true allow global routing to finish with congestion |
|
true/false, when true allow global routing to finish with overflow |
|
minimum layer to use for global routing of signals |
|
maximum layer to use for global routing of signals |
|
minimum layer to use for global routing of clock nets |
|
maximum layer to use for global routing of clock nets |
|
true/false, when true turns off via generation in detailed router and only uses the specified tech vias |
|
false or value, when set this specifies to the detailed router the specific process node |
|
false or value, TODO |
|
false or value, TODO |
|
false or value, TODO |
|
true/false, when true performs a via ripup step after detailed routing to remove power vias that are causing DRC violations |
|
specifies the margin to apply when performing setup repair in library timing units |
|
specifies the margin to apply when performing hold repair in library timing units |
|
specifies the amount of margin to apply to max slew repairs in percent (0 - 100) |
|
specifies the amount of margin to apply to max capacitance repairs in percent (0 - 100) |
|
true/false, when true enables adding buffers to the input ports |
|
true/false, when true enables adding buffers to the output ports |
|
timing derating factor to use for hold corners |
|
timing derating factor to use for setup corners |
|
true/false, when true enables adding fill, if enabled by the PDK, to the design |
|
true/false, when true enables IR drop analysis |
|
list of “tool key level” to enable debugging of OpenROAD |
7.13.7.3. Files
Parameters |
Help |
tap cell insertion script |
|
file used to specify the parasitics for estimation |
|
list of files to use for power grid generation |
|
list of files to use for specifying global connections |
|
script to generate a padring using ICeWall in OpenROAD |
|
script constrain pin placement |
7.13.8. screenshot
Generate a PNG file from a layout file
Setup file: screenshot.py
Built using target: asap7_demo
7.13.8.1. Configuration
7.13.8.2. Variables
Parameters |
Help |
Task script variables specified as key value pairs. Variable names and value types must match the name and type of task and reference script consuming the variable. |
|
list of timing corners to use |
|
list of parasitic extraction corners to use |
|
corner to use for power analysis |
|
global placement density (0.0 - 1.0) |
|
global placement cell padding in number of sites |
|
detailed placement cell padding in number of sites |
|
macro halo to use when performing automated macro placement ([x, y] in microns) |
|
macro channel to use when performing automated macro placement ([x, y] in microns) |
|
list of default vias to use for detail routing |
|
list of layers to treat as unidirectional regardless of what the tech lef specifies |
|
maximum distance between tie high/low cells in microns |
|
true/false, when true enables power grid generation |
|
true/false, when true global placement will consider the routability of the design |
|
true/false, when true global placement will consider the timing performance of the design |
|
true/false, when true the detailed placement optimization will be performed |
|
maximum cell movement in detailed placement optimization in microns, 0 will result in the tool default maximum displacement |
|
maximum cell movement in detailed placement in microns, 0 will result in the tool default maximum displacement |
|
maximum distance between buffers during clock tree synthesis in microns |
|
clusting distance to use during clock tree synthesis in microns |
|
number of instances in a cluster to use during clock tree synthesis |
|
perform level balancing in clock tree synthesis |
|
maximum number of repair iterations to use during antenna repairs |
|
adds a margin to the antenna ratios (0 - 100) |
|
true, false, when true perform pin access before global routing |
|
maximum number of iterations to use in flobal routing when attempting to solve overflow |
|
macro extension distance in number of gcells, this can be useful when the detailed router needs additional space to avoid DRCs |
|
true/false, when true allow global routing to finish with congestion |
|
true/false, when true allow global routing to finish with overflow |
|
minimum layer to use for global routing of signals |
|
maximum layer to use for global routing of signals |
|
minimum layer to use for global routing of clock nets |
|
maximum layer to use for global routing of clock nets |
|
true/false, when true turns off via generation in detailed router and only uses the specified tech vias |
|
false or value, when set this specifies to the detailed router the specific process node |
|
false or value, TODO |
|
false or value, TODO |
|
false or value, TODO |
|
true/false, when true performs a via ripup step after detailed routing to remove power vias that are causing DRC violations |
|
specifies the margin to apply when performing setup repair in library timing units |
|
specifies the margin to apply when performing hold repair in library timing units |
|
specifies the amount of margin to apply to max slew repairs in percent (0 - 100) |
|
specifies the amount of margin to apply to max capacitance repairs in percent (0 - 100) |
|
true/false, when true enables adding buffers to the input ports |
|
true/false, when true enables adding buffers to the output ports |
|
timing derating factor to use for hold corners |
|
timing derating factor to use for setup corners |
|
true/false, when true enables adding fill, if enabled by the PDK, to the design |
|
true/false, when true enables IR drop analysis |
|
list of “tool key level” to enable debugging of OpenROAD |
|
Task script variables specified as key value pairs. Variable names and value types must match the name and type of task and reference script consuming the variable. |
|
Task script variables specified as key value pairs. Variable names and value types must match the name and type of task and reference script consuming the variable. |
7.13.8.3. Files
Parameters |
Help |
tap cell insertion script |
|
file used to specify the parasitics for estimation |
|
list of files to use for power grid generation |
|
list of files to use for specifying global connections |
|
script to generate a padring using ICeWall in OpenROAD |
|
script constrain pin placement |
7.13.9. show
Show a design in openroad
Setup file: show.py
Built using target: asap7_demo
7.13.9.1. Configuration
7.13.9.2. Variables
Parameters |
Help |
Task script variables specified as key value pairs. Variable names and value types must match the name and type of task and reference script consuming the variable. |
|
list of timing corners to use |
|
list of parasitic extraction corners to use |
|
corner to use for power analysis |
|
global placement density (0.0 - 1.0) |
|
global placement cell padding in number of sites |
|
detailed placement cell padding in number of sites |
|
macro halo to use when performing automated macro placement ([x, y] in microns) |
|
macro channel to use when performing automated macro placement ([x, y] in microns) |
|
list of default vias to use for detail routing |
|
list of layers to treat as unidirectional regardless of what the tech lef specifies |
|
maximum distance between tie high/low cells in microns |
|
true/false, when true enables power grid generation |
|
true/false, when true global placement will consider the routability of the design |
|
true/false, when true global placement will consider the timing performance of the design |
|
true/false, when true the detailed placement optimization will be performed |
|
maximum cell movement in detailed placement optimization in microns, 0 will result in the tool default maximum displacement |
|
maximum cell movement in detailed placement in microns, 0 will result in the tool default maximum displacement |
|
maximum distance between buffers during clock tree synthesis in microns |
|
clusting distance to use during clock tree synthesis in microns |
|
number of instances in a cluster to use during clock tree synthesis |
|
perform level balancing in clock tree synthesis |
|
maximum number of repair iterations to use during antenna repairs |
|
adds a margin to the antenna ratios (0 - 100) |
|
true, false, when true perform pin access before global routing |
|
maximum number of iterations to use in flobal routing when attempting to solve overflow |
|
macro extension distance in number of gcells, this can be useful when the detailed router needs additional space to avoid DRCs |
|
true/false, when true allow global routing to finish with congestion |
|
true/false, when true allow global routing to finish with overflow |
|
minimum layer to use for global routing of signals |
|
maximum layer to use for global routing of signals |
|
minimum layer to use for global routing of clock nets |
|
maximum layer to use for global routing of clock nets |
|
true/false, when true turns off via generation in detailed router and only uses the specified tech vias |
|
false or value, when set this specifies to the detailed router the specific process node |
|
false or value, TODO |
|
false or value, TODO |
|
false or value, TODO |
|
true/false, when true performs a via ripup step after detailed routing to remove power vias that are causing DRC violations |
|
specifies the margin to apply when performing setup repair in library timing units |
|
specifies the margin to apply when performing hold repair in library timing units |
|
specifies the amount of margin to apply to max slew repairs in percent (0 - 100) |
|
specifies the amount of margin to apply to max capacitance repairs in percent (0 - 100) |
|
true/false, when true enables adding buffers to the input ports |
|
true/false, when true enables adding buffers to the output ports |
|
timing derating factor to use for hold corners |
|
timing derating factor to use for setup corners |
|
true/false, when true enables adding fill, if enabled by the PDK, to the design |
|
true/false, when true enables IR drop analysis |
|
list of “tool key level” to enable debugging of OpenROAD |
|
Task script variables specified as key value pairs. Variable names and value types must match the name and type of task and reference script consuming the variable. |
7.13.9.3. Files
Parameters |
Help |
tap cell insertion script |
|
file used to specify the parasitics for estimation |
|
list of files to use for power grid generation |
|
list of files to use for specifying global connections |
|
script to generate a padring using ICeWall in OpenROAD |
|
script constrain pin placement |
7.14. surelog
Surelog is a SystemVerilog pre-processor, parser, elaborator, and UHDM compiler that provdes IEEE design and testbench C/C++ VPI and a Python AST API.
Documentation: https://github.com/chipsalliance/Surelog
Sources: https://github.com/chipsalliance/Surelog
Installation: https://github.com/chipsalliance/Surelog
Setup file: surelog.py
Keypath |
Value |
surelog |
|
/home/docs/checkouts/readthedocs.org/user_builds/siliconcompiler/envs/stable/lib/python3.7/site-packages/siliconcompiler/tools/surelog/bin |
|
--version |
|
>=1.13 |
7.14.1. import
Import verilog files
Setup file: import.py
7.14.1.1. Configuration
Keypath |
Value |
^\[WRN: |
|
^\[(ERR|FTL|SNT): |
|
|
|
<design>.v |
|
input,rtl,verilog |
|
2 |
7.15. sv2v
sv2v converts SystemVerilog (IEEE 1800-2017) to Verilog (IEEE 1364-2005), with an emphasis on supporting synthesizable language constructs. The primary goal of this project is to create a completely free and open-source tool for converting SystemVerilog to Verilog. While methods for performing this conversion already exist, they generally either rely on commercial tools, or are limited in scope.
Documentation: https://github.com/zachjs/sv2v
Sources: https://github.com/zachjs/sv2v
Installation: https://github.com/zachjs/sv2v
Setup file: sv2v.py
Keypath |
Value |
sv2v |
|
--numeric-version |
|
>=0.0.9 |
7.15.1. convert
Convert SystemVerilog to verilog
Setup file: convert.py
7.15.1.1. Configuration
Keypath |
Value |
|
|
<design>.v |
|
<design>.v |
|
2 |
7.16. verilator
Verilator is a free and open-source software tool which converts Verilog (a hardware description language) to a cycle-accurate behavioral model in C++ or SystemC.
For all steps, this driver runs Verilator using the -sv switch to enable
parsing a subset of SystemVerilog features. All steps also support using
['option', 'relax'] to make warnings nonfatal.
Documentation: https://verilator.org/guide/latest
Sources: https://github.com/verilator/verilator
Installation: https://verilator.org/guide/latest/install.html
Setup file: verilator.py
Keypath |
Value |
verilator |
|
--version |
|
>=4.028 |
7.16.1. compile
Compiles Verilog and C/C++ sources into an executable. Takes in a single
pickled Verilog file from inputs/<design>.v and a set of C/C++ sources
from ['input', 'c', ...]. Outputs an executable in
outputs/<design>.vexe.
This step supports using the ['option', 'trace'] parameter to enable
Verilator’s --trace flag.
Setup file: compile.py
Built using target: freepdk45_demo
7.16.1.1. Configuration
Keypath |
Value |
|
^\%Warning |
^\%Error |
|
|
|
<design>.v |
|
2 |
7.16.2. import
Preprocesses and pickles Verilog sources. Takes in a set of Verilog source
files supplied via ['input', 'verilog', ...] and reads the following
parameters:
Outputs a single Verilog file in outputs/<design>.v.
Setup file: import.py
Built using target: freepdk45_demo
7.16.2.1. Configuration
Keypath |
Value |
|
^\%Warning |
^\%Error |
|
|
|
<design>.v |
|
input,rtl,verilog |
|
2 |
7.16.3. lint
Lints Verilog source. Takes in a single pickled Verilog file from
inputs/<design>.v and produces no outputs. Results of linting can be
programatically queried using errors/warnings metrics.
Setup file: lint.py
Built using target: freepdk45_demo
7.16.3.1. Configuration
Keypath |
Value |
^\%Warning |
|
^\%Error |
|
|
|
inputs/<design>.v |
|
2 |
7.17. vivado
Vivado is an FPGA programming tool suite from Xilinx used to program Xilinx devices.
Documentation: https://www.xilinx.com/products/design-tools/vivado.html
Setup file: vivado.py
Keypath |
Value |
vivado |
|
-version |
|
xilinx |
|
tcl |
7.18. vpr
VPR (Versatile Place and Route) is an open source CAD tool designed for the exploration of new FPGA architectures and CAD algorithms, at the packing, placement and routing phases of the CAD flow. VPR takes, as input, a description of an FPGA architecture along with a technology-mapped user circuit. It then performs packing, placement, and routing to map the circuit onto the FPGA. The output of VPR includes the FPGA configuration needed to implement the circuit and statistics about the final mapped design (eg. critical path delay, area, etc).
Documentation: https://docs.verilogtorouting.org/en/latest
Sources: https://github.com/verilog-to-routing/vtr-verilog-to-routing
Installation: https://github.com/verilog-to-routing/vtr-verilog-to-routing
Setup file: vpr.py
Keypath |
Value |
vpr |
|
0.0 |
7.18.1. apr
Perform automated place and route with VPR
Setup file: apr.py
7.18.1.1. Configuration
Keypath |
Value |
|
|
|
|
2 |
7.19. xyce
Xyce is a high performance SPICE-compatible circuit simulator capable capable of solving extremely large circuit problems by supporting large-scale parallel computing platforms. It also supports serial execution on all common desktop platforms, and small-scale parallel runs on Unix-like systems.
Documentation: https://xyce.sandia.gov/documentation-tutorials/
Sources: https://github.com/Xyce/Xyce
Installation: https://xyce.sandia.gov/documentation-tutorials/building-guide/
Status: SC integration WIP
Setup file: xyce.py
Keypath |
Value |
xyce |
|
0.0 |
7.20. yosys
Yosys is a framework for RTL synthesis that takes synthesizable Verilog-2005 design and converts it to BLIF, EDIF, BTOR, SMT, Verilog netlist etc. The tool supports logical synthesis and tech mapping to ASIC standard cell libraries, FPGA architectures. In addition it has built in formal methods for property and equivalence checking.
Documentation: https://yosyshq.readthedocs.io/projects/yosys/en/latest/
Sources: https://github.com/YosysHQ/yosys
Installation: https://github.com/YosysHQ/yosys
Setup file: yosys.py
Keypath |
Value |
yosys |
|
--version |
|
>=0.24 |
|
tcl |
7.20.1. lec
Perform logical equivalence checks
Setup file: lec.py
Built using target: asap7_demo
7.20.1.1. Configuration
Keypath |
Value |
Warning: |
|
^ERROR |
|
-c |
|
True |
|
True |
|
False |
|
/home/docs/checkouts/readthedocs.org/user_builds/siliconcompiler/checkouts/stable/third_party/pdks/virtual/asap7/libs/asap7sc7p5t_rvt/r1p7/techmap/yosys/cells_latch.v |
|
slow |
|
/home/docs/checkouts/readthedocs.org/user_builds/siliconcompiler/checkouts/stable/third_party/pdks/virtual/asap7/libs/asap7sc7p5t_rvt/r1p7/nldm/asap7sc7p5t_rvt_ss.lib.gz |
|
inputs/sc_dff_library.lib |
|
|
inputs/sc_abc.constraints |
|
BUFx2_ASAP7_75t_R |
<design>.vg |
|
|
|
tools/yosys |
|
sc_lec.tcl |
7.20.1.2. Variables
Parameters |
Help |
True/False, invoke synth with the -flatten option |
|
True/False, call autoname to rename wires based on registers |
|
False/path to map_adders, techmap adders in Yosys |
|
File to use for techmapping in Yosys |
|
Timing corner to use for synthesis |
|
Liberty file to use for flip-flop mapping, if not specified the first in the logiclib is used |
|
File to use for the DFF mapping stage of Yosys |
|
File used to pass in contraints to abc |
|
Buffer that drives the abc techmapping, defaults to first buffer specified |
|
List of modules in input files to prevent flatten from “flattening” |
|
Capacitive load for the abc techmapping in fF, if not specified it will not be used |
|
Clock period to use for synthesis in ps, if more than one clock is specified, the smallest period is used. |
|
Used to derate the clock period to further constrain the clock, values between 0 and 1 |
7.20.2. syn_asic
Perform ASIC synthesis
Setup file: syn_asic.py
Built using target: asap7_demo
7.20.2.1. Configuration
Keypath |
Value |
Warning: |
|
^ERROR |
|
-c |
|
True |
|
True |
|
False |
|
/home/docs/checkouts/readthedocs.org/user_builds/siliconcompiler/checkouts/stable/third_party/pdks/virtual/asap7/libs/asap7sc7p5t_rvt/r1p7/techmap/yosys/cells_latch.v |
|
|
slow |
/home/docs/checkouts/readthedocs.org/user_builds/siliconcompiler/checkouts/stable/third_party/pdks/virtual/asap7/libs/asap7sc7p5t_rvt/r1p7/nldm/asap7sc7p5t_rvt_ss.lib.gz |
|
|
inputs/sc_dff_library.lib |
|
inputs/sc_abc.constraints |
|
BUFx2_ASAP7_75t_R |
<design>.v |
|
<design>.vg |
|
|
|
tools/yosys |
|
sc_syn.tcl |
7.20.2.2. Variables
Parameters |
Help |
True/False, invoke synth with the -flatten option |
|
True/False, call autoname to rename wires based on registers |
|
False/path to map_adders, techmap adders in Yosys |
|
File to use for techmapping in Yosys |
|
Timing corner to use for synthesis |
|
Liberty file to use for flip-flop mapping, if not specified the first in the logiclib is used |
|
File to use for the DFF mapping stage of Yosys |
|
File used to pass in contraints to abc |
|
Buffer that drives the abc techmapping, defaults to first buffer specified |
|
List of modules in input files to prevent flatten from “flattening” |
|
Capacitive load for the abc techmapping in fF, if not specified it will not be used |
|
Clock period to use for synthesis in ps, if more than one clock is specified, the smallest period is used. |
|
Used to derate the clock period to further constrain the clock, values between 0 and 1 |
7.20.3. syn_fpga
Perform FPGA synthesis
Setup file: syn_fpga.py
Built using target: fpgaflow_demo
7.20.3.1. Configuration
Keypath |
Value |
Warning: |
|
^ERROR |
|
-c |
|
<design>.v |
|
|
|
fpga,partname |
|
tools/yosys |
|
sc_syn.tcl |