3. Python-based frontends

Since SC itself is a Python library, it can be used as-is in an end-to-end build script with any Python-based HDL that can be scripted to export designs to Verilog.

For example, if you have SC installed already, you can quickly get started building designs written in the Migen HDL. To install Migen, run pip install migen. Then, paste the following into a file called “heartbeat_migen.py”.

from migen import *
from migen.fhdl.verilog import convert

import siliconcompiler

class Heartbeat(Module):
  def __init__(self, N=8):
    self.out = Signal()
    self.counter_reg = Signal(N)


    self.sync += self.counter_reg.eq(self.counter_reg + 1)
    self.sync += self.out.eq(self.counter_reg == Cat(Replicate(0, N-1), 1))

def main():
    heartbeat = Heartbeat()
    convert(heartbeat, ios={heartbeat.out}, name='heartbeat').write('heartbeat.v')

    chip = siliconcompiler.Chip('heartbeat')
    # default Migen clock pin is named 'sys_clk'
    chip.clock(pin='sys_clk', period=1)

if __name__ == '__main__':

Run this file with python heartbeat_migen.py to compile your Migen design down to a GDS and automatically display it in KLayout.

In this example, the Heartbeat class describes a design as a Migen module, and the main() function implements the build flow. The flow begins by using Migen’s built-in functionality for exporting the design as a file named “heartbeat.v”. The rest of the flow uses SC’s core API to take this Verilog file and feed it into a basic asicflow build, as described in the Quickstart guide. For more info on how Migen works, see the Migen docs.

Although we wrote this example using Migen in particular, the concepts apply to other Python-based HDLs, such as MyHDL or Amaranth (note that Amaranth’s Verilog backend requires Yosys installed locally).