2. Pre-Defined Flows#
The following are examples are pre-built flows that come with SiliconCompiler which you can use for your own builds.
See the pre-built targets for examples on how these are used in conjunction with pdks, tools and libraries.
2.1. asicflow#
A configurable ASIC compilation flow.
The ‘asicflow’ includes the stages below. The steps syn, floorplan, physyn, place, cts, route, and dfm have minimization associated with them. To view the flowgraph, see the .png file.
import: Sources are collected and packaged for compilation
syn: Translates RTL to netlist using Yosys
floorplan: Floorplanning
physyn: Physical Synthesis
place: Global and detailed placement
cts: Clock tree synthesis
route: Global and detailed routing
dfm: Metal fill, atenna fixes and any other post routing steps
export: Export design from APR tool and merge with library GDS
sta: Static timing analysis (signoff)
lvs: Layout versus schematic check (signoff)
drc: Design rule check (signoff)
The syn, physyn, place, cts, route steps supports per process options that can be set up by setting ‘<step>_np’ arg to a value > 1, as detailed below:
syn_np : Number of parallel synthesis jobs to launch
floorplan_np : Number of parallel floorplan jobs to launch
physyn_np : Number of parallel physical synthesis jobs to launch
place_np : Number of parallel place jobs to launch
cts_np : Number of parallel clock tree synthesis jobs to launch
route_np : Number of parallel routing jobs to launch
Setup file: asicflow.py
2.1.1. Configuration#
2.1.1.1. import.verilog#
Keypath |
Value |
surelog |
|
parse |
|
|
siliconcompiler.tools.surelog.parse |
2.1.1.2. import.convert#
Keypath |
Value |
('import.verilog', '0') |
|
sv2v |
|
convert |
|
|
siliconcompiler.tools.sv2v.convert |
2.1.1.3. import.chisel#
Keypath |
Value |
chisel |
|
convert |
|
|
siliconcompiler.tools.chisel.convert |
2.1.1.4. import.c#
Keypath |
Value |
bambu |
|
convert |
|
siliconcompiler.tools.bambu.convert |
2.1.1.5. import.bluespec#
Keypath |
Value |
bluespec |
|
convert |
|
|
siliconcompiler.tools.bluespec.convert |
2.1.1.6. import.vhdl#
Keypath |
Value |
ghdl |
|
convert |
|
siliconcompiler.tools.ghdl.convert |
2.1.1.7. import.combine#
Keypath |
Value |
|
|
builtin |
|
concatenate |
|
|
siliconcompiler.tools.builtin.concatenate |
2.1.1.8. syn#
Keypath |
Value |
('import.combine', '0') |
|
0.0 |
|
yosys |
|
syn_asic |
|
siliconcompiler.tools.yosys.syn_asic |
|
('import.combine', '0') |
|
0.0 |
|
yosys |
|
syn_asic |
|
siliconcompiler.tools.yosys.syn_asic |
|
('import.combine', '0') |
|
0.0 |
|
yosys |
|
syn_asic |
|
siliconcompiler.tools.yosys.syn_asic |
2.1.1.9. syn.min#
Keypath |
Value |
|
|
builtin |
|
minimum |
|
siliconcompiler.tools.builtin.minimum |
2.1.1.10. floorplan.init#
2.1.1.11. floorplan.macro_placement#
2.1.1.12. floorplan.tapcell#
2.1.1.13. floorplan.power_grid#
2.1.1.14. floorplan.pin_placement#
2.1.1.15. floorplan.min#
Keypath |
Value |
|
|
builtin |
|
minimum |
|
|
siliconcompiler.tools.builtin.minimum |
2.1.1.16. place.global#
2.1.1.17. place.repair_design#
2.1.1.18. place.detailed#
2.1.1.19. place.min#
Keypath |
Value |
|
|
builtin |
|
minimum |
|
siliconcompiler.tools.builtin.minimum |
2.1.1.20. cts.clock_tree_synthesis#
2.1.1.21. cts.repair_timing#
2.1.1.22. cts.fillcell#
2.1.1.23. cts.min#
Keypath |
Value |
|
|
builtin |
|
minimum |
|
siliconcompiler.tools.builtin.minimum |
2.1.1.24. route.global#
2.1.1.25. route.antenna_repair#
2.1.1.26. route.detailed#
2.1.1.27. route.min#
Keypath |
Value |
|
|
builtin |
|
minimum |
|
siliconcompiler.tools.builtin.minimum |
2.1.1.28. dfm.metal_fill#
Keypath |
Value |
('route.min', '0') |
|
|
1.0 |
|
1.0 |
|
1.0 |
|
0.0 |
|
0.0 |
|
0.0 |
openroad |
|
fillmetal_insertion |
|
|
siliconcompiler.tools.openroad.fillmetal_insertion |
2.1.1.29. write.gds#
Keypath |
Value |
('dfm.metal_fill', '0') |
|
klayout |
|
export |
|
siliconcompiler.tools.klayout.export |
2.1.1.30. write.views#
Keypath |
Value |
('dfm.metal_fill', '0') |
|
openroad |
|
write_data |
|
siliconcompiler.tools.openroad.write_data |
2.2. asictopflow#
A flow for stitching together hardened blocks without doing any automated place-and-route.
This flow generates a GDS and a netlist for passing to a verification/signoff flow.
Setup file: asictopflow.py
2.2.1. Configuration#
2.2.1.1. import#
Keypath |
Value |
|
0.0 |
surelog |
|
parse |
|
siliconcompiler.tools.surelog.parse |
2.2.1.2. syn#
Keypath |
Value |
('import', '0') |
|
0.0 |
|
yosys |
|
syn_asic |
|
siliconcompiler.tools.yosys.syn_asic |
2.2.1.3. export#
Keypath |
Value |
('import', '0') |
|
|
0.0 |
klayout |
|
export |
|
siliconcompiler.tools.klayout.export |
2.3. drcflow#
Perform a DRC run on an input GDS
Setup file: drcflow.py
2.3.1. Configuration#
2.3.1.1. drc#
Keypath |
Value |
klayout |
|
drc |
|
siliconcompiler.tools.klayout.drc |
2.4. dvflow#
A configurable constrained random stimulus DV flow.
The verification pipeline includes the following steps:
compile: RTL sources are compiled into object form (once)
sim: Compiled RTL is exercised using generated test
The dvflow can be parametrized using a single ‘np’ parameter. Setting ‘np’ > 1 results in multiple independent verification pipelines to be launched.
Supported tools are:
icarus
verilator
xyce
xdm-xyce
This flow is a WIP
Setup file: dvflow.py
2.4.1. Configuration#
2.4.1.1. compile#
Keypath |
Value |
icarus |
|
compile |
|
siliconcompiler.tools.icarus.compile |
2.4.1.2. sim#
Keypath |
Value |
('compile', '0') |
|
execute |
|
exec_input |
|
siliconcompiler.tools.execute.exec_input |
|
('compile', '0') |
|
execute |
|
exec_input |
|
siliconcompiler.tools.execute.exec_input |
|
('compile', '0') |
|
execute |
|
exec_input |
|
siliconcompiler.tools.execute.exec_input |
|
('compile', '0') |
|
execute |
|
exec_input |
|
siliconcompiler.tools.execute.exec_input |
|
('compile', '0') |
|
execute |
|
exec_input |
|
siliconcompiler.tools.execute.exec_input |
2.5. fpgaflow#
A configurable FPGA compilation flow.
The ‘fpgaflow’ module is a configurable FPGA flow with support for open source and commercial tool flows.
The following step convention is recommended for VPR.
import: Sources are collected and packaged for compilation
syn: Synthesize RTL into an device specific netlist
place: FPGA specific placement step
route: FPGA specific routing step
bitstream: Bitstream generation
Note that nextpnr does not appear to support breaking placement, routing, and bitstream generation into individual steps, leading to the following recommended step convention
import: Sources are collected and packaged for compilation
syn: Synthesize RTL into an device specific netlist
apr: One-step execution of place, route, bitstream with nextpnr
- Args:
fpgaflow_type (str): this parameter can be used to select a specific fpga flow instead of one selected from the partname.
partname (str): this parameter can be used to select a specific fpga flow instead of one selected from the partname set in the schema.
Setup file: fpgaflow.py
2.5.1. Configuration#
2.5.1.1. import.verilog#
Keypath |
Value |
surelog |
|
parse |
|
|
siliconcompiler.tools.surelog.parse |
2.5.1.2. import.convert#
Keypath |
Value |
('import.verilog', '0') |
|
sv2v |
|
convert |
|
|
siliconcompiler.tools.sv2v.convert |
2.5.1.3. import.chisel#
Keypath |
Value |
chisel |
|
convert |
|
|
siliconcompiler.tools.chisel.convert |
2.5.1.4. import.c#
Keypath |
Value |
bambu |
|
convert |
|
siliconcompiler.tools.bambu.convert |
2.5.1.5. import.bluespec#
Keypath |
Value |
bluespec |
|
convert |
|
|
siliconcompiler.tools.bluespec.convert |
2.5.1.6. import.vhdl#
Keypath |
Value |
ghdl |
|
convert |
|
siliconcompiler.tools.ghdl.convert |
2.5.1.7. import.combine#
Keypath |
Value |
|
|
builtin |
|
concatenate |
|
|
siliconcompiler.tools.builtin.concatenate |
2.5.1.8. syn#
Keypath |
Value |
('import.combine', '0') |
|
1.0 |
|
1.0 |
|
1.0 |
|
|
1.0 |
1.0 |
|
0.0 |
|
0.0 |
|
0.0 |
|
|
0.0 |
0.0 |
|
0.0 |
|
0.0 |
|
0.0 |
|
0.0 |
|
0.0 |
|
yosys |
|
syn_fpga |
|
siliconcompiler.tools.yosys.syn_fpga |
2.5.1.9. place#
Keypath |
Value |
('syn', '0') |
|
1.0 |
|
1.0 |
|
1.0 |
|
|
1.0 |
1.0 |
|
0.0 |
|
0.0 |
|
0.0 |
|
|
0.0 |
0.0 |
|
0.0 |
|
|
0.0 |
0.0 |
|
0.0 |
|
|
0.0 |
vpr |
|
place |
|
siliconcompiler.tools.vpr.place |
2.5.1.10. route#
Keypath |
Value |
('place', '0') |
|
1.0 |
|
1.0 |
|
1.0 |
|
|
1.0 |
1.0 |
|
0.0 |
|
0.0 |
|
0.0 |
|
|
0.0 |
0.0 |
|
0.0 |
|
|
0.0 |
0.0 |
|
0.0 |
|
|
0.0 |
vpr |
|
route |
|
siliconcompiler.tools.vpr.route |
2.5.1.11. bitstream#
2.6. generate_openroad_rcx#
Flow to generate the OpenRCX decks needed by OpenROAD to do parasitic extraction.
Setup file: generate_openroad_rcx.py
2.6.1. Configuration#
2.6.1.1. bench#
Keypath |
Value |
openroad |
|
rcx_bench |
|
siliconcompiler.tools.openroad.rcx_bench |
2.6.1.2. pex#
Keypath |
Value |
('bench', '0') |
|
builtin |
|
nop |
|
siliconcompiler.tools.builtin.nop |
|
('bench', '0') |
|
builtin |
|
nop |
|
siliconcompiler.tools.builtin.nop |
|
('bench', '0') |
|
builtin |
|
nop |
|
siliconcompiler.tools.builtin.nop |
|
('bench', '0') |
|
builtin |
|
nop |
|
siliconcompiler.tools.builtin.nop |
|
('bench', '0') |
|
builtin |
|
nop |
|
siliconcompiler.tools.builtin.nop |
2.6.1.3. extract#
Keypath |
Value |
|
|
openroad |
|
rcx_extract |
|
siliconcompiler.tools.openroad.rcx_extract |
|
|
|
openroad |
|
rcx_extract |
|
siliconcompiler.tools.openroad.rcx_extract |
|
|
|
openroad |
|
rcx_extract |
|
siliconcompiler.tools.openroad.rcx_extract |
|
|
|
openroad |
|
rcx_extract |
|
siliconcompiler.tools.openroad.rcx_extract |
|
|
|
openroad |
|
rcx_extract |
|
siliconcompiler.tools.openroad.rcx_extract |
2.7. interposerflow#
A flow to perform RDL routing and generate a GDS
Setup file: interposerflow.py
2.7.1. Configuration#
2.7.1.1. rdlroute#
Keypath |
Value |
openroad |
|
rdlroute |
|
|
siliconcompiler.tools.openroad.rdlroute |
2.7.1.2. write_gds#
Keypath |
Value |
('rdlroute', '0') |
|
klayout |
|
export |
|
|
siliconcompiler.tools.klayout.export |
2.8. lintflow#
An RTL linting flow.
Setup file: lintflow.py
2.8.1. Configuration#
2.8.1.1. lint#
Keypath |
Value |
verilator |
|
lint |
|
siliconcompiler.tools.verilator.lint |
2.9. screenshotflow#
Flow to generate a high resolution design image from a GDS or OAS file.
The ‘screenshotflow’ includes the stages below.
prepare: Prepare the stream file, such as flattening design, removing layers, and merging shapes
screenshot: Generate a set of screenshots tiled across the design
merge: Merge tiled images into a single image
Setup file: screenshotflow.py
2.9.1. Configuration#
2.9.1.1. prepare#
Keypath |
Value |
klayout |
|
operations |
|
|
siliconcompiler.tools.klayout.operations |
2.9.1.2. screenshot#
Keypath |
Value |
('prepare', '0') |
|
klayout |
|
screenshot |
|
|
siliconcompiler.tools.klayout.screenshot |
2.9.1.3. merge#
Keypath |
Value |
('screenshot', '0') |
|
montage |
|
tile |
|
siliconcompiler.tools.montage.tile |
2.10. showflow#
A flow to show the output files generated from other flows.
Required settings for this flow are below:
filetype : Type of file to show
Optional settings for this flow are below:
np : Number of parallel show jobs to launch
screenshot : true/false, indicate if this should be configured as a screenshot
showtools: dictionary of file extensions with the associated show and screenshot tasks
Setup file: showflow.py
2.10.1. Configuration#
2.10.1.1. show#
Keypath |
Value |
klayout |
|
show |
|
siliconcompiler.tools.klayout.show |
|
klayout |
|
show |
|
siliconcompiler.tools.klayout.show |
|
klayout |
|
show |
|
siliconcompiler.tools.klayout.show |
2.11. signoffflow#
A flow for running LVS/DRC signoff on a GDS layout.
Inputs must be passed to this flow as follows:
flow.input('<path-to-layout>.gds')
flow.input('<path-to-netlist>.vg')
Setup file: signoffflow.py
2.11.1. Configuration#
2.11.1.1. import#
Keypath |
Value |
|
0.0 |
builtin |
|
nop |
|
siliconcompiler.tools.builtin.nop |
2.11.1.2. extspice#
Keypath |
Value |
('import', '0') |
|
|
0.0 |
magic |
|
extspice |
|
siliconcompiler.tools.magic.extspice |
2.11.1.3. drc#
Keypath |
Value |
('import', '0') |
|
0.0 |
|
magic |
|
drc |
|
siliconcompiler.tools.magic.drc |
2.11.1.4. lvs#
Keypath |
Value |
('extspice', '0') |
|
0.0 |
|
netgen |
|
lvs |
|
siliconcompiler.tools.netgen.lvs |
2.11.1.5. signoff#
Keypath |
Value |
|
|
|
0.0 |
builtin |
|
join |
|
siliconcompiler.tools.builtin.join |
2.12. synflow#
A configurable ASIC synthesys flow with static timing.
The ‘synflow’ includes the stages below. The steps syn have minimization associated with them. To view the flowgraph, see the .png file.
import: Sources are collected and packaged for compilation
syn: Translates RTL to netlist using Yosys
timing: Create timing reports of design
The syn and timing steps supports per process options that can be set up by setting ‘syn_np’ or ‘timing_np’ arg to a value > 1, as detailed below:
syn_np : Number of parallel synthesis jobs to launch
timing_np : Number of parallel timing jobs to launch
Setup file: synflow.py
2.12.1. Configuration#
2.12.1.1. import.verilog#
Keypath |
Value |
surelog |
|
parse |
|
|
siliconcompiler.tools.surelog.parse |
2.12.1.2. import.convert#
Keypath |
Value |
('import.verilog', '0') |
|
sv2v |
|
convert |
|
|
siliconcompiler.tools.sv2v.convert |
2.12.1.3. import.chisel#
Keypath |
Value |
chisel |
|
convert |
|
|
siliconcompiler.tools.chisel.convert |
2.12.1.4. import.c#
Keypath |
Value |
bambu |
|
convert |
|
siliconcompiler.tools.bambu.convert |
2.12.1.5. import.bluespec#
Keypath |
Value |
bluespec |
|
convert |
|
|
siliconcompiler.tools.bluespec.convert |
2.12.1.6. import.vhdl#
Keypath |
Value |
ghdl |
|
convert |
|
siliconcompiler.tools.ghdl.convert |
2.12.1.7. import.combine#
Keypath |
Value |
|
|
builtin |
|
concatenate |
|
|
siliconcompiler.tools.builtin.concatenate |
2.12.1.8. syn#
Keypath |
Value |
('import.combine', '0') |
|
0.0 |
|
yosys |
|
syn_asic |
|
siliconcompiler.tools.yosys.syn_asic |
|
('import.combine', '0') |
|
0.0 |
|
yosys |
|
syn_asic |
|
siliconcompiler.tools.yosys.syn_asic |
|
('import.combine', '0') |
|
0.0 |
|
yosys |
|
syn_asic |
|
siliconcompiler.tools.yosys.syn_asic |
2.12.1.9. synmin#
Keypath |
Value |
|
|
builtin |
|
minimum |
|
siliconcompiler.tools.builtin.minimum |
2.12.1.10. timing#
Keypath |
Value |
('synmin', '0') |
|
|
1.0 |
|
1.0 |
|
1.0 |
0.0 |
|
0.0 |
|
0.0 |
|
opensta |
|
timing |
|
siliconcompiler.tools.opensta.timing |
|
('synmin', '0') |
|
|
1.0 |
|
1.0 |
|
1.0 |
0.0 |
|
0.0 |
|
0.0 |
|
opensta |
|
timing |
|
siliconcompiler.tools.opensta.timing |
|
('synmin', '0') |
|
|
1.0 |
|
1.0 |
|
1.0 |
0.0 |
|
0.0 |
|
0.0 |
|
opensta |
|
timing |
|
siliconcompiler.tools.opensta.timing |