Defining a Library

In hardware design, a library is a collection of reusable components. SiliconCompiler generalizes this concept with the Design object, which acts as a standardized “manifest” for any piece of IP (Intellectual Property) you want to include in your design.

This could be a hard macro with pre-defined physical layouts (GDS, LEF), a standard cell library from a foundry, or a soft IP delivered as RTL source code (Verilog, VHDL).

By packaging IP into a Design, you make it easy to manage, version, and reuse across different projects. Libraries are loaded into a project using the Project.add_dep() method.

Types of Libraries

There are two primary categories of libraries you can define:

• Hard Libraries (StdCellLibrary): These represent foundational, physical IP. This includes standard cell libraries, I/O cells, or hard macros (like SRAMs or SERDES) that have fixed layouts. They are defined using the specialized StdCellLibrary class, which has extra features for handling physical and timing models.

• Soft Libraries (Design): These represent synthesizable IP delivered as source code. This is common for digital IP cores that you want to integrate into your design before synthesis. They are defined using the base Design class.

Example 1: Hard IP Library

This example demonstrates how to define a library for a hard macro. This macro is a pre-designed block with its own physical layout (LEF, GDS) and timing models (.lib). We will use the StdCellLibrary because it is a physical, foundational component.

from pathlib import Path
from siliconcompiler import StdCellLibrary
from my_pdk import FakePDK # Assuming a PDK is defined elsewhere

class FakeHardIPLibrary(StdCellLibrary):
    def __init__(self):
        # 1. Call the parent constructor with a unique name for the library.
        super().__init__("fakeip")

        # 2. Associate this library with a specific PDK.
        # This tells SiliconCompiler that this IP is designed for this technology.
        self.add_asic_pdk(FakePDK())

        # 3. Define the location of the library's source files.
        # Here, we point to a local directory.
        path_base = Path("fakeip")
        self.set_dataroot("fakedata", "python://fakedata_module")

        # 4. Organize the library's files into standardized filesets.
        with self.active_dataroot("fakedata"):
            # Define the physical view files (LEF and GDS).
            with self.active_fileset("models.physical"):
                self.add_file(path_base / "lef" / "fakeip.lef")
                self.add_file(path_base / "gds" / "fakeip.gds")
                # Helper function to add standard APR tech files.
                self.add_asic_aprfileset()

            # Define the timing models. This library provides an NLDM model
            # for the "typical" corner.
            with self.active_fileset("models.timing.nldm"):
                self.add_file(path_base / "nldm" / "fakeip.lib")
                # Helper to associate the file with a specific corner.
                self.add_asic_libcornerfileset("typical", "nldm")

Using the Library

To use either of these libraries in your design, you would instantiate the class and add it as a dependency to your project.

import siliconcompiler

project = siliconcompiler.ASIC()

# Instantiate and add the hard IP library.
hard_ip_lib = FakeHardIPLibrary()
project.add_asiclib(hard_ip_lib)

# Now, the 'fakeip' will be included during compilation.
# project.run()

Example 2: Soft IP Library

This example shows how to define a library for a soft IP core, which is just a reusable block of RTL code. Since there are no physical or timing views, we use the Design.

from siliconcompiler import Design

class FakeSoftIP(Design):
    def __init__(self):
        # 1. Call the parent constructor with a unique name.
        super().__init__("fakesoftip")

        # 2. Set metadata for the library.
        self.set_version("v1.0")

        # 3. Define the location of the source files.
        self.set_dataroot("fakedata", "python://fakedata_module")

        # 4. Add the RTL source code to the 'rtl' fileset.
        # When this library is included in a project, this Verilog file
        # will be passed to the synthesis tool.
        with self.active_dataroot("fakedata"), self.active_fileset("rtl"):
                self.add_file("rtl/fakeip.v")

Using the Library

To use either of these libraries in your design, you would instantiate the class and add it as a dependency to your project.

import siliconcompiler

project = siliconcompiler.Project()

# Instantiate and add the soft IP library.
soft_ip_lib = FakeSoftIP()
project.add_dep(soft_ip_lib)

# Now, the 'fakeip.v' source file will be included during compilation.
# project.run()

Useful APIs

Core Configuration

add_file	Adds files to a fileset.
set_dataroot	Registers a data source by name, path, and optional version tag.

PDK and Physical Views

add_file	Adds files to a fileset.
set_dataroot	Registers a data source by name, path, and optional version tag.
add_asic_pdk	Adds the PDK associated with this library.
add_asic_aprfileset	Adds a mapping between filesets defined in the library.
add_asic_libcornerfileset	Adds a mapping between filesets a corners defined in the library.

Class Reference

For a complete list of all available methods, please see the full class documentation.

Design

Class siliconcompiler.Design

Design.active_dataroot	Use this context to set the dataroot parameter on files and directory parameters.
Design.active_fileset	Provides a context to temporarily set an active design fileset.
Design.add_define	Adds preprocessor macro definitions to a fileset.
Design.add_dep	Adds a module dependency to this design.
Design.add_depfileset	Record a reference to an imported dependency's fileset.
Design.add_file	Adds files to a fileset.
Design.add_idir	Adds include directories to a fileset.
Design.add_lib	Adds dynamic libraries to a fileset.
Design.add_libdir	Adds dynamic library directories to a fileset.
Design.add_undefine	Adds preprocessor macro (un)definitions to a fileset.
Design.check_filepaths	Verifies that paths to all files in manifest are valid.
Design.copy_fileset	Creates a new copy of a source fileset.
Design.find_files	Returns absolute paths to files or directories based on the keypath provided.
Design.get_dataroot	Returns absolute path to the data directory.
Design.get_define	Returns defined macros for a fileset.
Design.get_dep	Returns all dependencies associated with this object or a specific one if requested.
Design.get_depfileset	Returns list of dependency filesets.
Design.get_file	Returns a list of files from one or more filesets.
Design.get_fileset	Computes the full, recursive list of (design, fileset) tuples required for a given set of top-level filesets.
Design.get_idir	Returns include directories for a fileset.
Design.get_lib	Returns list of dynamic libraries for a fileset.
Design.get_libdir	Returns dynamic library directories for a fileset.
Design.get_param	Returns value of a named fileset parameter.
Design.get_topmodule	Returns the topmodule of a fileset.
Design.get_undefine	Returns undefined macros for a fileset.
Design.has_dep	Checks if a specific dependency is present.
Design.has_file	Returns true if the fileset contains files.
Design.has_fileset	Checks if a fileset exists in the schema.
Design.has_idir	Returns true if idirs are defined for the fileset
Design.has_libdir	Returns true if library directories are defined for the fileset
Design.hash_files	Generates hash values for a list of parameter files.
Design.read_fileset	Imports filesets from a standard formatted text file.
Design.remove_dep	Removes a previously registered module.
Design.set_dataroot	Registers a data source by name, path, and optional version tag.
Design.set_param	Sets a named parameter for a fileset.
Design.set_topmodule	Sets the topmodule of a fileset.
Design.write_depgraph	Renders and saves the dependency graph to a file.
Design.write_fileset	Exports filesets to a standard formatted text file.

StdCellLibrary

Class siliconcompiler.StdCellLibrary

StdCellLibrary.active_dataroot	Use this context to set the dataroot parameter on files and directory parameters.
StdCellLibrary.active_fileset	Provides a context to temporarily set an active design fileset.
StdCellLibrary.add_asic_aprfileset	Adds a mapping between filesets defined in the library.
StdCellLibrary.add_asic_celllist	Adds a standard cell library to the specified type.
StdCellLibrary.add_asic_libcornerfileset	Adds a mapping between filesets a corners defined in the library.
StdCellLibrary.add_asic_pdk	Adds the PDK associated with this library.
StdCellLibrary.add_asic_pexcornerfileset	Adds a mapping between filesets a corners defined in the library.
StdCellLibrary.add_asic_site	Adds a standard site to the library.
StdCellLibrary.add_asic_stackup	Set the stackups supported by this library.
StdCellLibrary.add_define	Adds preprocessor macro definitions to a fileset.
StdCellLibrary.add_dep	Adds a module dependency to this design.
StdCellLibrary.add_depfileset	Record a reference to an imported dependency's fileset.
StdCellLibrary.add_file	Adds files to a fileset.
StdCellLibrary.add_idir	Adds include directories to a fileset.
StdCellLibrary.add_lib	Adds dynamic libraries to a fileset.
StdCellLibrary.add_libdir	Adds dynamic library directories to a fileset.
StdCellLibrary.add_undefine	Adds preprocessor macro (un)definitions to a fileset.
StdCellLibrary.check_filepaths	Verifies that paths to all files in manifest are valid.
StdCellLibrary.copy_fileset	Creates a new copy of a source fileset.
StdCellLibrary.define_tool_parameter	Define a new tool parameter for the library.
StdCellLibrary.find_files	Returns absolute paths to files or directories based on the keypath provided.
StdCellLibrary.get_dataroot	Returns absolute path to the data directory.
StdCellLibrary.get_define	Returns defined macros for a fileset.
StdCellLibrary.get_dep	Returns all dependencies associated with this object or a specific one if requested.
StdCellLibrary.get_depfileset	Returns list of dependency filesets.
StdCellLibrary.get_file	Returns a list of files from one or more filesets.
StdCellLibrary.get_fileset	Computes the full, recursive list of (design, fileset) tuples required for a given set of top-level filesets.
StdCellLibrary.get_idir	Returns include directories for a fileset.
StdCellLibrary.get_lib	Returns list of dynamic libraries for a fileset.
StdCellLibrary.get_libdir	Returns dynamic library directories for a fileset.
StdCellLibrary.get_param	Returns value of a named fileset parameter.
StdCellLibrary.get_topmodule	Returns the topmodule of a fileset.
StdCellLibrary.get_undefine	Returns undefined macros for a fileset.
StdCellLibrary.has_dep	Checks if a specific dependency is present.
StdCellLibrary.has_file	Returns true if the fileset contains files.
StdCellLibrary.has_fileset	Checks if a fileset exists in the schema.
StdCellLibrary.has_idir	Returns true if idirs are defined for the fileset
StdCellLibrary.has_libdir	Returns true if library directories are defined for the fileset
StdCellLibrary.hash_files	Generates hash values for a list of parameter files.
StdCellLibrary.read_fileset	Imports filesets from a standard formatted text file.
StdCellLibrary.remove_dep	Removes a previously registered module.
StdCellLibrary.set_dataroot	Registers a data source by name, path, and optional version tag.
StdCellLibrary.set_param	Sets a named parameter for a fileset.
StdCellLibrary.set_topmodule	Sets the topmodule of a fileset.
StdCellLibrary.write_depgraph	Renders and saves the dependency graph to a file.
StdCellLibrary.write_fileset	Exports filesets to a standard formatted text file.