Welcome to SiliconCompiler’s Documentation!#
Version: 0.38.5
Useful Links: What is SiliconCompiler? | Installation | GitHub Repo | File an Issue
SiliconCompiler is an open source, modular build system that automates translation from hardware design source code to silicon (“make for silicon”).
Getting started#
New here?
Install it, then run the demo – RTL to GDS in thirteen lines. What is SiliconCompiler?
Bringing your own design?
The User Guide runs pre-defined flows on your own RTL. Start by bringing your own design, or lint it first – no EDA tools needed.
Looking something up?
The Reference Manual has the schema and the Python API. How do I…? and the FAQ answer by task.
Extending SiliconCompiler?
The Development Guide covers your own tools, flows, targets, PDKs and libraries, and packaging them. Contributing covers review.
I want to…#
Every page below is one click from here, grouped by what you are trying to do.
Get something running#
Install SiliconCompiler –
pip install siliconcompiler, plus the tools a local flow needs.Run the demo build – RTL to GDS, walked through line by line.
Check my RTL for mistakes – the quickest thing to try: the default linter needs no EDA tools at all.
Simulate, or prove a property formally – Verilator, Icarus, cocotb, and viewing the waveform.
Build my own design – what to change when the design is yours.
Work out why a run failed – reading logs, metrics and the failing node.
Run it somewhere else#
Run remotely, with nothing installed locally – compile against a server.
Run inside a container – the supported route on Windows.
Run steps in parallel – more than one node at a time.
Run on a cluster – Slurm and friends.
Run builds in CI – keeping a design building on every commit.
Watch a build while it runs – the web dashboard.
Get an email when a job finishes – job status notifications.
Take a design further#
Build an SoC with a memory – a processor and an SRAM macro.
Target an FPGA – bitstreams instead of masks.
Wrap a design in an IO pad ring – pads, corners, bond pads and a core power grid.
Reuse a block that is already hardened – instantiating a macro.
Harden a parameterized module – one module, several configurations.
Write RTL in something other than Verilog – Chisel, Migen/Amaranth, Bluespec and more.
Improve the parasitic estimate – calibrating against a golden extraction.
Sweep a parameter across many jobs – multi-job flows and automation.
Build my own flow – wiring tasks into a graph of your own.
Use commercial tools – Synopsys, Cadence and Siemens flows.
Browse the example designs – every example in the repository, built and pictured.
When something is wrong#
Frequently asked questions – the questions that come up most.
How do I…? – a task-oriented index of the calls you need.
Look up a term – the glossary.
Port code written against the Chip API –
Chipwas removed in 0.35.0; this maps the old calls to the current ones.File an issue – if you cannot find something, or something is not working, the SiliconCompiler team is happy to help.
Extend it#
Add a tool, flow, target, PDK or library – the Development Guide.
Package a library so others can install it – turning modules into a
pip-installable distribution.Contribute to SiliconCompiler – where a new module belongs, and how to get it reviewed.
Supported technologies#
Type |
Supported |
|---|---|
Languages |
C, Verilog, SV, VHDL, Chisel, Migen/Amaranth, Bluespec, MLIR |
Simulation |
Verilator, Icarus, GHDL, Xyce |
Synthesis |
Yosys, Vivado, Synopsys, Cadence |
ASIC APR |
OpenROAD, Synopsys, Cadence |
FPGA APR |
VPR, nextpnr, Vivado |
Layout Viewer |
Klayout, OpenROAD, Cadence, Synopsys |
DRC/LVS |
Klayout, Magic, Synopsys, Siemens |
Open PDKs |
sky130, ihp130, gf180, asap7, freepdk45, gt2n, icsprout55, interposer – all shipped by lambdapdk |
Foundry PDKs |
gf12lp, gf22fdx, intel16 – require a foundry agreement; see packaging an external library |