2. Pre-Defined Flows#

The following are examples are pre-built flows that come with SiliconCompiler which you can use for your own builds.

See the pre-built targets for examples on how these are used in conjunction with pdks, tools and libraries.

2.1. asicflow#

A configurable ASIC compilation flow.

The ‘asicflow’ includes the stages below. The steps syn, floorplan, physyn, place, cts, route, and dfm have minimization associated with them. To view the flowgraph, see the .png file.

  • import: Sources are collected and packaged for compilation

  • syn: Translates RTL to netlist using Yosys

  • floorplan: Floorplanning

  • physyn: Physical Synthesis

  • place: Global and detailed placement

  • cts: Clock tree synthesis

  • route: Global and detailed routing

  • dfm: Metal fill, atenna fixes and any other post routing steps

  • export: Export design from APR tool and merge with library GDS

  • sta: Static timing analysis (signoff)

  • lvs: Layout versus schematic check (signoff)

  • drc: Design rule check (signoff)

The syn, physyn, place, cts, route steps supports per process options that can be set up by setting ‘<step>_np’ arg to a value > 1, as detailed below:

  • syn_np : Number of parallel synthesis jobs to launch

  • floorplan_np : Number of parallel floorplan jobs to launch

  • physyn_np : Number of parallel physical synthesis jobs to launch

  • place_np : Number of parallel place jobs to launch

  • cts_np : Number of parallel clock tree synthesis jobs to launch

  • route_np : Number of parallel routing jobs to launch

Setup file: asicflow.py

../../_images/asicflow.svg

2.1.1. Configuration#

2.1.1.1. import#

Keypath

Value

['flowgraph', 'asicflow', 'import', '0', 'tool']

surelog

['flowgraph', 'asicflow', 'import', '0', 'task']

parse

['flowgraph', 'asicflow', 'import', '0', 'taskmodule']

siliconcompiler.tools.surelog.parse

2.1.1.2. syn#

Keypath

Value

['flowgraph', 'asicflow', 'syn', '0', 'input']

('import', '0')

['flowgraph', 'asicflow', 'syn', '0', 'goal', 'errors']

0.0

['flowgraph', 'asicflow', 'syn', '0', 'tool']

yosys

['flowgraph', 'asicflow', 'syn', '0', 'task']

syn_asic

['flowgraph', 'asicflow', 'syn', '0', 'taskmodule']

siliconcompiler.tools.yosys.syn_asic

['flowgraph', 'asicflow', 'syn', '1', 'input']

('import', '0')

['flowgraph', 'asicflow', 'syn', '1', 'goal', 'errors']

0.0

['flowgraph', 'asicflow', 'syn', '1', 'tool']

yosys

['flowgraph', 'asicflow', 'syn', '1', 'task']

syn_asic

['flowgraph', 'asicflow', 'syn', '1', 'taskmodule']

siliconcompiler.tools.yosys.syn_asic

['flowgraph', 'asicflow', 'syn', '2', 'input']

('import', '0')

['flowgraph', 'asicflow', 'syn', '2', 'goal', 'errors']

0.0

['flowgraph', 'asicflow', 'syn', '2', 'tool']

yosys

['flowgraph', 'asicflow', 'syn', '2', 'task']

syn_asic

['flowgraph', 'asicflow', 'syn', '2', 'taskmodule']

siliconcompiler.tools.yosys.syn_asic

2.1.1.3. synmin#

Keypath

Value

['flowgraph', 'asicflow', 'synmin', '0', 'input']

  • ('syn', '0')
  • ('syn', '1')
  • ('syn', '2')

['flowgraph', 'asicflow', 'synmin', '0', 'tool']

builtin

['flowgraph', 'asicflow', 'synmin', '0', 'task']

minimum

['flowgraph', 'asicflow', 'synmin', '0', 'taskmodule']

siliconcompiler.tools.builtin.minimum

2.1.1.4. floorplan#

Keypath

Value

['flowgraph', 'asicflow', 'floorplan', '0', 'input']

('synmin', '0')

['flowgraph', 'asicflow', 'floorplan', '0', 'weight', 'cellarea']

1.0

['flowgraph', 'asicflow', 'floorplan', '0', 'weight', 'peakpower']

1.0

['flowgraph', 'asicflow', 'floorplan', '0', 'weight', 'leakagepower']

1.0

['flowgraph', 'asicflow', 'floorplan', '0', 'goal', 'errors']

0.0

['flowgraph', 'asicflow', 'floorplan', '0', 'goal', 'setupwns']

0.0

['flowgraph', 'asicflow', 'floorplan', '0', 'goal', 'setuptns']

0.0

['flowgraph', 'asicflow', 'floorplan', '0', 'tool']

openroad

['flowgraph', 'asicflow', 'floorplan', '0', 'task']

floorplan

['flowgraph', 'asicflow', 'floorplan', '0', 'taskmodule']

siliconcompiler.tools.openroad.floorplan

['flowgraph', 'asicflow', 'floorplan', '1', 'input']

('synmin', '0')

['flowgraph', 'asicflow', 'floorplan', '1', 'weight', 'cellarea']

1.0

['flowgraph', 'asicflow', 'floorplan', '1', 'weight', 'peakpower']

1.0

['flowgraph', 'asicflow', 'floorplan', '1', 'weight', 'leakagepower']

1.0

['flowgraph', 'asicflow', 'floorplan', '1', 'goal', 'errors']

0.0

['flowgraph', 'asicflow', 'floorplan', '1', 'goal', 'setupwns']

0.0

['flowgraph', 'asicflow', 'floorplan', '1', 'goal', 'setuptns']

0.0

['flowgraph', 'asicflow', 'floorplan', '1', 'tool']

openroad

['flowgraph', 'asicflow', 'floorplan', '1', 'task']

floorplan

['flowgraph', 'asicflow', 'floorplan', '1', 'taskmodule']

siliconcompiler.tools.openroad.floorplan

['flowgraph', 'asicflow', 'floorplan', '2', 'input']

('synmin', '0')

['flowgraph', 'asicflow', 'floorplan', '2', 'weight', 'cellarea']

1.0

['flowgraph', 'asicflow', 'floorplan', '2', 'weight', 'peakpower']

1.0

['flowgraph', 'asicflow', 'floorplan', '2', 'weight', 'leakagepower']

1.0

['flowgraph', 'asicflow', 'floorplan', '2', 'goal', 'errors']

0.0

['flowgraph', 'asicflow', 'floorplan', '2', 'goal', 'setupwns']

0.0

['flowgraph', 'asicflow', 'floorplan', '2', 'goal', 'setuptns']

0.0

['flowgraph', 'asicflow', 'floorplan', '2', 'tool']

openroad

['flowgraph', 'asicflow', 'floorplan', '2', 'task']

floorplan

['flowgraph', 'asicflow', 'floorplan', '2', 'taskmodule']

siliconcompiler.tools.openroad.floorplan

2.1.1.5. floorplanmin#

Keypath

Value

['flowgraph', 'asicflow', 'floorplanmin', '0', 'input']

  • ('floorplan', '0')
  • ('floorplan', '1')
  • ('floorplan', '2')

['flowgraph', 'asicflow', 'floorplanmin', '0', 'tool']

builtin

['flowgraph', 'asicflow', 'floorplanmin', '0', 'task']

minimum

['flowgraph', 'asicflow', 'floorplanmin', '0', 'taskmodule']

siliconcompiler.tools.builtin.minimum

2.1.1.6. place#

Keypath

Value

['flowgraph', 'asicflow', 'place', '0', 'input']

('floorplanmin', '0')

['flowgraph', 'asicflow', 'place', '0', 'weight', 'cellarea']

1.0

['flowgraph', 'asicflow', 'place', '0', 'weight', 'peakpower']

1.0

['flowgraph', 'asicflow', 'place', '0', 'weight', 'leakagepower']

1.0

['flowgraph', 'asicflow', 'place', '0', 'goal', 'errors']

0.0

['flowgraph', 'asicflow', 'place', '0', 'goal', 'setupwns']

0.0

['flowgraph', 'asicflow', 'place', '0', 'goal', 'setuptns']

0.0

['flowgraph', 'asicflow', 'place', '0', 'tool']

openroad

['flowgraph', 'asicflow', 'place', '0', 'task']

place

['flowgraph', 'asicflow', 'place', '0', 'taskmodule']

siliconcompiler.tools.openroad.place

['flowgraph', 'asicflow', 'place', '1', 'input']

('floorplanmin', '0')

['flowgraph', 'asicflow', 'place', '1', 'weight', 'cellarea']

1.0

['flowgraph', 'asicflow', 'place', '1', 'weight', 'peakpower']

1.0

['flowgraph', 'asicflow', 'place', '1', 'weight', 'leakagepower']

1.0

['flowgraph', 'asicflow', 'place', '1', 'goal', 'errors']

0.0

['flowgraph', 'asicflow', 'place', '1', 'goal', 'setupwns']

0.0

['flowgraph', 'asicflow', 'place', '1', 'goal', 'setuptns']

0.0

['flowgraph', 'asicflow', 'place', '1', 'tool']

openroad

['flowgraph', 'asicflow', 'place', '1', 'task']

place

['flowgraph', 'asicflow', 'place', '1', 'taskmodule']

siliconcompiler.tools.openroad.place

['flowgraph', 'asicflow', 'place', '2', 'input']

('floorplanmin', '0')

['flowgraph', 'asicflow', 'place', '2', 'weight', 'cellarea']

1.0

['flowgraph', 'asicflow', 'place', '2', 'weight', 'peakpower']

1.0

['flowgraph', 'asicflow', 'place', '2', 'weight', 'leakagepower']

1.0

['flowgraph', 'asicflow', 'place', '2', 'goal', 'errors']

0.0

['flowgraph', 'asicflow', 'place', '2', 'goal', 'setupwns']

0.0

['flowgraph', 'asicflow', 'place', '2', 'goal', 'setuptns']

0.0

['flowgraph', 'asicflow', 'place', '2', 'tool']

openroad

['flowgraph', 'asicflow', 'place', '2', 'task']

place

['flowgraph', 'asicflow', 'place', '2', 'taskmodule']

siliconcompiler.tools.openroad.place

2.1.1.7. placemin#

Keypath

Value

['flowgraph', 'asicflow', 'placemin', '0', 'input']

  • ('place', '0')
  • ('place', '1')
  • ('place', '2')

['flowgraph', 'asicflow', 'placemin', '0', 'tool']

builtin

['flowgraph', 'asicflow', 'placemin', '0', 'task']

minimum

['flowgraph', 'asicflow', 'placemin', '0', 'taskmodule']

siliconcompiler.tools.builtin.minimum

2.1.1.8. cts#

Keypath

Value

['flowgraph', 'asicflow', 'cts', '0', 'input']

('placemin', '0')

['flowgraph', 'asicflow', 'cts', '0', 'weight', 'cellarea']

1.0

['flowgraph', 'asicflow', 'cts', '0', 'weight', 'peakpower']

1.0

['flowgraph', 'asicflow', 'cts', '0', 'weight', 'leakagepower']

1.0

['flowgraph', 'asicflow', 'cts', '0', 'goal', 'errors']

0.0

['flowgraph', 'asicflow', 'cts', '0', 'goal', 'setupwns']

0.0

['flowgraph', 'asicflow', 'cts', '0', 'goal', 'setuptns']

0.0

['flowgraph', 'asicflow', 'cts', '0', 'tool']

openroad

['flowgraph', 'asicflow', 'cts', '0', 'task']

cts

['flowgraph', 'asicflow', 'cts', '0', 'taskmodule']

siliconcompiler.tools.openroad.cts

['flowgraph', 'asicflow', 'cts', '1', 'input']

('placemin', '0')

['flowgraph', 'asicflow', 'cts', '1', 'weight', 'cellarea']

1.0

['flowgraph', 'asicflow', 'cts', '1', 'weight', 'peakpower']

1.0

['flowgraph', 'asicflow', 'cts', '1', 'weight', 'leakagepower']

1.0

['flowgraph', 'asicflow', 'cts', '1', 'goal', 'errors']

0.0

['flowgraph', 'asicflow', 'cts', '1', 'goal', 'setupwns']

0.0

['flowgraph', 'asicflow', 'cts', '1', 'goal', 'setuptns']

0.0

['flowgraph', 'asicflow', 'cts', '1', 'tool']

openroad

['flowgraph', 'asicflow', 'cts', '1', 'task']

cts

['flowgraph', 'asicflow', 'cts', '1', 'taskmodule']

siliconcompiler.tools.openroad.cts

['flowgraph', 'asicflow', 'cts', '2', 'input']

('placemin', '0')

['flowgraph', 'asicflow', 'cts', '2', 'weight', 'cellarea']

1.0

['flowgraph', 'asicflow', 'cts', '2', 'weight', 'peakpower']

1.0

['flowgraph', 'asicflow', 'cts', '2', 'weight', 'leakagepower']

1.0

['flowgraph', 'asicflow', 'cts', '2', 'goal', 'errors']

0.0

['flowgraph', 'asicflow', 'cts', '2', 'goal', 'setupwns']

0.0

['flowgraph', 'asicflow', 'cts', '2', 'goal', 'setuptns']

0.0

['flowgraph', 'asicflow', 'cts', '2', 'tool']

openroad

['flowgraph', 'asicflow', 'cts', '2', 'task']

cts

['flowgraph', 'asicflow', 'cts', '2', 'taskmodule']

siliconcompiler.tools.openroad.cts

2.1.1.9. ctsmin#

Keypath

Value

['flowgraph', 'asicflow', 'ctsmin', '0', 'input']

  • ('cts', '0')
  • ('cts', '1')
  • ('cts', '2')

['flowgraph', 'asicflow', 'ctsmin', '0', 'tool']

builtin

['flowgraph', 'asicflow', 'ctsmin', '0', 'task']

minimum

['flowgraph', 'asicflow', 'ctsmin', '0', 'taskmodule']

siliconcompiler.tools.builtin.minimum

2.1.1.10. route#

Keypath

Value

['flowgraph', 'asicflow', 'route', '0', 'input']

('ctsmin', '0')

['flowgraph', 'asicflow', 'route', '0', 'weight', 'cellarea']

1.0

['flowgraph', 'asicflow', 'route', '0', 'weight', 'peakpower']

1.0

['flowgraph', 'asicflow', 'route', '0', 'weight', 'leakagepower']

1.0

['flowgraph', 'asicflow', 'route', '0', 'goal', 'errors']

0.0

['flowgraph', 'asicflow', 'route', '0', 'goal', 'setupwns']

0.0

['flowgraph', 'asicflow', 'route', '0', 'goal', 'setuptns']

0.0

['flowgraph', 'asicflow', 'route', '0', 'tool']

openroad

['flowgraph', 'asicflow', 'route', '0', 'task']

route

['flowgraph', 'asicflow', 'route', '0', 'taskmodule']

siliconcompiler.tools.openroad.route

['flowgraph', 'asicflow', 'route', '1', 'input']

('ctsmin', '0')

['flowgraph', 'asicflow', 'route', '1', 'weight', 'cellarea']

1.0

['flowgraph', 'asicflow', 'route', '1', 'weight', 'peakpower']

1.0

['flowgraph', 'asicflow', 'route', '1', 'weight', 'leakagepower']

1.0

['flowgraph', 'asicflow', 'route', '1', 'goal', 'errors']

0.0

['flowgraph', 'asicflow', 'route', '1', 'goal', 'setupwns']

0.0

['flowgraph', 'asicflow', 'route', '1', 'goal', 'setuptns']

0.0

['flowgraph', 'asicflow', 'route', '1', 'tool']

openroad

['flowgraph', 'asicflow', 'route', '1', 'task']

route

['flowgraph', 'asicflow', 'route', '1', 'taskmodule']

siliconcompiler.tools.openroad.route

['flowgraph', 'asicflow', 'route', '2', 'input']

('ctsmin', '0')

['flowgraph', 'asicflow', 'route', '2', 'weight', 'cellarea']

1.0

['flowgraph', 'asicflow', 'route', '2', 'weight', 'peakpower']

1.0

['flowgraph', 'asicflow', 'route', '2', 'weight', 'leakagepower']

1.0

['flowgraph', 'asicflow', 'route', '2', 'goal', 'errors']

0.0

['flowgraph', 'asicflow', 'route', '2', 'goal', 'setupwns']

0.0

['flowgraph', 'asicflow', 'route', '2', 'goal', 'setuptns']

0.0

['flowgraph', 'asicflow', 'route', '2', 'tool']

openroad

['flowgraph', 'asicflow', 'route', '2', 'task']

route

['flowgraph', 'asicflow', 'route', '2', 'taskmodule']

siliconcompiler.tools.openroad.route

2.1.1.11. routemin#

Keypath

Value

['flowgraph', 'asicflow', 'routemin', '0', 'input']

  • ('route', '0')
  • ('route', '1')
  • ('route', '2')

['flowgraph', 'asicflow', 'routemin', '0', 'tool']

builtin

['flowgraph', 'asicflow', 'routemin', '0', 'task']

minimum

['flowgraph', 'asicflow', 'routemin', '0', 'taskmodule']

siliconcompiler.tools.builtin.minimum

2.1.1.12. dfm#

Keypath

Value

['flowgraph', 'asicflow', 'dfm', '0', 'input']

('routemin', '0')

['flowgraph', 'asicflow', 'dfm', '0', 'weight', 'cellarea']

1.0

['flowgraph', 'asicflow', 'dfm', '0', 'weight', 'peakpower']

1.0

['flowgraph', 'asicflow', 'dfm', '0', 'weight', 'leakagepower']

1.0

['flowgraph', 'asicflow', 'dfm', '0', 'goal', 'errors']

0.0

['flowgraph', 'asicflow', 'dfm', '0', 'goal', 'setupwns']

0.0

['flowgraph', 'asicflow', 'dfm', '0', 'goal', 'setuptns']

0.0

['flowgraph', 'asicflow', 'dfm', '0', 'tool']

openroad

['flowgraph', 'asicflow', 'dfm', '0', 'task']

dfm

['flowgraph', 'asicflow', 'dfm', '0', 'taskmodule']

siliconcompiler.tools.openroad.dfm

2.1.1.13. export#

Keypath

Value

['flowgraph', 'asicflow', 'export', '0', 'input']

('dfm', '0')

['flowgraph', 'asicflow', 'export', '0', 'tool']

klayout

['flowgraph', 'asicflow', 'export', '0', 'task']

export

['flowgraph', 'asicflow', 'export', '0', 'taskmodule']

siliconcompiler.tools.klayout.export

['flowgraph', 'asicflow', 'export', '1', 'input']

('dfm', '0')

['flowgraph', 'asicflow', 'export', '1', 'tool']

openroad

['flowgraph', 'asicflow', 'export', '1', 'task']

export

['flowgraph', 'asicflow', 'export', '1', 'taskmodule']

siliconcompiler.tools.openroad.export

2.2. asictopflow#

A flow for stitching together hardened blocks without doing any automated place-and-route.

This flow generates a GDS and a netlist for passing to a verification/signoff flow.

Setup file: asictopflow.py

../../_images/asictopflow.svg

2.2.1. Configuration#

2.2.1.1. import#

Keypath

Value

['flowgraph', 'asictopflow', 'import', '0', 'goal', 'errors']

0.0

['flowgraph', 'asictopflow', 'import', '0', 'tool']

surelog

['flowgraph', 'asictopflow', 'import', '0', 'task']

parse

['flowgraph', 'asictopflow', 'import', '0', 'taskmodule']

siliconcompiler.tools.surelog.parse

2.2.1.2. syn#

Keypath

Value

['flowgraph', 'asictopflow', 'syn', '0', 'input']

('import', '0')

['flowgraph', 'asictopflow', 'syn', '0', 'goal', 'errors']

0.0

['flowgraph', 'asictopflow', 'syn', '0', 'tool']

yosys

['flowgraph', 'asictopflow', 'syn', '0', 'task']

syn_asic

['flowgraph', 'asictopflow', 'syn', '0', 'taskmodule']

siliconcompiler.tools.yosys.syn_asic

2.2.1.3. export#

Keypath

Value

['flowgraph', 'asictopflow', 'export', '0', 'input']

('import', '0')

['flowgraph', 'asictopflow', 'export', '0', 'goal', 'errors']

0.0

['flowgraph', 'asictopflow', 'export', '0', 'tool']

klayout

['flowgraph', 'asictopflow', 'export', '0', 'task']

export

['flowgraph', 'asictopflow', 'export', '0', 'taskmodule']

siliconcompiler.tools.klayout.export

2.3. dvflow#

A configurable constrained random stimulus DV flow.

The verification pipeline includes the followins teps:

  • compile: RTL sources are compiled into object form (once)

  • sim: Compiled RTL is exercised using generated test

The dvflow can be parametrized using a single ‘np’ parameter. Setting ‘np’ > 1 results in multiple independent verificaiton pipelines to be launched.

This flow is a WIP

Setup file: dvflow.py

../../_images/dvflow.svg

2.3.1. Configuration#

2.3.1.1. compile#

Keypath

Value

['flowgraph', 'dvflow', 'compile', '0', 'tool']

icarus

['flowgraph', 'dvflow', 'compile', '0', 'task']

compile

['flowgraph', 'dvflow', 'compile', '0', 'taskmodule']

siliconcompiler.tools.icarus.compile

2.3.1.2. sim#

Keypath

Value

['flowgraph', 'dvflow', 'sim', '0', 'input']

('compile', '0')

['flowgraph', 'dvflow', 'sim', '0', 'tool']

execute

['flowgraph', 'dvflow', 'sim', '0', 'task']

exec_input

['flowgraph', 'dvflow', 'sim', '0', 'taskmodule']

siliconcompiler.tools.execute.exec_input

['flowgraph', 'dvflow', 'sim', '1', 'input']

('compile', '0')

['flowgraph', 'dvflow', 'sim', '1', 'tool']

execute

['flowgraph', 'dvflow', 'sim', '1', 'task']

exec_input

['flowgraph', 'dvflow', 'sim', '1', 'taskmodule']

siliconcompiler.tools.execute.exec_input

['flowgraph', 'dvflow', 'sim', '2', 'input']

('compile', '0')

['flowgraph', 'dvflow', 'sim', '2', 'tool']

execute

['flowgraph', 'dvflow', 'sim', '2', 'task']

exec_input

['flowgraph', 'dvflow', 'sim', '2', 'taskmodule']

siliconcompiler.tools.execute.exec_input

['flowgraph', 'dvflow', 'sim', '3', 'input']

('compile', '0')

['flowgraph', 'dvflow', 'sim', '3', 'tool']

execute

['flowgraph', 'dvflow', 'sim', '3', 'task']

exec_input

['flowgraph', 'dvflow', 'sim', '3', 'taskmodule']

siliconcompiler.tools.execute.exec_input

['flowgraph', 'dvflow', 'sim', '4', 'input']

('compile', '0')

['flowgraph', 'dvflow', 'sim', '4', 'tool']

execute

['flowgraph', 'dvflow', 'sim', '4', 'task']

exec_input

['flowgraph', 'dvflow', 'sim', '4', 'taskmodule']

siliconcompiler.tools.execute.exec_input

2.4. fpgaflow#

A configurable FPGA compilation flow.

The ‘fpgaflow’ module is a configurable FPGA flow with support for open source and commercial tool flows.

The following step convention is recommended for VPR.

  • import: Sources are collected and packaged for compilation

  • syn: Synthesize RTL into an device specific netlist

  • place: FPGA specific placement step

  • route: FPGA specific routing step

  • bitstream: Bitstream generation

Note that nextpnr does not appear to support breaking placement, routing, and bitstream generation into individual steps, leading to the following recommended step convention

  • import: Sources are collected and packaged for compilation

  • syn: Synthesize RTL into an device specific netlist

  • apr: One-step execution of place, route, bitstream with nextpnr

Schema keypaths:

Setup file: fpgaflow.py

../../_images/fpgaflow.svg

2.4.1. Configuration#

2.4.1.1. import#

Keypath

Value

['flowgraph', 'fpgaflow', 'import', '0', 'weight', 'luts']

1.0

['flowgraph', 'fpgaflow', 'import', '0', 'weight', 'dsps']

1.0

['flowgraph', 'fpgaflow', 'import', '0', 'weight', 'brams']

1.0

['flowgraph', 'fpgaflow', 'import', '0', 'weight', 'peakpower']

1.0

['flowgraph', 'fpgaflow', 'import', '0', 'weight', 'leakagepower']

1.0

['flowgraph', 'fpgaflow', 'import', '0', 'weight', 'registers']

1.0

['flowgraph', 'fpgaflow', 'import', '0', 'weight', 'pins']

1.0

['flowgraph', 'fpgaflow', 'import', '0', 'goal', 'errors']

0.0

['flowgraph', 'fpgaflow', 'import', '0', 'goal', 'warnings']

0.0

['flowgraph', 'fpgaflow', 'import', '0', 'goal', 'drvs']

0.0

['flowgraph', 'fpgaflow', 'import', '0', 'goal', 'unconstrained']

0.0

['flowgraph', 'fpgaflow', 'import', '0', 'goal', 'holdwns']

0.0

['flowgraph', 'fpgaflow', 'import', '0', 'goal', 'holdtns']

0.0

['flowgraph', 'fpgaflow', 'import', '0', 'goal', 'holdpaths']

0.0

['flowgraph', 'fpgaflow', 'import', '0', 'goal', 'setupwns']

0.0

['flowgraph', 'fpgaflow', 'import', '0', 'goal', 'setuptns']

0.0

['flowgraph', 'fpgaflow', 'import', '0', 'goal', 'setuppaths']

0.0

['flowgraph', 'fpgaflow', 'import', '0', 'tool']

surelog

['flowgraph', 'fpgaflow', 'import', '0', 'task']

parse

['flowgraph', 'fpgaflow', 'import', '0', 'taskmodule']

siliconcompiler.tools.surelog.parse

2.4.1.2. syn#

Keypath

Value

['flowgraph', 'fpgaflow', 'syn', '0', 'input']

('import', '0')

['flowgraph', 'fpgaflow', 'syn', '0', 'weight', 'luts']

1.0

['flowgraph', 'fpgaflow', 'syn', '0', 'weight', 'dsps']

1.0

['flowgraph', 'fpgaflow', 'syn', '0', 'weight', 'brams']

1.0

['flowgraph', 'fpgaflow', 'syn', '0', 'weight', 'peakpower']

1.0

['flowgraph', 'fpgaflow', 'syn', '0', 'weight', 'leakagepower']

1.0

['flowgraph', 'fpgaflow', 'syn', '0', 'weight', 'registers']

1.0

['flowgraph', 'fpgaflow', 'syn', '0', 'weight', 'pins']

1.0

['flowgraph', 'fpgaflow', 'syn', '0', 'goal', 'errors']

0.0

['flowgraph', 'fpgaflow', 'syn', '0', 'goal', 'warnings']

0.0

['flowgraph', 'fpgaflow', 'syn', '0', 'goal', 'drvs']

0.0

['flowgraph', 'fpgaflow', 'syn', '0', 'goal', 'unconstrained']

0.0

['flowgraph', 'fpgaflow', 'syn', '0', 'goal', 'holdwns']

0.0

['flowgraph', 'fpgaflow', 'syn', '0', 'goal', 'holdtns']

0.0

['flowgraph', 'fpgaflow', 'syn', '0', 'goal', 'holdpaths']

0.0

['flowgraph', 'fpgaflow', 'syn', '0', 'goal', 'setupwns']

0.0

['flowgraph', 'fpgaflow', 'syn', '0', 'goal', 'setuptns']

0.0

['flowgraph', 'fpgaflow', 'syn', '0', 'goal', 'setuppaths']

0.0

['flowgraph', 'fpgaflow', 'syn', '0', 'tool']

yosys

['flowgraph', 'fpgaflow', 'syn', '0', 'task']

syn_fpga

['flowgraph', 'fpgaflow', 'syn', '0', 'taskmodule']

siliconcompiler.tools.yosys.syn_fpga

2.4.1.3. apr#

Keypath

Value

['flowgraph', 'fpgaflow', 'apr', '0', 'input']

('syn', '0')

['flowgraph', 'fpgaflow', 'apr', '0', 'weight', 'luts']

1.0

['flowgraph', 'fpgaflow', 'apr', '0', 'weight', 'dsps']

1.0

['flowgraph', 'fpgaflow', 'apr', '0', 'weight', 'brams']

1.0

['flowgraph', 'fpgaflow', 'apr', '0', 'weight', 'peakpower']

1.0

['flowgraph', 'fpgaflow', 'apr', '0', 'weight', 'leakagepower']

1.0

['flowgraph', 'fpgaflow', 'apr', '0', 'weight', 'registers']

1.0

['flowgraph', 'fpgaflow', 'apr', '0', 'weight', 'pins']

1.0

['flowgraph', 'fpgaflow', 'apr', '0', 'goal', 'errors']

0.0

['flowgraph', 'fpgaflow', 'apr', '0', 'goal', 'warnings']

0.0

['flowgraph', 'fpgaflow', 'apr', '0', 'goal', 'drvs']

0.0

['flowgraph', 'fpgaflow', 'apr', '0', 'goal', 'unconstrained']

0.0

['flowgraph', 'fpgaflow', 'apr', '0', 'goal', 'holdwns']

0.0

['flowgraph', 'fpgaflow', 'apr', '0', 'goal', 'holdtns']

0.0

['flowgraph', 'fpgaflow', 'apr', '0', 'goal', 'holdpaths']

0.0

['flowgraph', 'fpgaflow', 'apr', '0', 'goal', 'setupwns']

0.0

['flowgraph', 'fpgaflow', 'apr', '0', 'goal', 'setuptns']

0.0

['flowgraph', 'fpgaflow', 'apr', '0', 'goal', 'setuppaths']

0.0

['flowgraph', 'fpgaflow', 'apr', '0', 'tool']

nextpnr

['flowgraph', 'fpgaflow', 'apr', '0', 'task']

apr

['flowgraph', 'fpgaflow', 'apr', '0', 'taskmodule']

siliconcompiler.tools.nextpnr.apr

2.5. generate_openroad_rcx#

Flow to generate the OpenRCX decks needed by OpenROAD to do parasitic extraction.

Setup file: generate_openroad_rcx.py

../../_images/generate_openroad_rcx.svg

2.5.1. Configuration#

2.5.1.1. bench#

Keypath

Value

['flowgraph', 'generate_rcx', 'bench', '0', 'tool']

openroad

['flowgraph', 'generate_rcx', 'bench', '0', 'task']

rcx_bench

['flowgraph', 'generate_rcx', 'bench', '0', 'taskmodule']

siliconcompiler.tools.openroad.rcx_bench

2.5.1.2. pex#

Keypath

Value

['flowgraph', 'generate_rcx', 'pex', '0', 'input']

('bench', '0')

['flowgraph', 'generate_rcx', 'pex', '0', 'tool']

builtin

['flowgraph', 'generate_rcx', 'pex', '0', 'task']

nop

['flowgraph', 'generate_rcx', 'pex', '0', 'taskmodule']

siliconcompiler.tools.builtin.nop

['flowgraph', 'generate_rcx', 'pex', '1', 'input']

('bench', '0')

['flowgraph', 'generate_rcx', 'pex', '1', 'tool']

builtin

['flowgraph', 'generate_rcx', 'pex', '1', 'task']

nop

['flowgraph', 'generate_rcx', 'pex', '1', 'taskmodule']

siliconcompiler.tools.builtin.nop

['flowgraph', 'generate_rcx', 'pex', '2', 'input']

('bench', '0')

['flowgraph', 'generate_rcx', 'pex', '2', 'tool']

builtin

['flowgraph', 'generate_rcx', 'pex', '2', 'task']

nop

['flowgraph', 'generate_rcx', 'pex', '2', 'taskmodule']

siliconcompiler.tools.builtin.nop

['flowgraph', 'generate_rcx', 'pex', '3', 'input']

('bench', '0')

['flowgraph', 'generate_rcx', 'pex', '3', 'tool']

builtin

['flowgraph', 'generate_rcx', 'pex', '3', 'task']

nop

['flowgraph', 'generate_rcx', 'pex', '3', 'taskmodule']

siliconcompiler.tools.builtin.nop

['flowgraph', 'generate_rcx', 'pex', '4', 'input']

('bench', '0')

['flowgraph', 'generate_rcx', 'pex', '4', 'tool']

builtin

['flowgraph', 'generate_rcx', 'pex', '4', 'task']

nop

['flowgraph', 'generate_rcx', 'pex', '4', 'taskmodule']

siliconcompiler.tools.builtin.nop

2.5.1.3. extract#

Keypath

Value

['flowgraph', 'generate_rcx', 'extract', '0', 'input']

  • ('pex', '0')
  • ('bench', '0')

['flowgraph', 'generate_rcx', 'extract', '0', 'tool']

openroad

['flowgraph', 'generate_rcx', 'extract', '0', 'task']

rcx_extract

['flowgraph', 'generate_rcx', 'extract', '0', 'taskmodule']

siliconcompiler.tools.openroad.rcx_extract

['flowgraph', 'generate_rcx', 'extract', '1', 'input']

  • ('pex', '1')
  • ('bench', '0')

['flowgraph', 'generate_rcx', 'extract', '1', 'tool']

openroad

['flowgraph', 'generate_rcx', 'extract', '1', 'task']

rcx_extract

['flowgraph', 'generate_rcx', 'extract', '1', 'taskmodule']

siliconcompiler.tools.openroad.rcx_extract

['flowgraph', 'generate_rcx', 'extract', '2', 'input']

  • ('pex', '2')
  • ('bench', '0')

['flowgraph', 'generate_rcx', 'extract', '2', 'tool']

openroad

['flowgraph', 'generate_rcx', 'extract', '2', 'task']

rcx_extract

['flowgraph', 'generate_rcx', 'extract', '2', 'taskmodule']

siliconcompiler.tools.openroad.rcx_extract

['flowgraph', 'generate_rcx', 'extract', '3', 'input']

  • ('pex', '3')
  • ('bench', '0')

['flowgraph', 'generate_rcx', 'extract', '3', 'tool']

openroad

['flowgraph', 'generate_rcx', 'extract', '3', 'task']

rcx_extract

['flowgraph', 'generate_rcx', 'extract', '3', 'taskmodule']

siliconcompiler.tools.openroad.rcx_extract

['flowgraph', 'generate_rcx', 'extract', '4', 'input']

  • ('pex', '4')
  • ('bench', '0')

['flowgraph', 'generate_rcx', 'extract', '4', 'tool']

openroad

['flowgraph', 'generate_rcx', 'extract', '4', 'task']

rcx_extract

['flowgraph', 'generate_rcx', 'extract', '4', 'taskmodule']

siliconcompiler.tools.openroad.rcx_extract

2.6. lintflow#

An RTL linting flow.

Setup file: lintflow.py

../../_images/lintflow.svg

2.6.1. Configuration#

2.6.1.1. lint#

Keypath

Value

['flowgraph', 'lintflow', 'lint', '0', 'tool']

verilator

['flowgraph', 'lintflow', 'lint', '0', 'task']

lint

['flowgraph', 'lintflow', 'lint', '0', 'taskmodule']

siliconcompiler.tools.verilator.lint

2.7. screenshotflow#

Flow to generate a high resolution design image from a GDS or OAS file.

The ‘screenshotflow’ includes the stages below.

  • prepare: Prepare the stream file, such as flattening design, removing layers, and merging shapes

  • screenshot: Generate a set of screenshots tiled across the design

  • merge: Merge tiled images into a single image

Setup file: screenshotflow.py

../../_images/screenshotflow.svg

2.7.1. Configuration#

2.7.1.1. prepare#

Keypath

Value

['flowgraph', 'screenshotflow', 'prepare', '0', 'tool']

klayout

['flowgraph', 'screenshotflow', 'prepare', '0', 'task']

operations

['flowgraph', 'screenshotflow', 'prepare', '0', 'taskmodule']

siliconcompiler.tools.klayout.operations

2.7.1.2. screenshot#

Keypath

Value

['flowgraph', 'screenshotflow', 'screenshot', '0', 'input']

('prepare', '0')

['flowgraph', 'screenshotflow', 'screenshot', '0', 'tool']

klayout

['flowgraph', 'screenshotflow', 'screenshot', '0', 'task']

screenshot

['flowgraph', 'screenshotflow', 'screenshot', '0', 'taskmodule']

siliconcompiler.tools.klayout.screenshot

2.7.1.3. merge#

Keypath

Value

['flowgraph', 'screenshotflow', 'merge', '0', 'input']

('screenshot', '0')

['flowgraph', 'screenshotflow', 'merge', '0', 'tool']

montage

['flowgraph', 'screenshotflow', 'merge', '0', 'task']

tile

['flowgraph', 'screenshotflow', 'merge', '0', 'taskmodule']

siliconcompiler.tools.montage.tile

2.8. showflow#

A flow to show the output files generated from other flows.

Required settings for this flow are below:

  • filetype : Type of file to show

Optional settings for this flow are below:

  • np : Number of parallel show jobs to launch

  • screenshot : true/false, indicate if this should be configured as a screenshot

Setup file: showflow.py

../../_images/showflow.svg

2.8.1. Configuration#

2.8.1.1. show#

Keypath

Value

['flowgraph', 'showflow', 'show', '0', 'tool']

klayout

['flowgraph', 'showflow', 'show', '0', 'task']

show

['flowgraph', 'showflow', 'show', '0', 'taskmodule']

siliconcompiler.tools.klayout.show

['flowgraph', 'showflow', 'show', '1', 'tool']

klayout

['flowgraph', 'showflow', 'show', '1', 'task']

show

['flowgraph', 'showflow', 'show', '1', 'taskmodule']

siliconcompiler.tools.klayout.show

['flowgraph', 'showflow', 'show', '2', 'tool']

klayout

['flowgraph', 'showflow', 'show', '2', 'task']

show

['flowgraph', 'showflow', 'show', '2', 'taskmodule']

siliconcompiler.tools.klayout.show

2.9. signoffflow#

A flow for running LVS/DRC signoff on a GDS layout.

Inputs must be passed to this flow as follows:

flow.input('<path-to-layout>.gds')
flow.input('<path-to-netlist>.vg')

Setup file: signoffflow.py

../../_images/signoffflow.svg

2.9.1. Configuration#

2.9.1.1. import#

Keypath

Value

['flowgraph', 'signoffflow', 'import', '0', 'goal', 'errors']

0.0

['flowgraph', 'signoffflow', 'import', '0', 'tool']

builtin

['flowgraph', 'signoffflow', 'import', '0', 'task']

nop

['flowgraph', 'signoffflow', 'import', '0', 'taskmodule']

siliconcompiler.tools.builtin.nop

2.9.1.2. extspice#

Keypath

Value

['flowgraph', 'signoffflow', 'extspice', '0', 'input']

('import', '0')

['flowgraph', 'signoffflow', 'extspice', '0', 'goal', 'errors']

0.0

['flowgraph', 'signoffflow', 'extspice', '0', 'tool']

magic

['flowgraph', 'signoffflow', 'extspice', '0', 'task']

extspice

['flowgraph', 'signoffflow', 'extspice', '0', 'taskmodule']

siliconcompiler.tools.magic.extspice

2.9.1.3. drc#

Keypath

Value

['flowgraph', 'signoffflow', 'drc', '0', 'input']

('import', '0')

['flowgraph', 'signoffflow', 'drc', '0', 'goal', 'errors']

0.0

['flowgraph', 'signoffflow', 'drc', '0', 'tool']

magic

['flowgraph', 'signoffflow', 'drc', '0', 'task']

drc

['flowgraph', 'signoffflow', 'drc', '0', 'taskmodule']

siliconcompiler.tools.magic.drc

2.9.1.4. lvs#

Keypath

Value

['flowgraph', 'signoffflow', 'lvs', '0', 'input']

('extspice', '0')

['flowgraph', 'signoffflow', 'lvs', '0', 'goal', 'errors']

0.0

['flowgraph', 'signoffflow', 'lvs', '0', 'tool']

netgen

['flowgraph', 'signoffflow', 'lvs', '0', 'task']

lvs

['flowgraph', 'signoffflow', 'lvs', '0', 'taskmodule']

siliconcompiler.tools.netgen.lvs

2.9.1.5. signoff#

Keypath

Value

['flowgraph', 'signoffflow', 'signoff', '0', 'input']

  • ('lvs', '0')
  • ('drc', '0')

['flowgraph', 'signoffflow', 'signoff', '0', 'goal', 'errors']

0.0

['flowgraph', 'signoffflow', 'signoff', '0', 'tool']

builtin

['flowgraph', 'signoffflow', 'signoff', '0', 'task']

join

['flowgraph', 'signoffflow', 'signoff', '0', 'taskmodule']

siliconcompiler.tools.builtin.join