2. Pre-Defined Flows#

The following are examples are pre-built flows that come with SiliconCompiler which you can use for your own builds.

See the pre-built targets for examples on how these are used in conjunction with pdks, tools and libraries.

2.1. asicflow#

A configurable ASIC compilation flow.

The ‘asicflow’ includes the stages below. The steps syn, floorplan, physyn, place, cts, route, and dfm have minimization associated with them. To view the flowgraph, see the .png file.

import: Sources are collected and packaged for compilation
syn: Translates RTL to netlist using Yosys
floorplan: Floorplanning
physyn: Physical Synthesis
place: Global and detailed placement
cts: Clock tree synthesis
route: Global and detailed routing
dfm: Metal fill, atenna fixes and any other post routing steps
export: Export design from APR tool and merge with library GDS
sta: Static timing analysis (signoff)
lvs: Layout versus schematic check (signoff)
drc: Design rule check (signoff)

The syn, physyn, place, cts, route steps supports per process options that can be set up by setting ‘<step>_np’ arg to a value > 1, as detailed below:

syn_np : Number of parallel synthesis jobs to launch
floorplan_np : Number of parallel floorplan jobs to launch
physyn_np : Number of parallel physical synthesis jobs to launch
place_np : Number of parallel place jobs to launch
cts_np : Number of parallel clock tree synthesis jobs to launch
route_np : Number of parallel routing jobs to launch

Setup file: asicflow.py

2.1.1. Configuration#

2.1.1.1. asicflow#

Keypath	Value
`['flowgraph', 'asicflow', 'import', '0', 'tool']`	`surelog`
`['flowgraph', 'asicflow', 'import', '0', 'task']`	`parse`
`['flowgraph', 'asicflow', 'import', '0', 'taskmodule']`	`siliconcompiler.tools.surelog.parse`
`['flowgraph', 'asicflow', 'syn', '0', 'input']`	`('import', '0')`
`['flowgraph', 'asicflow', 'syn', '0', 'goal', 'errors']`	`0.0`
`['flowgraph', 'asicflow', 'syn', '0', 'tool']`	`yosys`
`['flowgraph', 'asicflow', 'syn', '0', 'task']`	`syn_asic`
`['flowgraph', 'asicflow', 'syn', '0', 'taskmodule']`	`siliconcompiler.tools.yosys.syn_asic`
`['flowgraph', 'asicflow', 'syn', '1', 'input']`	`('import', '0')`
`['flowgraph', 'asicflow', 'syn', '1', 'goal', 'errors']`	`0.0`
`['flowgraph', 'asicflow', 'syn', '1', 'tool']`	`yosys`
`['flowgraph', 'asicflow', 'syn', '1', 'task']`	`syn_asic`
`['flowgraph', 'asicflow', 'syn', '1', 'taskmodule']`	`siliconcompiler.tools.yosys.syn_asic`
`['flowgraph', 'asicflow', 'syn', '2', 'input']`	`('import', '0')`
`['flowgraph', 'asicflow', 'syn', '2', 'goal', 'errors']`	`0.0`
`['flowgraph', 'asicflow', 'syn', '2', 'tool']`	`yosys`
`['flowgraph', 'asicflow', 'syn', '2', 'task']`	`syn_asic`
`['flowgraph', 'asicflow', 'syn', '2', 'taskmodule']`	`siliconcompiler.tools.yosys.syn_asic`
`['flowgraph', 'asicflow', 'synmin', '0', 'input']`	`('syn', '0')` `('syn', '1')` `('syn', '2')`
`['flowgraph', 'asicflow', 'synmin', '0', 'tool']`	`builtin`
`['flowgraph', 'asicflow', 'synmin', '0', 'task']`	`minimum`
`['flowgraph', 'asicflow', 'synmin', '0', 'taskmodule']`	`siliconcompiler.tools.builtin.minimum`
`['flowgraph', 'asicflow', 'floorplan', '0', 'input']`	`('synmin', '0')`
`['flowgraph', 'asicflow', 'floorplan', '0', 'weight', 'cellarea']`	`1.0`
`['flowgraph', 'asicflow', 'floorplan', '0', 'weight', 'peakpower']`	`1.0`
`['flowgraph', 'asicflow', 'floorplan', '0', 'weight', 'leakagepower']`	`1.0`
`['flowgraph', 'asicflow', 'floorplan', '0', 'goal', 'errors']`	`0.0`
`['flowgraph', 'asicflow', 'floorplan', '0', 'goal', 'setupwns']`	`0.0`
`['flowgraph', 'asicflow', 'floorplan', '0', 'goal', 'setuptns']`	`0.0`
`['flowgraph', 'asicflow', 'floorplan', '0', 'tool']`	`openroad`
`['flowgraph', 'asicflow', 'floorplan', '0', 'task']`	`floorplan`
`['flowgraph', 'asicflow', 'floorplan', '0', 'taskmodule']`	`siliconcompiler.tools.openroad.floorplan`
`['flowgraph', 'asicflow', 'floorplan', '1', 'input']`	`('synmin', '0')`
`['flowgraph', 'asicflow', 'floorplan', '1', 'weight', 'cellarea']`	`1.0`
`['flowgraph', 'asicflow', 'floorplan', '1', 'weight', 'peakpower']`	`1.0`
`['flowgraph', 'asicflow', 'floorplan', '1', 'weight', 'leakagepower']`	`1.0`
`['flowgraph', 'asicflow', 'floorplan', '1', 'goal', 'errors']`	`0.0`
`['flowgraph', 'asicflow', 'floorplan', '1', 'goal', 'setupwns']`	`0.0`
`['flowgraph', 'asicflow', 'floorplan', '1', 'goal', 'setuptns']`	`0.0`
`['flowgraph', 'asicflow', 'floorplan', '1', 'tool']`	`openroad`
`['flowgraph', 'asicflow', 'floorplan', '1', 'task']`	`floorplan`
`['flowgraph', 'asicflow', 'floorplan', '1', 'taskmodule']`	`siliconcompiler.tools.openroad.floorplan`
`['flowgraph', 'asicflow', 'floorplan', '2', 'input']`	`('synmin', '0')`
`['flowgraph', 'asicflow', 'floorplan', '2', 'weight', 'cellarea']`	`1.0`
`['flowgraph', 'asicflow', 'floorplan', '2', 'weight', 'peakpower']`	`1.0`
`['flowgraph', 'asicflow', 'floorplan', '2', 'weight', 'leakagepower']`	`1.0`
`['flowgraph', 'asicflow', 'floorplan', '2', 'goal', 'errors']`	`0.0`
`['flowgraph', 'asicflow', 'floorplan', '2', 'goal', 'setupwns']`	`0.0`
`['flowgraph', 'asicflow', 'floorplan', '2', 'goal', 'setuptns']`	`0.0`
`['flowgraph', 'asicflow', 'floorplan', '2', 'tool']`	`openroad`
`['flowgraph', 'asicflow', 'floorplan', '2', 'task']`	`floorplan`
`['flowgraph', 'asicflow', 'floorplan', '2', 'taskmodule']`	`siliconcompiler.tools.openroad.floorplan`
`['flowgraph', 'asicflow', 'floorplanmin', '0', 'input']`	`('floorplan', '0')` `('floorplan', '1')` `('floorplan', '2')`
`['flowgraph', 'asicflow', 'floorplanmin', '0', 'tool']`	`builtin`
`['flowgraph', 'asicflow', 'floorplanmin', '0', 'task']`	`minimum`
`['flowgraph', 'asicflow', 'floorplanmin', '0', 'taskmodule']`	`siliconcompiler.tools.builtin.minimum`
`['flowgraph', 'asicflow', 'physyn', '0', 'input']`	`('floorplanmin', '0')`
`['flowgraph', 'asicflow', 'physyn', '0', 'weight', 'cellarea']`	`1.0`
`['flowgraph', 'asicflow', 'physyn', '0', 'weight', 'peakpower']`	`1.0`
`['flowgraph', 'asicflow', 'physyn', '0', 'weight', 'leakagepower']`	`1.0`
`['flowgraph', 'asicflow', 'physyn', '0', 'goal', 'errors']`	`0.0`
`['flowgraph', 'asicflow', 'physyn', '0', 'goal', 'setupwns']`	`0.0`
`['flowgraph', 'asicflow', 'physyn', '0', 'goal', 'setuptns']`	`0.0`
`['flowgraph', 'asicflow', 'physyn', '0', 'tool']`	`openroad`
`['flowgraph', 'asicflow', 'physyn', '0', 'task']`	`physyn`
`['flowgraph', 'asicflow', 'physyn', '0', 'taskmodule']`	`siliconcompiler.tools.openroad.physyn`
`['flowgraph', 'asicflow', 'physyn', '1', 'input']`	`('floorplanmin', '0')`
`['flowgraph', 'asicflow', 'physyn', '1', 'weight', 'cellarea']`	`1.0`
`['flowgraph', 'asicflow', 'physyn', '1', 'weight', 'peakpower']`	`1.0`
`['flowgraph', 'asicflow', 'physyn', '1', 'weight', 'leakagepower']`	`1.0`
`['flowgraph', 'asicflow', 'physyn', '1', 'goal', 'errors']`	`0.0`
`['flowgraph', 'asicflow', 'physyn', '1', 'goal', 'setupwns']`	`0.0`
`['flowgraph', 'asicflow', 'physyn', '1', 'goal', 'setuptns']`	`0.0`
`['flowgraph', 'asicflow', 'physyn', '1', 'tool']`	`openroad`
`['flowgraph', 'asicflow', 'physyn', '1', 'task']`	`physyn`
`['flowgraph', 'asicflow', 'physyn', '1', 'taskmodule']`	`siliconcompiler.tools.openroad.physyn`
`['flowgraph', 'asicflow', 'physyn', '2', 'input']`	`('floorplanmin', '0')`
`['flowgraph', 'asicflow', 'physyn', '2', 'weight', 'cellarea']`	`1.0`
`['flowgraph', 'asicflow', 'physyn', '2', 'weight', 'peakpower']`	`1.0`
`['flowgraph', 'asicflow', 'physyn', '2', 'weight', 'leakagepower']`	`1.0`
`['flowgraph', 'asicflow', 'physyn', '2', 'goal', 'errors']`	`0.0`
`['flowgraph', 'asicflow', 'physyn', '2', 'goal', 'setupwns']`	`0.0`
`['flowgraph', 'asicflow', 'physyn', '2', 'goal', 'setuptns']`	`0.0`
`['flowgraph', 'asicflow', 'physyn', '2', 'tool']`	`openroad`
`['flowgraph', 'asicflow', 'physyn', '2', 'task']`	`physyn`
`['flowgraph', 'asicflow', 'physyn', '2', 'taskmodule']`	`siliconcompiler.tools.openroad.physyn`
`['flowgraph', 'asicflow', 'physynmin', '0', 'input']`	`('physyn', '0')` `('physyn', '1')` `('physyn', '2')`
`['flowgraph', 'asicflow', 'physynmin', '0', 'tool']`	`builtin`
`['flowgraph', 'asicflow', 'physynmin', '0', 'task']`	`minimum`
`['flowgraph', 'asicflow', 'physynmin', '0', 'taskmodule']`	`siliconcompiler.tools.builtin.minimum`
`['flowgraph', 'asicflow', 'place', '0', 'input']`	`('physynmin', '0')`
`['flowgraph', 'asicflow', 'place', '0', 'weight', 'cellarea']`	`1.0`
`['flowgraph', 'asicflow', 'place', '0', 'weight', 'peakpower']`	`1.0`
`['flowgraph', 'asicflow', 'place', '0', 'weight', 'leakagepower']`	`1.0`
`['flowgraph', 'asicflow', 'place', '0', 'goal', 'errors']`	`0.0`
`['flowgraph', 'asicflow', 'place', '0', 'goal', 'setupwns']`	`0.0`
`['flowgraph', 'asicflow', 'place', '0', 'goal', 'setuptns']`	`0.0`
`['flowgraph', 'asicflow', 'place', '0', 'tool']`	`openroad`
`['flowgraph', 'asicflow', 'place', '0', 'task']`	`place`
`['flowgraph', 'asicflow', 'place', '0', 'taskmodule']`	`siliconcompiler.tools.openroad.place`
`['flowgraph', 'asicflow', 'place', '1', 'input']`	`('physynmin', '0')`
`['flowgraph', 'asicflow', 'place', '1', 'weight', 'cellarea']`	`1.0`
`['flowgraph', 'asicflow', 'place', '1', 'weight', 'peakpower']`	`1.0`
`['flowgraph', 'asicflow', 'place', '1', 'weight', 'leakagepower']`	`1.0`
`['flowgraph', 'asicflow', 'place', '1', 'goal', 'errors']`	`0.0`
`['flowgraph', 'asicflow', 'place', '1', 'goal', 'setupwns']`	`0.0`
`['flowgraph', 'asicflow', 'place', '1', 'goal', 'setuptns']`	`0.0`
`['flowgraph', 'asicflow', 'place', '1', 'tool']`	`openroad`
`['flowgraph', 'asicflow', 'place', '1', 'task']`	`place`
`['flowgraph', 'asicflow', 'place', '1', 'taskmodule']`	`siliconcompiler.tools.openroad.place`
`['flowgraph', 'asicflow', 'place', '2', 'input']`	`('physynmin', '0')`
`['flowgraph', 'asicflow', 'place', '2', 'weight', 'cellarea']`	`1.0`
`['flowgraph', 'asicflow', 'place', '2', 'weight', 'peakpower']`	`1.0`
`['flowgraph', 'asicflow', 'place', '2', 'weight', 'leakagepower']`	`1.0`
`['flowgraph', 'asicflow', 'place', '2', 'goal', 'errors']`	`0.0`
`['flowgraph', 'asicflow', 'place', '2', 'goal', 'setupwns']`	`0.0`
`['flowgraph', 'asicflow', 'place', '2', 'goal', 'setuptns']`	`0.0`
`['flowgraph', 'asicflow', 'place', '2', 'tool']`	`openroad`
`['flowgraph', 'asicflow', 'place', '2', 'task']`	`place`
`['flowgraph', 'asicflow', 'place', '2', 'taskmodule']`	`siliconcompiler.tools.openroad.place`
`['flowgraph', 'asicflow', 'placemin', '0', 'input']`	`('place', '0')` `('place', '1')` `('place', '2')`
`['flowgraph', 'asicflow', 'placemin', '0', 'tool']`	`builtin`
`['flowgraph', 'asicflow', 'placemin', '0', 'task']`	`minimum`
`['flowgraph', 'asicflow', 'placemin', '0', 'taskmodule']`	`siliconcompiler.tools.builtin.minimum`
`['flowgraph', 'asicflow', 'cts', '0', 'input']`	`('placemin', '0')`
`['flowgraph', 'asicflow', 'cts', '0', 'weight', 'cellarea']`	`1.0`
`['flowgraph', 'asicflow', 'cts', '0', 'weight', 'peakpower']`	`1.0`
`['flowgraph', 'asicflow', 'cts', '0', 'weight', 'leakagepower']`	`1.0`
`['flowgraph', 'asicflow', 'cts', '0', 'goal', 'errors']`	`0.0`
`['flowgraph', 'asicflow', 'cts', '0', 'goal', 'setupwns']`	`0.0`
`['flowgraph', 'asicflow', 'cts', '0', 'goal', 'setuptns']`	`0.0`
`['flowgraph', 'asicflow', 'cts', '0', 'tool']`	`openroad`
`['flowgraph', 'asicflow', 'cts', '0', 'task']`	`cts`
`['flowgraph', 'asicflow', 'cts', '0', 'taskmodule']`	`siliconcompiler.tools.openroad.cts`
`['flowgraph', 'asicflow', 'cts', '1', 'input']`	`('placemin', '0')`
`['flowgraph', 'asicflow', 'cts', '1', 'weight', 'cellarea']`	`1.0`
`['flowgraph', 'asicflow', 'cts', '1', 'weight', 'peakpower']`	`1.0`
`['flowgraph', 'asicflow', 'cts', '1', 'weight', 'leakagepower']`	`1.0`
`['flowgraph', 'asicflow', 'cts', '1', 'goal', 'errors']`	`0.0`
`['flowgraph', 'asicflow', 'cts', '1', 'goal', 'setupwns']`	`0.0`
`['flowgraph', 'asicflow', 'cts', '1', 'goal', 'setuptns']`	`0.0`
`['flowgraph', 'asicflow', 'cts', '1', 'tool']`	`openroad`
`['flowgraph', 'asicflow', 'cts', '1', 'task']`	`cts`
`['flowgraph', 'asicflow', 'cts', '1', 'taskmodule']`	`siliconcompiler.tools.openroad.cts`
`['flowgraph', 'asicflow', 'cts', '2', 'input']`	`('placemin', '0')`
`['flowgraph', 'asicflow', 'cts', '2', 'weight', 'cellarea']`	`1.0`
`['flowgraph', 'asicflow', 'cts', '2', 'weight', 'peakpower']`	`1.0`
`['flowgraph', 'asicflow', 'cts', '2', 'weight', 'leakagepower']`	`1.0`
`['flowgraph', 'asicflow', 'cts', '2', 'goal', 'errors']`	`0.0`
`['flowgraph', 'asicflow', 'cts', '2', 'goal', 'setupwns']`	`0.0`
`['flowgraph', 'asicflow', 'cts', '2', 'goal', 'setuptns']`	`0.0`
`['flowgraph', 'asicflow', 'cts', '2', 'tool']`	`openroad`
`['flowgraph', 'asicflow', 'cts', '2', 'task']`	`cts`
`['flowgraph', 'asicflow', 'cts', '2', 'taskmodule']`	`siliconcompiler.tools.openroad.cts`
`['flowgraph', 'asicflow', 'ctsmin', '0', 'input']`	`('cts', '0')` `('cts', '1')` `('cts', '2')`
`['flowgraph', 'asicflow', 'ctsmin', '0', 'tool']`	`builtin`
`['flowgraph', 'asicflow', 'ctsmin', '0', 'task']`	`minimum`
`['flowgraph', 'asicflow', 'ctsmin', '0', 'taskmodule']`	`siliconcompiler.tools.builtin.minimum`
`['flowgraph', 'asicflow', 'route', '0', 'input']`	`('ctsmin', '0')`
`['flowgraph', 'asicflow', 'route', '0', 'weight', 'cellarea']`	`1.0`
`['flowgraph', 'asicflow', 'route', '0', 'weight', 'peakpower']`	`1.0`
`['flowgraph', 'asicflow', 'route', '0', 'weight', 'leakagepower']`	`1.0`
`['flowgraph', 'asicflow', 'route', '0', 'goal', 'errors']`	`0.0`
`['flowgraph', 'asicflow', 'route', '0', 'goal', 'setupwns']`	`0.0`
`['flowgraph', 'asicflow', 'route', '0', 'goal', 'setuptns']`	`0.0`
`['flowgraph', 'asicflow', 'route', '0', 'tool']`	`openroad`
`['flowgraph', 'asicflow', 'route', '0', 'task']`	`route`
`['flowgraph', 'asicflow', 'route', '0', 'taskmodule']`	`siliconcompiler.tools.openroad.route`
`['flowgraph', 'asicflow', 'route', '1', 'input']`	`('ctsmin', '0')`
`['flowgraph', 'asicflow', 'route', '1', 'weight', 'cellarea']`	`1.0`
`['flowgraph', 'asicflow', 'route', '1', 'weight', 'peakpower']`	`1.0`
`['flowgraph', 'asicflow', 'route', '1', 'weight', 'leakagepower']`	`1.0`
`['flowgraph', 'asicflow', 'route', '1', 'goal', 'errors']`	`0.0`
`['flowgraph', 'asicflow', 'route', '1', 'goal', 'setupwns']`	`0.0`
`['flowgraph', 'asicflow', 'route', '1', 'goal', 'setuptns']`	`0.0`
`['flowgraph', 'asicflow', 'route', '1', 'tool']`	`openroad`
`['flowgraph', 'asicflow', 'route', '1', 'task']`	`route`
`['flowgraph', 'asicflow', 'route', '1', 'taskmodule']`	`siliconcompiler.tools.openroad.route`
`['flowgraph', 'asicflow', 'route', '2', 'input']`	`('ctsmin', '0')`
`['flowgraph', 'asicflow', 'route', '2', 'weight', 'cellarea']`	`1.0`
`['flowgraph', 'asicflow', 'route', '2', 'weight', 'peakpower']`	`1.0`
`['flowgraph', 'asicflow', 'route', '2', 'weight', 'leakagepower']`	`1.0`
`['flowgraph', 'asicflow', 'route', '2', 'goal', 'errors']`	`0.0`
`['flowgraph', 'asicflow', 'route', '2', 'goal', 'setupwns']`	`0.0`
`['flowgraph', 'asicflow', 'route', '2', 'goal', 'setuptns']`	`0.0`
`['flowgraph', 'asicflow', 'route', '2', 'tool']`	`openroad`
`['flowgraph', 'asicflow', 'route', '2', 'task']`	`route`
`['flowgraph', 'asicflow', 'route', '2', 'taskmodule']`	`siliconcompiler.tools.openroad.route`
`['flowgraph', 'asicflow', 'routemin', '0', 'input']`	`('route', '0')` `('route', '1')` `('route', '2')`
`['flowgraph', 'asicflow', 'routemin', '0', 'tool']`	`builtin`
`['flowgraph', 'asicflow', 'routemin', '0', 'task']`	`minimum`
`['flowgraph', 'asicflow', 'routemin', '0', 'taskmodule']`	`siliconcompiler.tools.builtin.minimum`
`['flowgraph', 'asicflow', 'dfm', '0', 'input']`	`('routemin', '0')`
`['flowgraph', 'asicflow', 'dfm', '0', 'weight', 'cellarea']`	`1.0`
`['flowgraph', 'asicflow', 'dfm', '0', 'weight', 'peakpower']`	`1.0`
`['flowgraph', 'asicflow', 'dfm', '0', 'weight', 'leakagepower']`	`1.0`
`['flowgraph', 'asicflow', 'dfm', '0', 'goal', 'errors']`	`0.0`
`['flowgraph', 'asicflow', 'dfm', '0', 'goal', 'setupwns']`	`0.0`
`['flowgraph', 'asicflow', 'dfm', '0', 'goal', 'setuptns']`	`0.0`
`['flowgraph', 'asicflow', 'dfm', '0', 'tool']`	`openroad`
`['flowgraph', 'asicflow', 'dfm', '0', 'task']`	`dfm`
`['flowgraph', 'asicflow', 'dfm', '0', 'taskmodule']`	`siliconcompiler.tools.openroad.dfm`
`['flowgraph', 'asicflow', 'export', '0', 'input']`	`('dfm', '0')`
`['flowgraph', 'asicflow', 'export', '0', 'tool']`	`klayout`
`['flowgraph', 'asicflow', 'export', '0', 'task']`	`export`
`['flowgraph', 'asicflow', 'export', '0', 'taskmodule']`	`siliconcompiler.tools.klayout.export`
`['flowgraph', 'asicflow', 'export', '1', 'input']`	`('dfm', '0')`
`['flowgraph', 'asicflow', 'export', '1', 'tool']`	`openroad`
`['flowgraph', 'asicflow', 'export', '1', 'task']`	`export`
`['flowgraph', 'asicflow', 'export', '1', 'taskmodule']`	`siliconcompiler.tools.openroad.export`

2.2. asictopflow#

A flow for stitching together hardened blocks without doing any automated place-and-route.

This flow generates a GDS and a netlist for passing to a verification/signoff flow.

Setup file: asictopflow.py

2.2.1. Configuration#

2.2.1.1. asictopflow#

Keypath	Value
`['flowgraph', 'asictopflow', 'import', '0', 'goal', 'errors']`	`0.0`
`['flowgraph', 'asictopflow', 'import', '0', 'tool']`	`surelog`
`['flowgraph', 'asictopflow', 'import', '0', 'task']`	`parse`
`['flowgraph', 'asictopflow', 'import', '0', 'taskmodule']`	`siliconcompiler.tools.surelog.parse`
`['flowgraph', 'asictopflow', 'syn', '0', 'input']`	`('import', '0')`
`['flowgraph', 'asictopflow', 'syn', '0', 'goal', 'errors']`	`0.0`
`['flowgraph', 'asictopflow', 'syn', '0', 'tool']`	`yosys`
`['flowgraph', 'asictopflow', 'syn', '0', 'task']`	`syn_asic`
`['flowgraph', 'asictopflow', 'syn', '0', 'taskmodule']`	`siliconcompiler.tools.yosys.syn_asic`
`['flowgraph', 'asictopflow', 'export', '0', 'input']`	`('import', '0')`
`['flowgraph', 'asictopflow', 'export', '0', 'goal', 'errors']`	`0.0`
`['flowgraph', 'asictopflow', 'export', '0', 'tool']`	`klayout`
`['flowgraph', 'asictopflow', 'export', '0', 'task']`	`export`
`['flowgraph', 'asictopflow', 'export', '0', 'taskmodule']`	`siliconcompiler.tools.klayout.export`

2.3. dvflow#

A configurable constrained random stimulus DV flow.

The verification pipeline includes the followins teps:

import: Sources are collected and packaged for compilation
compile: RTL sources are compiled into object form (once)
testgen: A random seed is used to generate a unique test
refsim: A golden trace of test is generated using a reference sim.
sim: Compiled RTL is exercised using generated test
compare: The outputs of the sim and refsim are compared
signoff: Parallel verification pipelines are merged and checked

The dvflow can be parametrized using a single ‘np’ parameter. Setting ‘np’ > 1 results in multiple independent verificaiton pipelines to be launched.

This flow is a WIP

Setup file: dvflow.py

2.3.1. Configuration#

2.3.1.1. dvflow#

Keypath	Value
`['flowgraph', 'dvflow', 'import', '0', 'tool']`	`surelog`
`['flowgraph', 'dvflow', 'import', '0', 'task']`	`parse`
`['flowgraph', 'dvflow', 'import', '0', 'taskmodule']`	`siliconcompiler.tools.surelog.parse`
`['flowgraph', 'dvflow', 'compile', '0', 'input']`	`('import', '0')`
`['flowgraph', 'dvflow', 'compile', '0', 'tool']`	`verilator`
`['flowgraph', 'dvflow', 'compile', '0', 'task']`	`compile`
`['flowgraph', 'dvflow', 'compile', '0', 'taskmodule']`	`siliconcompiler.tools.verilator.compile`
`['flowgraph', 'dvflow', 'signoff', '0', 'input']`	`('compile', '0')` `('compile', '1')` `('compile', '2')` `('compile', '3')` `('compile', '4')`
`['flowgraph', 'dvflow', 'signoff', '0', 'tool']`	`builtin`
`['flowgraph', 'dvflow', 'signoff', '0', 'task']`	`verify`
`['flowgraph', 'dvflow', 'signoff', '0', 'taskmodule']`	`siliconcompiler.tools.builtin.verify`

2.4. fpgaflow#

A configurable FPGA compilation flow.

The ‘fpgaflow’ module is a configurable FPGA flow with support for open source and commercial tool flows. The fpgaflow relies on the FPGA partname to determine which design tools to use for RTL to bitstream generation. All flows go through a common design import step that collects all source files from disk before proceeding. The implementation pipeline and tools used depend on the FPGA device being targeted. The following step convention is recommended for tools.

import: Sources are collected and packaged for compilation
syn: Synthesize RTL into an device specific netlist
apr: FPGA specific placement and routing step
bitstream: Bitstream generation
program: Program the device

Some FPGA target flows have a single ‘compile’ step that combines the syn, apr, and bitstream steps.

The fpgaflow can be configured througthe following schema parameters

Schema keypaths:

[‘fpga’, ‘partname’]: Used to select partname to vendor and tool flow
[‘fpga’, ‘program’]: Used to turn on/off HW programming step

Setup file: fpgaflow.py

2.4.1. Configuration#

2.4.1.1. fpgaflow#

Keypath	Value
`['flowgraph', 'fpgaflow', 'import', '0', 'weight', 'luts']`	`1.0`
`['flowgraph', 'fpgaflow', 'import', '0', 'weight', 'dsps']`	`1.0`
`['flowgraph', 'fpgaflow', 'import', '0', 'weight', 'brams']`	`1.0`
`['flowgraph', 'fpgaflow', 'import', '0', 'weight', 'peakpower']`	`1.0`
`['flowgraph', 'fpgaflow', 'import', '0', 'weight', 'leakagepower']`	`1.0`
`['flowgraph', 'fpgaflow', 'import', '0', 'weight', 'registers']`	`1.0`
`['flowgraph', 'fpgaflow', 'import', '0', 'weight', 'pins']`	`1.0`
`['flowgraph', 'fpgaflow', 'import', '0', 'goal', 'errors']`	`0.0`
`['flowgraph', 'fpgaflow', 'import', '0', 'goal', 'warnings']`	`0.0`
`['flowgraph', 'fpgaflow', 'import', '0', 'goal', 'drvs']`	`0.0`
`['flowgraph', 'fpgaflow', 'import', '0', 'goal', 'unconstrained']`	`0.0`
`['flowgraph', 'fpgaflow', 'import', '0', 'goal', 'holdwns']`	`0.0`
`['flowgraph', 'fpgaflow', 'import', '0', 'goal', 'holdtns']`	`0.0`
`['flowgraph', 'fpgaflow', 'import', '0', 'goal', 'holdpaths']`	`0.0`
`['flowgraph', 'fpgaflow', 'import', '0', 'goal', 'setupwns']`	`0.0`
`['flowgraph', 'fpgaflow', 'import', '0', 'goal', 'setuptns']`	`0.0`
`['flowgraph', 'fpgaflow', 'import', '0', 'goal', 'setuppaths']`	`0.0`
`['flowgraph', 'fpgaflow', 'import', '0', 'tool']`	`surelog`
`['flowgraph', 'fpgaflow', 'import', '0', 'task']`	`parse`
`['flowgraph', 'fpgaflow', 'import', '0', 'taskmodule']`	`siliconcompiler.tools.surelog.parse`
`['flowgraph', 'fpgaflow', 'syn_fpga', '0', 'input']`	`('import', '0')`
`['flowgraph', 'fpgaflow', 'syn_fpga', '0', 'weight', 'luts']`	`1.0`
`['flowgraph', 'fpgaflow', 'syn_fpga', '0', 'weight', 'dsps']`	`1.0`
`['flowgraph', 'fpgaflow', 'syn_fpga', '0', 'weight', 'brams']`	`1.0`
`['flowgraph', 'fpgaflow', 'syn_fpga', '0', 'weight', 'peakpower']`	`1.0`
`['flowgraph', 'fpgaflow', 'syn_fpga', '0', 'weight', 'leakagepower']`	`1.0`
`['flowgraph', 'fpgaflow', 'syn_fpga', '0', 'weight', 'registers']`	`1.0`
`['flowgraph', 'fpgaflow', 'syn_fpga', '0', 'weight', 'pins']`	`1.0`
`['flowgraph', 'fpgaflow', 'syn_fpga', '0', 'goal', 'errors']`	`0.0`
`['flowgraph', 'fpgaflow', 'syn_fpga', '0', 'goal', 'warnings']`	`0.0`
`['flowgraph', 'fpgaflow', 'syn_fpga', '0', 'goal', 'drvs']`	`0.0`
`['flowgraph', 'fpgaflow', 'syn_fpga', '0', 'goal', 'unconstrained']`	`0.0`
`['flowgraph', 'fpgaflow', 'syn_fpga', '0', 'goal', 'holdwns']`	`0.0`
`['flowgraph', 'fpgaflow', 'syn_fpga', '0', 'goal', 'holdtns']`	`0.0`
`['flowgraph', 'fpgaflow', 'syn_fpga', '0', 'goal', 'holdpaths']`	`0.0`
`['flowgraph', 'fpgaflow', 'syn_fpga', '0', 'goal', 'setupwns']`	`0.0`
`['flowgraph', 'fpgaflow', 'syn_fpga', '0', 'goal', 'setuptns']`	`0.0`
`['flowgraph', 'fpgaflow', 'syn_fpga', '0', 'goal', 'setuppaths']`	`0.0`
`['flowgraph', 'fpgaflow', 'syn_fpga', '0', 'tool']`	`yosys`
`['flowgraph', 'fpgaflow', 'syn_fpga', '0', 'task']`	`syn_fpga`
`['flowgraph', 'fpgaflow', 'syn_fpga', '0', 'taskmodule']`	`siliconcompiler.tools.yosys.syn_fpga`
`['flowgraph', 'fpgaflow', 'apr', '0', 'input']`	`('syn_fpga', '0')`
`['flowgraph', 'fpgaflow', 'apr', '0', 'weight', 'luts']`	`1.0`
`['flowgraph', 'fpgaflow', 'apr', '0', 'weight', 'dsps']`	`1.0`
`['flowgraph', 'fpgaflow', 'apr', '0', 'weight', 'brams']`	`1.0`
`['flowgraph', 'fpgaflow', 'apr', '0', 'weight', 'peakpower']`	`1.0`
`['flowgraph', 'fpgaflow', 'apr', '0', 'weight', 'leakagepower']`	`1.0`
`['flowgraph', 'fpgaflow', 'apr', '0', 'weight', 'registers']`	`1.0`
`['flowgraph', 'fpgaflow', 'apr', '0', 'weight', 'pins']`	`1.0`
`['flowgraph', 'fpgaflow', 'apr', '0', 'goal', 'errors']`	`0.0`
`['flowgraph', 'fpgaflow', 'apr', '0', 'goal', 'warnings']`	`0.0`
`['flowgraph', 'fpgaflow', 'apr', '0', 'goal', 'drvs']`	`0.0`
`['flowgraph', 'fpgaflow', 'apr', '0', 'goal', 'unconstrained']`	`0.0`
`['flowgraph', 'fpgaflow', 'apr', '0', 'goal', 'holdwns']`	`0.0`
`['flowgraph', 'fpgaflow', 'apr', '0', 'goal', 'holdtns']`	`0.0`
`['flowgraph', 'fpgaflow', 'apr', '0', 'goal', 'holdpaths']`	`0.0`
`['flowgraph', 'fpgaflow', 'apr', '0', 'goal', 'setupwns']`	`0.0`
`['flowgraph', 'fpgaflow', 'apr', '0', 'goal', 'setuptns']`	`0.0`
`['flowgraph', 'fpgaflow', 'apr', '0', 'goal', 'setuppaths']`	`0.0`
`['flowgraph', 'fpgaflow', 'apr', '0', 'tool']`	`nextpnr`
`['flowgraph', 'fpgaflow', 'apr', '0', 'task']`	`apr`
`['flowgraph', 'fpgaflow', 'apr', '0', 'taskmodule']`	`siliconcompiler.tools.nextpnr.apr`
`['flowgraph', 'fpgaflow', 'bitstream', '0', 'input']`	`('apr', '0')`
`['flowgraph', 'fpgaflow', 'bitstream', '0', 'weight', 'luts']`	`1.0`
`['flowgraph', 'fpgaflow', 'bitstream', '0', 'weight', 'dsps']`	`1.0`
`['flowgraph', 'fpgaflow', 'bitstream', '0', 'weight', 'brams']`	`1.0`
`['flowgraph', 'fpgaflow', 'bitstream', '0', 'weight', 'peakpower']`	`1.0`
`['flowgraph', 'fpgaflow', 'bitstream', '0', 'weight', 'leakagepower']`	`1.0`
`['flowgraph', 'fpgaflow', 'bitstream', '0', 'weight', 'registers']`	`1.0`
`['flowgraph', 'fpgaflow', 'bitstream', '0', 'weight', 'pins']`	`1.0`
`['flowgraph', 'fpgaflow', 'bitstream', '0', 'goal', 'errors']`	`0.0`
`['flowgraph', 'fpgaflow', 'bitstream', '0', 'goal', 'warnings']`	`0.0`
`['flowgraph', 'fpgaflow', 'bitstream', '0', 'goal', 'drvs']`	`0.0`
`['flowgraph', 'fpgaflow', 'bitstream', '0', 'goal', 'unconstrained']`	`0.0`
`['flowgraph', 'fpgaflow', 'bitstream', '0', 'goal', 'holdwns']`	`0.0`
`['flowgraph', 'fpgaflow', 'bitstream', '0', 'goal', 'holdtns']`	`0.0`
`['flowgraph', 'fpgaflow', 'bitstream', '0', 'goal', 'holdpaths']`	`0.0`
`['flowgraph', 'fpgaflow', 'bitstream', '0', 'goal', 'setupwns']`	`0.0`
`['flowgraph', 'fpgaflow', 'bitstream', '0', 'goal', 'setuptns']`	`0.0`
`['flowgraph', 'fpgaflow', 'bitstream', '0', 'goal', 'setuppaths']`	`0.0`
`['flowgraph', 'fpgaflow', 'bitstream', '0', 'tool']`	`icepack`
`['flowgraph', 'fpgaflow', 'bitstream', '0', 'task']`	`bitstream`
`['flowgraph', 'fpgaflow', 'bitstream', '0', 'taskmodule']`	`siliconcompiler.tools.icepack.bitstream`

2.5. lintflow#

An RTL linting flow.

Setup file: lintflow.py

2.5.1. Configuration#

2.5.1.1. lintflow#

Keypath	Value
`['flowgraph', 'lintflow', 'lint', '0', 'tool']`	`verilator`
`['flowgraph', 'lintflow', 'lint', '0', 'task']`	`lint`
`['flowgraph', 'lintflow', 'lint', '0', 'taskmodule']`	`siliconcompiler.tools.verilator.lint`

2.6. showflow#

A flow to show the output files generated from other flows.

Required settings for this flow are below:

filetype : Type of file to show

Optional settings for this flow are below:

np : Number of parallel show jobs to launch
screenshot : true/false, indicate if this should be configured as a screenshot

Setup file: showflow.py

2.6.1. Configuration#

2.6.1.1. showflow#

Keypath	Value
`['flowgraph', 'showflow', 'import', '0', 'tool']`	`builtin`
`['flowgraph', 'showflow', 'import', '0', 'task']`	`nop`
`['flowgraph', 'showflow', 'import', '0', 'taskmodule']`	`siliconcompiler.tools.builtin.nop`
`['flowgraph', 'showflow', 'show', '0', 'input']`	`('import', '0')`
`['flowgraph', 'showflow', 'show', '0', 'tool']`	`klayout`
`['flowgraph', 'showflow', 'show', '0', 'task']`	`show`
`['flowgraph', 'showflow', 'show', '0', 'taskmodule']`	`siliconcompiler.tools.klayout.show`
`['flowgraph', 'showflow', 'show', '1', 'input']`	`('import', '0')`
`['flowgraph', 'showflow', 'show', '1', 'tool']`	`klayout`
`['flowgraph', 'showflow', 'show', '1', 'task']`	`show`
`['flowgraph', 'showflow', 'show', '1', 'taskmodule']`	`siliconcompiler.tools.klayout.show`
`['flowgraph', 'showflow', 'show', '2', 'input']`	`('import', '0')`
`['flowgraph', 'showflow', 'show', '2', 'tool']`	`klayout`
`['flowgraph', 'showflow', 'show', '2', 'task']`	`show`
`['flowgraph', 'showflow', 'show', '2', 'taskmodule']`	`siliconcompiler.tools.klayout.show`

2.7. signoffflow#

A flow for running LVS/DRC signoff on a GDS layout.

Inputs must be passed to this flow as follows:

flow.input('<path-to-layout>.gds')
flow.input('<path-to-netlist>.vg')

Setup file: signoffflow.py

2.7.1. Configuration#

2.7.1.1. signoffflow#

Keypath	Value
`['flowgraph', 'signoffflow', 'import', '0', 'goal', 'errors']`	`0.0`
`['flowgraph', 'signoffflow', 'import', '0', 'tool']`	`builtin`
`['flowgraph', 'signoffflow', 'import', '0', 'task']`	`nop`
`['flowgraph', 'signoffflow', 'import', '0', 'taskmodule']`	`siliconcompiler.tools.builtin.nop`
`['flowgraph', 'signoffflow', 'extspice', '0', 'input']`	`('import', '0')`
`['flowgraph', 'signoffflow', 'extspice', '0', 'goal', 'errors']`	`0.0`
`['flowgraph', 'signoffflow', 'extspice', '0', 'tool']`	`magic`
`['flowgraph', 'signoffflow', 'extspice', '0', 'task']`	`extspice`
`['flowgraph', 'signoffflow', 'extspice', '0', 'taskmodule']`	`siliconcompiler.tools.magic.extspice`
`['flowgraph', 'signoffflow', 'drc', '0', 'input']`	`('import', '0')`
`['flowgraph', 'signoffflow', 'drc', '0', 'goal', 'errors']`	`0.0`
`['flowgraph', 'signoffflow', 'drc', '0', 'tool']`	`magic`
`['flowgraph', 'signoffflow', 'drc', '0', 'task']`	`drc`
`['flowgraph', 'signoffflow', 'drc', '0', 'taskmodule']`	`siliconcompiler.tools.magic.drc`
`['flowgraph', 'signoffflow', 'lvs', '0', 'input']`	`('extspice', '0')`
`['flowgraph', 'signoffflow', 'lvs', '0', 'goal', 'errors']`	`0.0`
`['flowgraph', 'signoffflow', 'lvs', '0', 'tool']`	`netgen`
`['flowgraph', 'signoffflow', 'lvs', '0', 'task']`	`lvs`
`['flowgraph', 'signoffflow', 'lvs', '0', 'taskmodule']`	`siliconcompiler.tools.netgen.lvs`
`['flowgraph', 'signoffflow', 'signoff', '0', 'input']`	`('lvs', '0')` `('drc', '0')`
`['flowgraph', 'signoffflow', 'signoff', '0', 'goal', 'errors']`	`0.0`
`['flowgraph', 'signoffflow', 'signoff', '0', 'tool']`	`builtin`
`['flowgraph', 'signoffflow', 'signoff', '0', 'task']`	`join`
`['flowgraph', 'signoffflow', 'signoff', '0', 'taskmodule']`	`siliconcompiler.tools.builtin.join`