3. Pre-Defined Tools#
The following are examples of pre-built tool drivers that come with SiliconCompiler which you can use for your own builds.
See the pre-built targets for examples on how these are used in conjunction with pdks, flows and libraries.
3.1. bambu#
The primary objective of the PandA project is to develop a usable framework that will enable the research of new ideas in the HW-SW Co-Design field.
The PandA framework includes methodologies supporting the research on high-level synthesis of hardware accelerators, on parallelism extraction for embedded systems, on hardware/software partitioning and mapping, on metrics for performance estimation of embedded software applications and on dynamic reconfigurable devices.
Documentation: ferrandi/PandA-bambu
Sources: ferrandi/PandA-bambu
Installation: https://panda.dei.polimi.it/?page_id=88
Setup file: bambu.py
3.1.1. Data sources#
Package |
Specifications |
siliconcompiler |
|
Keypath |
Value |
bambu |
|
--version |
|
>=0.9.6 |
3.1.2. convert#
Performs high level synthesis to generate a verilog output
Setup file: convert.py
3.2. bluespec#
Bluespec is a high-level hardware description language. It has a variety of advanced features including a powerful type system that can prevent errors prior to synthesis time, and its most distinguishing feature, Guarded Atomic Actions, allow you to define hardware components in a modular manner based on their invariants, and let the compiler pick a scheduler.
Documentation: B-Lang-org/bsc
Sources: B-Lang-org/bsc
Installation: B-Lang-org/bsc
Setup file: bluespec.py
3.2.1. Data sources#
Package |
Specifications |
siliconcompiler |
|
Keypath |
Value |
bsc |
|
-v |
|
>=2021.07 |
3.2.2. convert#
Performs high level synthesis to generate a verilog output
Setup file: convert.py
3.3. builtin#
Builtin tools for SiliconCompiler
Setup file: builtin.py
3.3.1. join#
Merges outputs from a list of input tasks.
Setup file: join.py
3.3.2. maximum#
Selects the task with the maximum metric score from a list of inputs.
Sequence of operation:
Check list of input tasks to see if all metrics meets goals
Check list of input tasks to find global min/max for each metric
Select MAX value if all metrics are met.
Normalize the min value as sel = (val - MIN) / (MAX - MIN)
Return normalized value and task name
Meeting metric goals takes precedence over compute metric scores. Only goals with values set and metrics with weights set are considered in the calculation.
Setup file: maximum.py
3.3.3. minimum#
Selects the task with the minimum metric score from a list of inputs.
Sequence of operation:
Check list of input tasks to see if all metrics meets goals
Check list of input tasks to find global min/max for each metric
Select MIN value if all metrics are met.
Normalize the min value as sel = (val - MIN) / (MAX - MIN)
Return normalized value and task name
Meeting metric goals takes precedence over compute metric scores. Only goals with values set and metrics with weights set are considered in the calculation.
Setup file: minimum.py
3.3.4. mux#
Selects a task from a list of inputs.
The selector criteria provided is used to create a custom function for selecting the best step/index pair from the inputs. Metrics and weights are passed in and used to select the step/index based on the minimum or maximum score depending on the ‘op’ argument from [‘flowgraph’, flow, step, index, ‘args’] in the form ‘minimum(metric)’ or ‘maximum(metric)’.
The function can be used to bypass the flows weight functions for the purpose of conditional flow execution and verification.
Setup file: mux.py
3.3.5. nop#
A no-operation that passes inputs to outputs.
Setup file: nop.py
3.3.6. verify#
Tests an assertion on an input task.
The input to this task is verified to ensure that all assertions are True. If any of the assertions fail, False is returned. Assertions are passed in using [‘flowgraph’, flow, step, index, ‘args’] in the form ‘metric==0.0’. The allowed conditional operators are: >, <, >=, <=, ==
Setup file: verify.py
3.4. chisel#
Chisel is a hardware design language that facilitates advanced circuit generation and design reuse for both ASIC and FPGA digital logic designs. Chisel adds hardware construction primitives to the Scala programming language, providing designers with the power of a modern programming language to write complex, parameterizable circuit generators that produce synthesizable Verilog.
Documentation: https://www.chisel-lang.org/docs
Sources: chipsalliance/chisel
Installation: The Chisel plugin relies on having the Scala Build Tool (sbt) installed. Instructions: https://www.scala-sbt.org/download.html.
Setup file: chisel.py
3.4.1. Data sources#
Package |
Specifications |
siliconcompiler |
|
Keypath |
Value |
sbt |
|
--version |
|
>=1.5.5 |
3.4.2. convert#
Performs high level synthesis to generate a verilog output
Setup file: convert.py
3.5. execute#
This tool is used to execute the output of a previous step. For example, if the flow contains a compile step which generates the next executable needed in the flow.
Setup file: execute.py
Keypath |
Value |
:exe: |
3.5.1. exec_input#
Execute the output of the previous step directly. This only works if the task receives a single file.
Setup file: exec_input.py
3.5.1.1. Configuration#
Keypath |
Value |
3.6. ghdl#
GHDL is an open-source analyzer, compiler, simulator and (experimental) synthesizer for VHDL. It allows you to analyse and elaborate sources for generating machine code from your design. Native program execution is the only way for high speed simulation.
Documentation: https://ghdl.readthedocs.io/en/latest
Sources: ghdl/ghdl
Installation: ghdl/ghdl
Setup file: ghdl.py
Keypath |
Value |
ghdl |
|
--version |
|
>=4.0.0-dev |
3.6.1. convert#
Imports VHDL and converts it to verilog
Setup file: convert.py
3.7. klayout#
Klayout is a production grade viewer and editor of GDSII and Oasis data with customizable Python and Ruby interfaces.
Documentation: https://www.klayout.de
Sources: KLayout/klayout
Installation: https://www.klayout.de/build.html
Setup file: klayout.py
3.7.1. Data sources#
Package |
Specifications |
siliconcompiler |
|
lambdapdk |
|
Keypath |
Value |
klayout |
|
|
|
>=0.28.0 |
|
json |
3.7.2. export#
Generate a GDSII file from an input DEF file
Setup file: export.py
Built using target: freepdk45_demo
3.7.2.1. Configuration#
Keypath |
Value |
(WARNING|warning) |
|
ERROR |
|
|
|
gds |
|
true |
|
true |
|
true |
|
|
4096 |
|
4096 |
1 |
|
1 |
|
10 |
|
0 |
|
|
2 |
|
|
|
|
|
|
|
|
|
3.7.2.2. Variables#
Parameters |
Help |
Extension to use for stream generation ((‘gds’, ‘oas’)) |
|
Export GDSII with timestamps |
|
true/false: true will cause KLayout to generate a screenshot of the layout |
|
true/false: true will cause kLayout to exit when complete |
|
List of layers to hide |
|
File to open |
|
File type to look for in the inputs |
|
Horizontal resolution in pixels |
|
Vertical resolution in pixels |
|
If greater than 1, splits the image into multiple segments along x-axis |
|
If greater than 1, splits the image into multiple segments along y-axis |
|
Margin around design in microns |
|
Width of lines in detailed screenshots |
|
Image oversampling used in detailed screenshots |
3.7.3. operations#
Perform unit operations on stream files. Currently supports:
rotating (rotate)
renaming (rename)
merging streams (merge)
adding streams together (add)
adding outline to top (outline)
swapping cells (swap)
adding new top cell (add_top)
renaming cells (rename_cell)
flatten
deleting layers
merging shapes
writing (write)
converting properties into text labels on design (convert_property)
To rotate:
>>> chip.add('tool', 'klayout, 'task', 'operations', 'var', 'operations', 'rotate')
To rename:
>>> chip.add('tool', 'klayout, 'task', 'operations', 'var', 'operations', \
'rename:tool,klayout,task,operations,var,new_name')
>>> chip.set('tool', 'klayout, 'task', 'operations', 'var', 'new_name', \
'chip_top')
To merge streams:
>>> chip.add('tool', 'klayout, 'task', 'operations', 'var', 'operations', \
'merge:tool,klayout,task,operations,file,fill_stream')
>>> chip.set('tool', 'klayout, 'task', 'operations', 'file', 'fill_stream', \
'./fill.gds')
or to get it from the inputs to this task:
>>> chip.add('tool', 'klayout, 'task', 'operations', 'var', 'operations', \
'merge:fill.gds')
To add streams:
>>> chip.add('tool', 'klayout, 'task', 'operations', 'var', 'operations', \
'add:tool,klayout,task,operations,file,fill_stream')
>>> chip.set('tool', 'klayout, 'task', 'operations', 'file', 'fill_stream', \
'./fill.gds')
or to get it from the inputs to this task:
>>> chip.add('tool', 'klayout, 'task', 'operations', 'var', 'operations', \
'add:fill.gds')
To add outline:
>>> chip.add('tool', 'klayout, 'task', 'operations', 'var', 'operations', \
'outline:tool,klayout,task,operations,var,outline')
>>> chip.set('tool', 'klayout, 'task', 'operations', 'var', 'outline', \
['10', '1']) # layer / purpose pair
To swap layout cells:
>>> chip.add('tool', 'klayout, 'task', 'operations', 'var', 'operations', \
'swap:tool,klayout,task,operations,var,cell_swap')
>>> chip.set('tool', 'klayout, 'task', 'operations', 'var', 'cell_swap', \
['dummy_ANDX2=ANDX2', 'dummy_NANDX2=NANDX2'])
To rename cells:
>>> chip.add('tool', 'klayout, 'task', 'operations', 'var', 'operations', \
'rename_cell:tool,klayout,task,operations,var,rename_cell')
>>> chip.set('tool', 'klayout, 'task', 'operations', 'var', 'rename_cell', \
['dummy_ANDX2=ANDX2', 'dummy_NANDX2=NANDX2'])
To add new top cell:
>>> chip.add('tool', 'klayout, 'task', 'operations', 'var', 'operations', \
'add_top:tool,klayout,task,operations,var,new_name')
>>> chip.set('tool', 'klayout, 'task', 'operations', 'var', 'new_name', \
'chip_top')
To write out a new file:
>>> chip.add('tool', 'klayout, 'task', 'operations', 'var', 'operations', \
'write:combined.gds')
To convert stream properties to text labels:
>>> chip.add('tool', 'klayout, 'task', 'operations', 'var', 'operations', \
'convert_property:tool,klayout,task,operations,var,convert_c4_bumps')
>>> chip.set('tool', 'klayout, 'task', 'operations', 'var', 'convert_c4_bumps', \
['10', '2', \ # layer / purpose pair for the source of the labels
'3' \ # stream property number
'85', '5']) # (optional) destination layer / purpose pair, if not provided
# the source pair will be used instead.
Setup file: operations.py
Built using target: freepdk45_demo
3.7.3.1. Configuration#
Keypath |
Value |
|
(WARNING|warning) |
|
ERROR |
|
|
gds |
|
|
true |
|
|
input,layout,gds |
|
|
|
|
3.7.3.2. Variables#
Parameters |
Help |
Extension to use for stream generation ((‘gds’, ‘oas’)) |
|
Export GDSII with timestamps |
3.7.4. screenshot#
Generate a PNG file from a layout file
Setup file: screenshot.py
Built using target: freepdk45_demo
3.7.4.1. Configuration#
Keypath |
Value |
|
(WARNING|warning) |
|
ERROR |
|
|
|
<path> |
|
true |
|
4096 |
|
4096 |
1 |
|
1 |
|
10 |
|
|
0 |
|
2 |
|
|
tool,klayout,task,screenshot,var,show_filepath |
|
|
|
|
3.7.4.2. Variables#
Parameters |
Help |
File to open |
|
true/false: true will cause kLayout to exit when complete |
|
List of layers to hide |
|
File type to look for in the inputs |
|
Horizontal resolution in pixels |
|
Vertical resolution in pixels |
|
If greater than 1, splits the image into multiple segments along x-axis |
|
If greater than 1, splits the image into multiple segments along y-axis |
|
Margin around design in microns |
|
Width of lines in detailed screenshots |
|
Image oversampling used in detailed screenshots |
3.7.5. show#
Show a layout in kLayout
Setup file: show.py
Built using target: freepdk45_demo
3.7.5.1. Configuration#
Keypath |
Value |
(WARNING|warning) |
|
ERROR |
|
|
|
<path> |
|
false |
|
tool,klayout,task,show,var,show_filepath |
|
|
|
|
3.7.5.2. Variables#
Parameters |
Help |
File to open |
|
true/false: true will cause kLayout to exit when complete |
|
List of layers to hide |
|
File type to look for in the inputs |
3.8. magic#
Magic is a chip layout viewer, editor, and circuit verifier with built in DRC and LVS engines.
Documentation: http://opencircuitdesign.com/magic/userguide.html
Installation: RTimothyEdwards/magic
Sources: RTimothyEdwards/magic
Setup file: magic.py
3.8.1. Data sources#
Package |
Specifications |
siliconcompiler |
|
lambdapdk |
|
Keypath |
Value |
magic |
|
--version |
|
>=8.3.196 |
|
tcl |
3.8.2. drc#
Perform DRC checks
Setup file: drc.py
Built using target: freepdk45_demo
3.8.2.1. Configuration#
Keypath |
Value |
^Error |
|
warning |
|
|
|
|
|
|
|
|
|
2 |
3.8.3. extspice#
Extract spice netlists from a GDS file for simulation use
Setup file: extspice.py
Built using target: freepdk45_demo
3.8.3.1. Configuration#
Keypath |
Value |
^Error |
|
warning |
|
|
|
|
|
|
|
|
|
|
|
2 |
3.9. montage#
ImageMagick® is a free and open-source software suite for displaying, converting, and editing raster image and vector image files. It can read and write over 200 image file formats, and can support a wide range of image manipulation operations, such as resizing, cropping, and color correction. Use the montage program to create a composite image by combining several separate images. The images are tiled on the composite image optionally adorned with a border, frame, image name, and more
Documentation: https://imagemagick.org/
Sources: ImageMagick/ImageMagick
Installation: ImageMagick/ImageMagick
Setup file: montage.py
Keypath |
Value |
montage |
|
-version |
|
>=6.9.0 |
3.9.1. tile#
Tiles input images into a single output image.
Notes: Need to make ensure that /etc/ImageMagick-6/policy.xml
<policy domain=”resource” name=”memory” value=”8GiB”/> <policy domain=”resource” name=”map” value=”8GiB”/> <policy domain=”resource” name=”width” value=”32KP”/> <policy domain=”resource” name=”height” value=”32KP”/> <policy domain=”resource” name=”area” value=”1GP”/> <policy domain=”resource” name=”disk” value=”8GiB”/>
This ensures there are enough resources available to generate the final image.
Setup file: tile.py
3.9.1.1. Configuration#
Keypath |
Value |
|
|
2 |
|
2 |
|
|
|
|
3.9.1.2. Variables#
Parameters |
Help |
Number of bins along the x-axis |
|
Number of bins along the y-axis |
3.10. openfpgaloader#
The OpenFPGALoader is a universal utility for programming FPGAs. Compatible with many boards, cables and FPGA from major manufacturers (Xilinx, Altera/Intel, Lattice, Gowin, Efinix, Anlogic). openFPGALoader works on Linux, Windows and macOS.
Documentation: trabucayre/openFPGALoader
Sources: trabucayre/openFPGALoader
Installation: trabucayre/openFPGALoader
Status: SC integration WIP
Setup file: openfpgaloader.py
Keypath |
Value |
openfpgaloader |
|
--Version |
|
0.5.0 |
3.11. openroad#
OpenROAD is an automated physical design platform for integrated circuit design with a complete set of features needed to translate a synthesized netlist to a tapeout ready GDSII.
Documentation: https://openroad.readthedocs.io/
Sources: The-OpenROAD-Project/OpenROAD
Installation: The-OpenROAD-Project/OpenROAD
Setup file: openroad.py
3.11.1. Data sources#
Package |
Specifications |
siliconcompiler |
|
lambdapdk |
|
Keypath |
Value |
openroad |
|
-version |
|
>=v2.0-13145 |
|
tcl |
3.11.2. cts#
Perform clock tree synthesis and timing repair
Setup file: cts.py
Built using target: asap7_demo
3.11.2.1. Configuration#
Keypath |
Value |
^\[WARNING|^Warning |
|
^\[ERROR |
|
-exit -metrics reports/metrics.json |
|
|
10 |
|
true |
|
true |
|
16 |
|
16 |
|
0.0 |
|
0.0 |
|
10 |
typical |
|
|
0 |
|
site |
|
|
|
|
false |
|
true |
|
true |
|
0.60 |
|
|
2 |
|
true |
|
true |
|
0.00 |
|
true |
|
1 |
|
0 |
|
false |
true |
|
|
0 |
|
BUFx4_ASAP7_75t_R |
|
60 |
|
100 |
|
30 |
|
true |
|
true |
|
0.0 |
|
0.0 |
|
0.0 |
|
0.0 |
|
false |
|
false |
|
true |
|
true |
|
100 |
|
false |
|
100 |
|
0 |
|
false |
|
false |
|
M2 |
|
M7 |
|
M2 |
|
M7 |
|
3 |
0 |
|
true |
|
true |
|
|
false |
|
false |
true |
|
typical |
|
|
|
|
|
|
|
|
|
|
|
|
|
2 |
3.11.2.2. Variables#
Parameters |
Help |
list of “tool key level” to enable debugging of OpenROAD |
|
Factor to apply when writing the abstract lef |
|
true/false, fill all layers when writing the abstract lef |
|
true/false, enable generating images of the design at the end of the task |
|
number of X bins to use for heatmap image generation |
|
number of Y bins to use for heatmap image generation |
|
timing derating factor to use for hold corners |
|
timing derating factor to use for setup corners |
|
number of paths to report timing for |
|
corner to use for power analysis |
|
buffer cell to use when auto generating timing constraints |
|
maximum distance between tie high/low cells in microns |
|
Snapping strategy to use when placing macros. Allowed values: none, site, manufacturing_grid |
|
additional arguments to pass along to the pin placer. |
|
macro halo to use when performing automated macro placement ([x, y] in microns) |
|
macro channel to use when performing automated macro placement ([x, y] in microns) |
|
true/false, enables the RTLMP macro placement |
|
minimum number of instances to use while clustering for macro placement |
|
maximum number of instances to use while clustering for macro placement |
|
minimum number of macros to use while clustering for macro placement |
|
maximum number of macros to use while clustering for macro placement |
|
true/false, when true enables power grid generation |
|
true/false, when true enables IR drop analysis |
|
list of nets to skip power grid analysis on |
|
global placement density (0.0 - 1.0) |
|
global placement cell padding in number of sites |
|
true/false, when true global placement will consider the routability of the design |
|
true/false, when true global placement will consider the timing performance of the design |
|
percent of remaining area density to apply above uniform density (0.00 - 0.99) |
|
true/false, when enabled a global placement is performed without considering the impact of the pin placements |
|
detailed placement cell padding in number of sites |
|
maximum cell movement in detailed placement in microns, 0 will result in the tool default maximum displacement |
|
true/false, disallow single site gaps in detail placement |
|
true/false, when true the detailed placement optimization will be performed |
|
maximum cell movement in detailed placement optimization in microns, 0 will result in the tool default maximum displacement |
|
buffer to use during clock tree synthesis |
|
maximum distance between buffers during clock tree synthesis in microns |
|
clustering distance to use during clock tree synthesis in microns |
|
number of instances in a cluster to use during clock tree synthesis |
|
perform level balancing in clock tree synthesis |
|
make clock tree synthesis aware of obstructions |
|
specifies the margin to apply when performing setup repair in library timing units |
|
specifies the margin to apply when performing setup repair in library timing units |
|
specifies the amount of margin to apply to max slew repairs in percent (0 - 100) |
|
specifies the amount of margin to apply to max capacitance repairs in percent (0 - 100) |
|
true/false, when true enables adding buffers to the input ports |
|
true/false, when true enables adding buffers to the output ports |
|
true/false, skip pin swap optimization |
|
true/false, skip gate cloning optimization |
|
percentage of violating nets to attempt to repair (0 - 100) |
|
true/false, when true perform pin access before global routing |
|
maximum number of iterations to use in global routing when attempting to solve overflow |
|
macro extension distance in number of gcells, this can be useful when the detailed router needs additional space to avoid DRCs |
|
true/false, when true allow global routing to finish with congestion |
|
true/false, when true allow global routing to finish with overflow |
|
minimum layer to use for global routing of signals |
|
maximum layer to use for global routing of signals |
|
minimum layer to use for global routing of clock nets |
|
maximum layer to use for global routing of clock nets |
|
maximum number of repair iterations to use during antenna repairs |
|
adds a margin to the antenna ratios (0 - 100) |
|
true/false, flag to indicate whether to check for antenna violations |
|
true/false, flag to indicate whether to repair antenna violations |
|
true/false, when true turns off via generation in detailed router and only uses the specified tech vias |
|
when set this specifies to the detailed router the specific process node |
|
TODO |
|
TODO |
|
TODO |
|
true/false, when true performs a via ripup step after detailed routing to remove power vias that are causing DRC violations |
|
list of default vias to use for detail routing |
|
list of layers to treat as unidirectional regardless of what the tech lef specifies |
|
true/false, when true enables adding fill, if enabled by the PDK, to the design |
|
list of parasitic extraction corners to use |
3.11.2.3. Files#
Parameters |
Help |
list of files to use for specifying global connections |
|
tap cell insertion script |
|
script to generate a padring using ICeWall in OpenROAD |
|
script constrain pin placement |
|
list of files to use for power grid generation |
|
file used to specify the parasitics for estimation |
3.11.3. dfm#
Design for manufacturing step will insert fill if specified
Setup file: dfm.py
Built using target: asap7_demo
3.11.3.1. Configuration#
Keypath |
Value |
^\[WARNING|^Warning |
|
^\[ERROR |
|
-exit -metrics reports/metrics.json |
|
|
10 |
|
true |
|
true |
|
16 |
|
16 |
|
0.0 |
|
0.0 |
|
10 |
typical |
|
|
0 |
|
site |
|
|
|
|
false |
|
true |
|
true |
|
0.60 |
|
|
2 |
|
true |
|
true |
|
0.00 |
|
true |
|
1 |
|
0 |
|
false |
true |
|
|
0 |
|
BUFx4_ASAP7_75t_R |
|
60 |
|
100 |
|
30 |
|
true |
|
true |
|
0.0 |
|
0.0 |
|
0.0 |
|
0.0 |
|
false |
|
false |
|
true |
|
true |
|
100 |
|
false |
|
100 |
|
0 |
|
false |
|
false |
|
M2 |
|
M7 |
|
M2 |
|
M7 |
|
3 |
0 |
|
true |
|
true |
|
|
false |
|
false |
true |
|
typical |
|
|
|
|
|
|
|
|
|
|
|
|
|
2 |
3.11.3.2. Variables#
Parameters |
Help |
list of “tool key level” to enable debugging of OpenROAD |
|
Factor to apply when writing the abstract lef |
|
true/false, fill all layers when writing the abstract lef |
|
true/false, enable generating images of the design at the end of the task |
|
number of X bins to use for heatmap image generation |
|
number of Y bins to use for heatmap image generation |
|
timing derating factor to use for hold corners |
|
timing derating factor to use for setup corners |
|
number of paths to report timing for |
|
corner to use for power analysis |
|
buffer cell to use when auto generating timing constraints |
|
maximum distance between tie high/low cells in microns |
|
Snapping strategy to use when placing macros. Allowed values: none, site, manufacturing_grid |
|
additional arguments to pass along to the pin placer. |
|
macro halo to use when performing automated macro placement ([x, y] in microns) |
|
macro channel to use when performing automated macro placement ([x, y] in microns) |
|
true/false, enables the RTLMP macro placement |
|
minimum number of instances to use while clustering for macro placement |
|
maximum number of instances to use while clustering for macro placement |
|
minimum number of macros to use while clustering for macro placement |
|
maximum number of macros to use while clustering for macro placement |
|
true/false, when true enables power grid generation |
|
true/false, when true enables IR drop analysis |
|
list of nets to skip power grid analysis on |
|
global placement density (0.0 - 1.0) |
|
global placement cell padding in number of sites |
|
true/false, when true global placement will consider the routability of the design |
|
true/false, when true global placement will consider the timing performance of the design |
|
percent of remaining area density to apply above uniform density (0.00 - 0.99) |
|
true/false, when enabled a global placement is performed without considering the impact of the pin placements |
|
detailed placement cell padding in number of sites |
|
maximum cell movement in detailed placement in microns, 0 will result in the tool default maximum displacement |
|
true/false, disallow single site gaps in detail placement |
|
true/false, when true the detailed placement optimization will be performed |
|
maximum cell movement in detailed placement optimization in microns, 0 will result in the tool default maximum displacement |
|
buffer to use during clock tree synthesis |
|
maximum distance between buffers during clock tree synthesis in microns |
|
clustering distance to use during clock tree synthesis in microns |
|
number of instances in a cluster to use during clock tree synthesis |
|
perform level balancing in clock tree synthesis |
|
make clock tree synthesis aware of obstructions |
|
specifies the margin to apply when performing setup repair in library timing units |
|
specifies the margin to apply when performing setup repair in library timing units |
|
specifies the amount of margin to apply to max slew repairs in percent (0 - 100) |
|
specifies the amount of margin to apply to max capacitance repairs in percent (0 - 100) |
|
true/false, when true enables adding buffers to the input ports |
|
true/false, when true enables adding buffers to the output ports |
|
true/false, skip pin swap optimization |
|
true/false, skip gate cloning optimization |
|
percentage of violating nets to attempt to repair (0 - 100) |
|
true/false, when true perform pin access before global routing |
|
maximum number of iterations to use in global routing when attempting to solve overflow |
|
macro extension distance in number of gcells, this can be useful when the detailed router needs additional space to avoid DRCs |
|
true/false, when true allow global routing to finish with congestion |
|
true/false, when true allow global routing to finish with overflow |
|
minimum layer to use for global routing of signals |
|
maximum layer to use for global routing of signals |
|
minimum layer to use for global routing of clock nets |
|
maximum layer to use for global routing of clock nets |
|
maximum number of repair iterations to use during antenna repairs |
|
adds a margin to the antenna ratios (0 - 100) |
|
true/false, flag to indicate whether to check for antenna violations |
|
true/false, flag to indicate whether to repair antenna violations |
|
true/false, when true turns off via generation in detailed router and only uses the specified tech vias |
|
when set this specifies to the detailed router the specific process node |
|
TODO |
|
TODO |
|
TODO |
|
true/false, when true performs a via ripup step after detailed routing to remove power vias that are causing DRC violations |
|
list of default vias to use for detail routing |
|
list of layers to treat as unidirectional regardless of what the tech lef specifies |
|
true/false, when true enables adding fill, if enabled by the PDK, to the design |
|
list of parasitic extraction corners to use |
3.11.3.3. Files#
Parameters |
Help |
list of files to use for specifying global connections |
|
tap cell insertion script |
|
script to generate a padring using ICeWall in OpenROAD |
|
script constrain pin placement |
|
list of files to use for power grid generation |
|
file used to specify the parasitics for estimation |
3.11.4. export#
Generate abstract views (LEF), timing libraries (liberty files), circuit descriptions (CDL), and parasitic annotation files (SPEF)
Setup file: export.py
Built using target: asap7_demo
3.11.4.1. Configuration#
Keypath |
Value |
^\[WARNING|^Warning |
|
^\[ERROR |
|
-exit -metrics reports/metrics.json |
|
|
10 |
|
true |
|
true |
|
16 |
|
16 |
|
0.0 |
|
0.0 |
|
10 |
|
typical |
|
0 |
|
site |
|
|
|
|
|
false |
true |
|
true |
|
|
0.60 |
|
2 |
|
true |
|
true |
|
0.00 |
|
true |
|
1 |
|
0 |
|
false |
true |
|
|
0 |
|
BUFx4_ASAP7_75t_R |
|
60 |
|
100 |
|
30 |
|
true |
|
true |
|
0.0 |
|
0.0 |
|
0.0 |
|
0.0 |
|
false |
|
false |
|
true |
|
true |
|
100 |
|
false |
|
100 |
|
0 |
|
false |
|
false |
|
M2 |
|
M7 |
|
M2 |
|
M7 |
|
3 |
0 |
|
true |
|
true |
|
|
false |
|
false |
|
true |
|
typical |
false |
|
|
|
|
|
|
|
|
|
|
|
|
|
1 |
3.11.4.2. Variables#
Parameters |
Help |
list of “tool key level” to enable debugging of OpenROAD |
|
Factor to apply when writing the abstract lef |
|
true/false, fill all layers when writing the abstract lef |
|
true/false, enable generating images of the design at the end of the task |
|
number of X bins to use for heatmap image generation |
|
number of Y bins to use for heatmap image generation |
|
timing derating factor to use for hold corners |
|
timing derating factor to use for setup corners |
|
number of paths to report timing for |
|
corner to use for power analysis |
|
buffer cell to use when auto generating timing constraints |
|
maximum distance between tie high/low cells in microns |
|
Snapping strategy to use when placing macros. Allowed values: none, site, manufacturing_grid |
|
additional arguments to pass along to the pin placer. |
|
macro halo to use when performing automated macro placement ([x, y] in microns) |
|
macro channel to use when performing automated macro placement ([x, y] in microns) |
|
true/false, enables the RTLMP macro placement |
|
minimum number of instances to use while clustering for macro placement |
|
maximum number of instances to use while clustering for macro placement |
|
minimum number of macros to use while clustering for macro placement |
|
maximum number of macros to use while clustering for macro placement |
|
true/false, when true enables power grid generation |
|
true/false, when true enables IR drop analysis |
|
list of nets to skip power grid analysis on |
|
global placement density (0.0 - 1.0) |
|
global placement cell padding in number of sites |
|
true/false, when true global placement will consider the routability of the design |
|
true/false, when true global placement will consider the timing performance of the design |
|
percent of remaining area density to apply above uniform density (0.00 - 0.99) |
|
true/false, when enabled a global placement is performed without considering the impact of the pin placements |
|
detailed placement cell padding in number of sites |
|
maximum cell movement in detailed placement in microns, 0 will result in the tool default maximum displacement |
|
true/false, disallow single site gaps in detail placement |
|
true/false, when true the detailed placement optimization will be performed |
|
maximum cell movement in detailed placement optimization in microns, 0 will result in the tool default maximum displacement |
|
buffer to use during clock tree synthesis |
|
maximum distance between buffers during clock tree synthesis in microns |
|
clustering distance to use during clock tree synthesis in microns |
|
number of instances in a cluster to use during clock tree synthesis |
|
perform level balancing in clock tree synthesis |
|
make clock tree synthesis aware of obstructions |
|
specifies the margin to apply when performing setup repair in library timing units |
|
specifies the margin to apply when performing setup repair in library timing units |
|
specifies the amount of margin to apply to max slew repairs in percent (0 - 100) |
|
specifies the amount of margin to apply to max capacitance repairs in percent (0 - 100) |
|
true/false, when true enables adding buffers to the input ports |
|
true/false, when true enables adding buffers to the output ports |
|
true/false, skip pin swap optimization |
|
true/false, skip gate cloning optimization |
|
percentage of violating nets to attempt to repair (0 - 100) |
|
true/false, when true perform pin access before global routing |
|
maximum number of iterations to use in global routing when attempting to solve overflow |
|
macro extension distance in number of gcells, this can be useful when the detailed router needs additional space to avoid DRCs |
|
true/false, when true allow global routing to finish with congestion |
|
true/false, when true allow global routing to finish with overflow |
|
minimum layer to use for global routing of signals |
|
maximum layer to use for global routing of signals |
|
minimum layer to use for global routing of clock nets |
|
maximum layer to use for global routing of clock nets |
|
maximum number of repair iterations to use during antenna repairs |
|
adds a margin to the antenna ratios (0 - 100) |
|
true/false, flag to indicate whether to check for antenna violations |
|
true/false, flag to indicate whether to repair antenna violations |
|
true/false, when true turns off via generation in detailed router and only uses the specified tech vias |
|
when set this specifies to the detailed router the specific process node |
|
TODO |
|
TODO |
|
TODO |
|
true/false, when true performs a via ripup step after detailed routing to remove power vias that are causing DRC violations |
|
list of default vias to use for detail routing |
|
list of layers to treat as unidirectional regardless of what the tech lef specifies |
|
true/false, when true enables adding fill, if enabled by the PDK, to the design |
|
list of parasitic extraction corners to use |
|
true/false, when true enables writing the CDL file for the design |
3.11.4.3. Files#
Parameters |
Help |
list of files to use for specifying global connections |
|
tap cell insertion script |
|
script to generate a padring using ICeWall in OpenROAD |
|
script constrain pin placement |
|
list of files to use for power grid generation |
|
file used to specify the parasitics for estimation |
3.11.5. floorplan#
Perform floorplanning, pin placements, macro placements and power grid generation
Setup file: floorplan.py
Built using target: asap7_demo
3.11.5.1. Configuration#
Keypath |
Value |
|
^\[WARNING|^Warning |
|
^\[ERROR |
-exit -metrics reports/metrics.json |
|
|
10 |
|
true |
|
true |
|
16 |
|
16 |
|
0.0 |
|
0.0 |
|
10 |
|
typical |
|
0 |
|
site |
|
|
|
|
|
false |
|
true |
|
true |
|
0.60 |
|
2 |
|
true |
|
true |
|
0.00 |
|
true |
|
1 |
|
0 |
|
false |
|
true |
|
0 |
|
BUFx4_ASAP7_75t_R |
|
60 |
|
100 |
|
30 |
|
true |
|
true |
|
0.0 |
|
0.0 |
|
0.0 |
|
0.0 |
|
false |
|
false |
|
true |
|
true |
|
100 |
|
false |
|
100 |
|
0 |
|
false |
|
false |
|
M2 |
|
M7 |
|
M2 |
|
M7 |
|
3 |
|
0 |
|
true |
|
true |
|
false |
|
false |
|
true |
|
typical |
|
|
|
|
|
|
|
|
|
|
|
|
2 |
3.11.5.2. Variables#
Parameters |
Help |
list of “tool key level” to enable debugging of OpenROAD |
|
Factor to apply when writing the abstract lef |
|
true/false, fill all layers when writing the abstract lef |
|
true/false, enable generating images of the design at the end of the task |
|
number of X bins to use for heatmap image generation |
|
number of Y bins to use for heatmap image generation |
|
timing derating factor to use for hold corners |
|
timing derating factor to use for setup corners |
|
number of paths to report timing for |
|
corner to use for power analysis |
|
buffer cell to use when auto generating timing constraints |
|
maximum distance between tie high/low cells in microns |
|
Snapping strategy to use when placing macros. Allowed values: none, site, manufacturing_grid |
|
additional arguments to pass along to the pin placer. |
|
macro halo to use when performing automated macro placement ([x, y] in microns) |
|
macro channel to use when performing automated macro placement ([x, y] in microns) |
|
true/false, enables the RTLMP macro placement |
|
minimum number of instances to use while clustering for macro placement |
|
maximum number of instances to use while clustering for macro placement |
|
minimum number of macros to use while clustering for macro placement |
|
maximum number of macros to use while clustering for macro placement |
|
true/false, when true enables power grid generation |
|
true/false, when true enables IR drop analysis |
|
list of nets to skip power grid analysis on |
|
global placement density (0.0 - 1.0) |
|
global placement cell padding in number of sites |
|
true/false, when true global placement will consider the routability of the design |
|
true/false, when true global placement will consider the timing performance of the design |
|
percent of remaining area density to apply above uniform density (0.00 - 0.99) |
|
true/false, when enabled a global placement is performed without considering the impact of the pin placements |
|
detailed placement cell padding in number of sites |
|
maximum cell movement in detailed placement in microns, 0 will result in the tool default maximum displacement |
|
true/false, disallow single site gaps in detail placement |
|
true/false, when true the detailed placement optimization will be performed |
|
maximum cell movement in detailed placement optimization in microns, 0 will result in the tool default maximum displacement |
|
buffer to use during clock tree synthesis |
|
maximum distance between buffers during clock tree synthesis in microns |
|
clustering distance to use during clock tree synthesis in microns |
|
number of instances in a cluster to use during clock tree synthesis |
|
perform level balancing in clock tree synthesis |
|
make clock tree synthesis aware of obstructions |
|
specifies the margin to apply when performing setup repair in library timing units |
|
specifies the margin to apply when performing setup repair in library timing units |
|
specifies the amount of margin to apply to max slew repairs in percent (0 - 100) |
|
specifies the amount of margin to apply to max capacitance repairs in percent (0 - 100) |
|
true/false, when true enables adding buffers to the input ports |
|
true/false, when true enables adding buffers to the output ports |
|
true/false, skip pin swap optimization |
|
true/false, skip gate cloning optimization |
|
percentage of violating nets to attempt to repair (0 - 100) |
|
true/false, when true perform pin access before global routing |
|
maximum number of iterations to use in global routing when attempting to solve overflow |
|
macro extension distance in number of gcells, this can be useful when the detailed router needs additional space to avoid DRCs |
|
true/false, when true allow global routing to finish with congestion |
|
true/false, when true allow global routing to finish with overflow |
|
minimum layer to use for global routing of signals |
|
maximum layer to use for global routing of signals |
|
minimum layer to use for global routing of clock nets |
|
maximum layer to use for global routing of clock nets |
|
maximum number of repair iterations to use during antenna repairs |
|
adds a margin to the antenna ratios (0 - 100) |
|
true/false, flag to indicate whether to check for antenna violations |
|
true/false, flag to indicate whether to repair antenna violations |
|
true/false, when true turns off via generation in detailed router and only uses the specified tech vias |
|
when set this specifies to the detailed router the specific process node |
|
TODO |
|
TODO |
|
TODO |
|
true/false, when true performs a via ripup step after detailed routing to remove power vias that are causing DRC violations |
|
list of default vias to use for detail routing |
|
list of layers to treat as unidirectional regardless of what the tech lef specifies |
|
true/false, when true enables adding fill, if enabled by the PDK, to the design |
|
list of parasitic extraction corners to use |
3.11.5.3. Files#
Parameters |
Help |
list of files to use for specifying global connections |
|
tap cell insertion script |
|
script to insert the padring |
|
script constrain pin placement |
|
list of files to use for power grid generation |
|
file used to specify the parasitics for estimation |
3.11.6. physyn#
Not implemented yet
Setup file: physyn.py
Built using target: asap7_demo
3.11.6.1. Configuration#
Keypath |
Value |
^\[WARNING|^Warning |
|
^\[ERROR |
|
-exit -metrics reports/metrics.json |
|
|
10 |
|
true |
|
true |
|
16 |
|
16 |
|
0.0 |
|
0.0 |
|
10 |
|
typical |
|
0 |
|
site |
|
|
|
|
|
false |
true |
|
true |
|
|
0.60 |
|
2 |
|
true |
|
true |
|
0.00 |
|
true |
|
1 |
|
0 |
|
false |
true |
|
|
0 |
|
BUFx4_ASAP7_75t_R |
|
60 |
|
100 |
|
30 |
|
true |
|
true |
|
0.0 |
|
0.0 |
|
0.0 |
|
0.0 |
|
false |
|
false |
|
true |
|
true |
|
100 |
|
false |
|
100 |
|
0 |
|
false |
|
false |
|
M2 |
|
M7 |
|
M2 |
|
M7 |
|
3 |
0 |
|
true |
|
true |
|
|
false |
|
false |
|
true |
|
typical |
|
|
|
|
|
|
|
|
|
|
|
|
2 |
3.11.6.2. Variables#
Parameters |
Help |
list of “tool key level” to enable debugging of OpenROAD |
|
Factor to apply when writing the abstract lef |
|
true/false, fill all layers when writing the abstract lef |
|
true/false, enable generating images of the design at the end of the task |
|
number of X bins to use for heatmap image generation |
|
number of Y bins to use for heatmap image generation |
|
timing derating factor to use for hold corners |
|
timing derating factor to use for setup corners |
|
number of paths to report timing for |
|
corner to use for power analysis |
|
buffer cell to use when auto generating timing constraints |
|
maximum distance between tie high/low cells in microns |
|
Snapping strategy to use when placing macros. Allowed values: none, site, manufacturing_grid |
|
additional arguments to pass along to the pin placer. |
|
macro halo to use when performing automated macro placement ([x, y] in microns) |
|
macro channel to use when performing automated macro placement ([x, y] in microns) |
|
true/false, enables the RTLMP macro placement |
|
minimum number of instances to use while clustering for macro placement |
|
maximum number of instances to use while clustering for macro placement |
|
minimum number of macros to use while clustering for macro placement |
|
maximum number of macros to use while clustering for macro placement |
|
true/false, when true enables power grid generation |
|
true/false, when true enables IR drop analysis |
|
list of nets to skip power grid analysis on |
|
global placement density (0.0 - 1.0) |
|
global placement cell padding in number of sites |
|
true/false, when true global placement will consider the routability of the design |
|
true/false, when true global placement will consider the timing performance of the design |
|
percent of remaining area density to apply above uniform density (0.00 - 0.99) |
|
true/false, when enabled a global placement is performed without considering the impact of the pin placements |
|
detailed placement cell padding in number of sites |
|
maximum cell movement in detailed placement in microns, 0 will result in the tool default maximum displacement |
|
true/false, disallow single site gaps in detail placement |
|
true/false, when true the detailed placement optimization will be performed |
|
maximum cell movement in detailed placement optimization in microns, 0 will result in the tool default maximum displacement |
|
buffer to use during clock tree synthesis |
|
maximum distance between buffers during clock tree synthesis in microns |
|
clustering distance to use during clock tree synthesis in microns |
|
number of instances in a cluster to use during clock tree synthesis |
|
perform level balancing in clock tree synthesis |
|
make clock tree synthesis aware of obstructions |
|
specifies the margin to apply when performing setup repair in library timing units |
|
specifies the margin to apply when performing setup repair in library timing units |
|
specifies the amount of margin to apply to max slew repairs in percent (0 - 100) |
|
specifies the amount of margin to apply to max capacitance repairs in percent (0 - 100) |
|
true/false, when true enables adding buffers to the input ports |
|
true/false, when true enables adding buffers to the output ports |
|
true/false, skip pin swap optimization |
|
true/false, skip gate cloning optimization |
|
percentage of violating nets to attempt to repair (0 - 100) |
|
true/false, when true perform pin access before global routing |
|
maximum number of iterations to use in global routing when attempting to solve overflow |
|
macro extension distance in number of gcells, this can be useful when the detailed router needs additional space to avoid DRCs |
|
true/false, when true allow global routing to finish with congestion |
|
true/false, when true allow global routing to finish with overflow |
|
minimum layer to use for global routing of signals |
|
maximum layer to use for global routing of signals |
|
minimum layer to use for global routing of clock nets |
|
maximum layer to use for global routing of clock nets |
|
maximum number of repair iterations to use during antenna repairs |
|
adds a margin to the antenna ratios (0 - 100) |
|
true/false, flag to indicate whether to check for antenna violations |
|
true/false, flag to indicate whether to repair antenna violations |
|
true/false, when true turns off via generation in detailed router and only uses the specified tech vias |
|
when set this specifies to the detailed router the specific process node |
|
TODO |
|
TODO |
|
TODO |
|
true/false, when true performs a via ripup step after detailed routing to remove power vias that are causing DRC violations |
|
list of default vias to use for detail routing |
|
list of layers to treat as unidirectional regardless of what the tech lef specifies |
|
true/false, when true enables adding fill, if enabled by the PDK, to the design |
|
list of parasitic extraction corners to use |
3.11.6.3. Files#
Parameters |
Help |
list of files to use for specifying global connections |
|
tap cell insertion script |
|
script to generate a padring using ICeWall in OpenROAD |
|
script constrain pin placement |
|
list of files to use for power grid generation |
|
file used to specify the parasitics for estimation |
3.11.7. place#
Perform global and detail placements along with design violation repairs
Setup file: place.py
Built using target: asap7_demo
3.11.7.1. Configuration#
Keypath |
Value |
^\[WARNING|^Warning |
|
^\[ERROR |
|
-exit -metrics reports/metrics.json |
|
|
10 |
|
true |
|
true |
|
16 |
|
16 |
|
0.0 |
|
0.0 |
|
10 |
|
typical |
|
0 |
|
site |
|
|
|
|
|
false |
true |
|
true |
|
|
0.60 |
|
2 |
|
true |
|
true |
|
0.00 |
|
true |
|
1 |
|
0 |
|
false |
true |
|
|
0 |
|
BUFx4_ASAP7_75t_R |
|
60 |
|
100 |
|
30 |
|
true |
|
true |
|
0.0 |
|
0.0 |
|
0.0 |
|
0.0 |
|
false |
|
false |
|
true |
|
true |
|
100 |
|
false |
|
100 |
|
0 |
|
false |
|
false |
|
M2 |
|
M7 |
|
M2 |
|
M7 |
|
3 |
0 |
|
true |
|
true |
|
|
false |
|
false |
|
true |
typical |
|
|
|
|
|
|
|
|
|
|
|
|
|
2 |
3.11.7.2. Variables#
Parameters |
Help |
list of “tool key level” to enable debugging of OpenROAD |
|
Factor to apply when writing the abstract lef |
|
true/false, fill all layers when writing the abstract lef |
|
true/false, enable generating images of the design at the end of the task |
|
number of X bins to use for heatmap image generation |
|
number of Y bins to use for heatmap image generation |
|
timing derating factor to use for hold corners |
|
timing derating factor to use for setup corners |
|
number of paths to report timing for |
|
corner to use for power analysis |
|
buffer cell to use when auto generating timing constraints |
|
maximum distance between tie high/low cells in microns |
|
Snapping strategy to use when placing macros. Allowed values: none, site, manufacturing_grid |
|
additional arguments to pass along to the pin placer. |
|
macro halo to use when performing automated macro placement ([x, y] in microns) |
|
macro channel to use when performing automated macro placement ([x, y] in microns) |
|
true/false, enables the RTLMP macro placement |
|
minimum number of instances to use while clustering for macro placement |
|
maximum number of instances to use while clustering for macro placement |
|
minimum number of macros to use while clustering for macro placement |
|
maximum number of macros to use while clustering for macro placement |
|
true/false, when true enables power grid generation |
|
true/false, when true enables IR drop analysis |
|
list of nets to skip power grid analysis on |
|
global placement density (0.0 - 1.0) |
|
global placement cell padding in number of sites |
|
true/false, when true global placement will consider the routability of the design |
|
true/false, when true global placement will consider the timing performance of the design |
|
percent of remaining area density to apply above uniform density (0.00 - 0.99) |
|
true/false, when enabled a global placement is performed without considering the impact of the pin placements |
|
detailed placement cell padding in number of sites |
|
maximum cell movement in detailed placement in microns, 0 will result in the tool default maximum displacement |
|
true/false, disallow single site gaps in detail placement |
|
true/false, when true the detailed placement optimization will be performed |
|
maximum cell movement in detailed placement optimization in microns, 0 will result in the tool default maximum displacement |
|
buffer to use during clock tree synthesis |
|
maximum distance between buffers during clock tree synthesis in microns |
|
clustering distance to use during clock tree synthesis in microns |
|
number of instances in a cluster to use during clock tree synthesis |
|
perform level balancing in clock tree synthesis |
|
make clock tree synthesis aware of obstructions |
|
specifies the margin to apply when performing setup repair in library timing units |
|
specifies the margin to apply when performing setup repair in library timing units |
|
specifies the amount of margin to apply to max slew repairs in percent (0 - 100) |
|
specifies the amount of margin to apply to max capacitance repairs in percent (0 - 100) |
|
true/false, when true enables adding buffers to the input ports |
|
true/false, when true enables adding buffers to the output ports |
|
true/false, skip pin swap optimization |
|
true/false, skip gate cloning optimization |
|
percentage of violating nets to attempt to repair (0 - 100) |
|
true/false, when true perform pin access before global routing |
|
maximum number of iterations to use in global routing when attempting to solve overflow |
|
macro extension distance in number of gcells, this can be useful when the detailed router needs additional space to avoid DRCs |
|
true/false, when true allow global routing to finish with congestion |
|
true/false, when true allow global routing to finish with overflow |
|
minimum layer to use for global routing of signals |
|
maximum layer to use for global routing of signals |
|
minimum layer to use for global routing of clock nets |
|
maximum layer to use for global routing of clock nets |
|
maximum number of repair iterations to use during antenna repairs |
|
adds a margin to the antenna ratios (0 - 100) |
|
true/false, flag to indicate whether to check for antenna violations |
|
true/false, flag to indicate whether to repair antenna violations |
|
true/false, when true turns off via generation in detailed router and only uses the specified tech vias |
|
when set this specifies to the detailed router the specific process node |
|
TODO |
|
TODO |
|
TODO |
|
true/false, when true performs a via ripup step after detailed routing to remove power vias that are causing DRC violations |
|
list of default vias to use for detail routing |
|
list of layers to treat as unidirectional regardless of what the tech lef specifies |
|
true/false, when true enables adding fill, if enabled by the PDK, to the design |
|
list of parasitic extraction corners to use |
3.11.7.3. Files#
Parameters |
Help |
list of files to use for specifying global connections |
|
tap cell insertion script |
|
script to generate a padring using ICeWall in OpenROAD |
|
script constrain pin placement |
|
list of files to use for power grid generation |
|
file used to specify the parasitics for estimation |
3.11.8. rcx_bench#
Helper method for configs specific to extraction tasks.
Setup file: rcx_bench.py
Built using target: asap7_demo
3.11.8.1. Configuration#
Keypath |
Value |
|
^\[WARNING|^Warning |
|
^\[ERROR |
-exit -metrics reports/metrics.json |
|
|
10 |
|
true |
|
true |
|
16 |
|
16 |
|
0.0 |
|
0.0 |
|
10 |
|
typical |
|
0 |
|
site |
|
|
|
|
|
false |
|
true |
|
true |
|
0.60 |
|
2 |
|
true |
|
true |
|
0.00 |
|
true |
|
1 |
|
0 |
|
false |
|
true |
|
0 |
|
BUFx4_ASAP7_75t_R |
|
60 |
|
100 |
|
30 |
|
true |
|
true |
|
0.0 |
|
0.0 |
|
0.0 |
|
0.0 |
|
false |
|
false |
|
true |
|
true |
|
100 |
|
false |
|
100 |
|
0 |
|
false |
|
false |
|
M2 |
|
M7 |
|
M2 |
|
M7 |
|
3 |
|
0 |
|
true |
|
true |
|
false |
|
false |
|
true |
|
typical |
7p5t |
|
|
M7 |
|
100 |
|
|
|
|
|
|
|
|
|
|
1 |
3.11.8.2. Variables#
Parameters |
Help |
list of “tool key level” to enable debugging of OpenROAD |
|
Factor to apply when writing the abstract lef |
|
true/false, fill all layers when writing the abstract lef |
|
true/false, enable generating images of the design at the end of the task |
|
number of X bins to use for heatmap image generation |
|
number of Y bins to use for heatmap image generation |
|
timing derating factor to use for hold corners |
|
timing derating factor to use for setup corners |
|
number of paths to report timing for |
|
corner to use for power analysis |
|
buffer cell to use when auto generating timing constraints |
|
maximum distance between tie high/low cells in microns |
|
Snapping strategy to use when placing macros. Allowed values: none, site, manufacturing_grid |
|
additional arguments to pass along to the pin placer. |
|
macro halo to use when performing automated macro placement ([x, y] in microns) |
|
macro channel to use when performing automated macro placement ([x, y] in microns) |
|
true/false, enables the RTLMP macro placement |
|
minimum number of instances to use while clustering for macro placement |
|
maximum number of instances to use while clustering for macro placement |
|
minimum number of macros to use while clustering for macro placement |
|
maximum number of macros to use while clustering for macro placement |
|
true/false, when true enables power grid generation |
|
true/false, when true enables IR drop analysis |
|
list of nets to skip power grid analysis on |
|
global placement density (0.0 - 1.0) |
|
global placement cell padding in number of sites |
|
true/false, when true global placement will consider the routability of the design |
|
true/false, when true global placement will consider the timing performance of the design |
|
percent of remaining area density to apply above uniform density (0.00 - 0.99) |
|
true/false, when enabled a global placement is performed without considering the impact of the pin placements |
|
detailed placement cell padding in number of sites |
|
maximum cell movement in detailed placement in microns, 0 will result in the tool default maximum displacement |
|
true/false, disallow single site gaps in detail placement |
|
true/false, when true the detailed placement optimization will be performed |
|
maximum cell movement in detailed placement optimization in microns, 0 will result in the tool default maximum displacement |
|
buffer to use during clock tree synthesis |
|
maximum distance between buffers during clock tree synthesis in microns |
|
clustering distance to use during clock tree synthesis in microns |
|
number of instances in a cluster to use during clock tree synthesis |
|
perform level balancing in clock tree synthesis |
|
make clock tree synthesis aware of obstructions |
|
specifies the margin to apply when performing setup repair in library timing units |
|
specifies the margin to apply when performing setup repair in library timing units |
|
specifies the amount of margin to apply to max slew repairs in percent (0 - 100) |
|
specifies the amount of margin to apply to max capacitance repairs in percent (0 - 100) |
|
true/false, when true enables adding buffers to the input ports |
|
true/false, when true enables adding buffers to the output ports |
|
true/false, skip pin swap optimization |
|
true/false, skip gate cloning optimization |
|
percentage of violating nets to attempt to repair (0 - 100) |
|
true/false, when true perform pin access before global routing |
|
maximum number of iterations to use in global routing when attempting to solve overflow |
|
macro extension distance in number of gcells, this can be useful when the detailed router needs additional space to avoid DRCs |
|
true/false, when true allow global routing to finish with congestion |
|
true/false, when true allow global routing to finish with overflow |
|
minimum layer to use for global routing of signals |
|
maximum layer to use for global routing of signals |
|
minimum layer to use for global routing of clock nets |
|
maximum layer to use for global routing of clock nets |
|
maximum number of repair iterations to use during antenna repairs |
|
adds a margin to the antenna ratios (0 - 100) |
|
true/false, flag to indicate whether to check for antenna violations |
|
true/false, flag to indicate whether to repair antenna violations |
|
true/false, when true turns off via generation in detailed router and only uses the specified tech vias |
|
when set this specifies to the detailed router the specific process node |
|
TODO |
|
TODO |
|
TODO |
|
true/false, when true performs a via ripup step after detailed routing to remove power vias that are causing DRC violations |
|
list of default vias to use for detail routing |
|
list of layers to treat as unidirectional regardless of what the tech lef specifies |
|
true/false, when true enables adding fill, if enabled by the PDK, to the design |
|
list of parasitic extraction corners to use |
|
Library type used to select the lef file |
|
Maximum layer to generate extraction bench for |
|
Length of bench wires |
3.11.8.3. Files#
Parameters |
Help |
list of files to use for specifying global connections |
|
tap cell insertion script |
|
script to generate a padring using ICeWall in OpenROAD |
|
script constrain pin placement |
|
list of files to use for power grid generation |
|
file used to specify the parasitics for estimation |
3.11.9. rcx_extract#
Helper method for configs specific to extraction tasks.
Setup file: rcx_extract.py
Built using target: asap7_demo
3.11.9.1. Configuration#
Keypath |
Value |
|
^\[WARNING|^Warning |
|
^\[ERROR |
-exit -metrics reports/metrics.json |
|
|
10 |
|
true |
|
true |
|
16 |
|
16 |
|
0.0 |
|
0.0 |
|
10 |
|
typical |
|
0 |
|
site |
|
|
|
|
|
false |
|
true |
|
true |
|
0.60 |
|
2 |
|
true |
|
true |
|
0.00 |
|
true |
|
1 |
|
0 |
|
false |
|
true |
|
0 |
|
BUFx4_ASAP7_75t_R |
|
60 |
|
100 |
|
30 |
|
true |
|
true |
|
0.0 |
|
0.0 |
|
0.0 |
|
0.0 |
|
false |
|
false |
|
true |
|
true |
|
100 |
|
false |
|
100 |
|
0 |
|
false |
|
false |
|
M2 |
|
M7 |
|
M2 |
|
M7 |
|
3 |
|
0 |
|
true |
|
true |
|
false |
|
false |
|
true |
|
typical |
|
7p5t |
|
|
|
|
|
|
|
|
|
|
|
|
1 |
3.11.9.2. Variables#
Parameters |
Help |
list of “tool key level” to enable debugging of OpenROAD |
|
Factor to apply when writing the abstract lef |
|
true/false, fill all layers when writing the abstract lef |
|
true/false, enable generating images of the design at the end of the task |
|
number of X bins to use for heatmap image generation |
|
number of Y bins to use for heatmap image generation |
|
timing derating factor to use for hold corners |
|
timing derating factor to use for setup corners |
|
number of paths to report timing for |
|
corner to use for power analysis |
|
buffer cell to use when auto generating timing constraints |
|
maximum distance between tie high/low cells in microns |
|
Snapping strategy to use when placing macros. Allowed values: none, site, manufacturing_grid |
|
additional arguments to pass along to the pin placer. |
|
macro halo to use when performing automated macro placement ([x, y] in microns) |
|
macro channel to use when performing automated macro placement ([x, y] in microns) |
|
true/false, enables the RTLMP macro placement |
|
minimum number of instances to use while clustering for macro placement |
|
maximum number of instances to use while clustering for macro placement |
|
minimum number of macros to use while clustering for macro placement |
|
maximum number of macros to use while clustering for macro placement |
|
true/false, when true enables power grid generation |
|
true/false, when true enables IR drop analysis |
|
list of nets to skip power grid analysis on |
|
global placement density (0.0 - 1.0) |
|
global placement cell padding in number of sites |
|
true/false, when true global placement will consider the routability of the design |
|
true/false, when true global placement will consider the timing performance of the design |
|
percent of remaining area density to apply above uniform density (0.00 - 0.99) |
|
true/false, when enabled a global placement is performed without considering the impact of the pin placements |
|
detailed placement cell padding in number of sites |
|
maximum cell movement in detailed placement in microns, 0 will result in the tool default maximum displacement |
|
true/false, disallow single site gaps in detail placement |
|
true/false, when true the detailed placement optimization will be performed |
|
maximum cell movement in detailed placement optimization in microns, 0 will result in the tool default maximum displacement |
|
buffer to use during clock tree synthesis |
|
maximum distance between buffers during clock tree synthesis in microns |
|
clustering distance to use during clock tree synthesis in microns |
|
number of instances in a cluster to use during clock tree synthesis |
|
perform level balancing in clock tree synthesis |
|
make clock tree synthesis aware of obstructions |
|
specifies the margin to apply when performing setup repair in library timing units |
|
specifies the margin to apply when performing setup repair in library timing units |
|
specifies the amount of margin to apply to max slew repairs in percent (0 - 100) |
|
specifies the amount of margin to apply to max capacitance repairs in percent (0 - 100) |
|
true/false, when true enables adding buffers to the input ports |
|
true/false, when true enables adding buffers to the output ports |
|
true/false, skip pin swap optimization |
|
true/false, skip gate cloning optimization |
|
percentage of violating nets to attempt to repair (0 - 100) |
|
true/false, when true perform pin access before global routing |
|
maximum number of iterations to use in global routing when attempting to solve overflow |
|
macro extension distance in number of gcells, this can be useful when the detailed router needs additional space to avoid DRCs |
|
true/false, when true allow global routing to finish with congestion |
|
true/false, when true allow global routing to finish with overflow |
|
minimum layer to use for global routing of signals |
|
maximum layer to use for global routing of signals |
|
minimum layer to use for global routing of clock nets |
|
maximum layer to use for global routing of clock nets |
|
maximum number of repair iterations to use during antenna repairs |
|
adds a margin to the antenna ratios (0 - 100) |
|
true/false, flag to indicate whether to check for antenna violations |
|
true/false, flag to indicate whether to repair antenna violations |
|
true/false, when true turns off via generation in detailed router and only uses the specified tech vias |
|
when set this specifies to the detailed router the specific process node |
|
TODO |
|
TODO |
|
TODO |
|
true/false, when true performs a via ripup step after detailed routing to remove power vias that are causing DRC violations |
|
list of default vias to use for detail routing |
|
list of layers to treat as unidirectional regardless of what the tech lef specifies |
|
true/false, when true enables adding fill, if enabled by the PDK, to the design |
|
list of parasitic extraction corners to use |
|
Library type used to select the lef file |
|
Parasitic corner to generate RCX file for |
3.11.9.3. Files#
Parameters |
Help |
list of files to use for specifying global connections |
|
tap cell insertion script |
|
script to generate a padring using ICeWall in OpenROAD |
|
script constrain pin placement |
|
list of files to use for power grid generation |
|
file used to specify the parasitics for estimation |
3.11.10. route#
Performs filler insertion, global routing, antenna repair, and detailed routing
Setup file: route.py
Built using target: asap7_demo
3.11.10.1. Configuration#
Keypath |
Value |
^\[WARNING|^Warning |
|
^\[ERROR |
|
-exit -metrics reports/metrics.json |
|
|
10 |
|
true |
|
true |
|
16 |
|
16 |
|
0.0 |
|
0.0 |
|
10 |
|
typical |
|
0 |
|
site |
|
|
|
|
|
false |
true |
|
true |
|
|
0.60 |
|
2 |
|
true |
|
true |
|
0.00 |
|
true |
|
1 |
|
0 |
|
false |
true |
|
|
0 |
|
BUFx4_ASAP7_75t_R |
|
60 |
|
100 |
|
30 |
|
true |
|
true |
|
0.0 |
|
0.0 |
|
0.0 |
|
0.0 |
|
false |
|
false |
|
true |
|
true |
|
100 |
|
false |
|
100 |
|
0 |
|
false |
|
false |
|
M2 |
|
M7 |
|
M2 |
|
M7 |
|
3 |
0 |
|
true |
|
true |
|
|
false |
|
false |
|
true |
typical |
|
|
|
|
|
|
|
|
|
|
|
|
|
2 |
3.11.10.2. Variables#
Parameters |
Help |
list of “tool key level” to enable debugging of OpenROAD |
|
Factor to apply when writing the abstract lef |
|
true/false, fill all layers when writing the abstract lef |
|
true/false, enable generating images of the design at the end of the task |
|
number of X bins to use for heatmap image generation |
|
number of Y bins to use for heatmap image generation |
|
timing derating factor to use for hold corners |
|
timing derating factor to use for setup corners |
|
number of paths to report timing for |
|
corner to use for power analysis |
|
buffer cell to use when auto generating timing constraints |
|
maximum distance between tie high/low cells in microns |
|
Snapping strategy to use when placing macros. Allowed values: none, site, manufacturing_grid |
|
additional arguments to pass along to the pin placer. |
|
macro halo to use when performing automated macro placement ([x, y] in microns) |
|
macro channel to use when performing automated macro placement ([x, y] in microns) |
|
true/false, enables the RTLMP macro placement |
|
minimum number of instances to use while clustering for macro placement |
|
maximum number of instances to use while clustering for macro placement |
|
minimum number of macros to use while clustering for macro placement |
|
maximum number of macros to use while clustering for macro placement |
|
true/false, when true enables power grid generation |
|
true/false, when true enables IR drop analysis |
|
list of nets to skip power grid analysis on |
|
global placement density (0.0 - 1.0) |
|
global placement cell padding in number of sites |
|
true/false, when true global placement will consider the routability of the design |
|
true/false, when true global placement will consider the timing performance of the design |
|
percent of remaining area density to apply above uniform density (0.00 - 0.99) |
|
true/false, when enabled a global placement is performed without considering the impact of the pin placements |
|
detailed placement cell padding in number of sites |
|
maximum cell movement in detailed placement in microns, 0 will result in the tool default maximum displacement |
|
true/false, disallow single site gaps in detail placement |
|
true/false, when true the detailed placement optimization will be performed |
|
maximum cell movement in detailed placement optimization in microns, 0 will result in the tool default maximum displacement |
|
buffer to use during clock tree synthesis |
|
maximum distance between buffers during clock tree synthesis in microns |
|
clustering distance to use during clock tree synthesis in microns |
|
number of instances in a cluster to use during clock tree synthesis |
|
perform level balancing in clock tree synthesis |
|
make clock tree synthesis aware of obstructions |
|
specifies the margin to apply when performing setup repair in library timing units |
|
specifies the margin to apply when performing setup repair in library timing units |
|
specifies the amount of margin to apply to max slew repairs in percent (0 - 100) |
|
specifies the amount of margin to apply to max capacitance repairs in percent (0 - 100) |
|
true/false, when true enables adding buffers to the input ports |
|
true/false, when true enables adding buffers to the output ports |
|
true/false, skip pin swap optimization |
|
true/false, skip gate cloning optimization |
|
percentage of violating nets to attempt to repair (0 - 100) |
|
true/false, when true perform pin access before global routing |
|
maximum number of iterations to use in global routing when attempting to solve overflow |
|
macro extension distance in number of gcells, this can be useful when the detailed router needs additional space to avoid DRCs |
|
true/false, when true allow global routing to finish with congestion |
|
true/false, when true allow global routing to finish with overflow |
|
minimum layer to use for global routing of signals |
|
maximum layer to use for global routing of signals |
|
minimum layer to use for global routing of clock nets |
|
maximum layer to use for global routing of clock nets |
|
maximum number of repair iterations to use during antenna repairs |
|
adds a margin to the antenna ratios (0 - 100) |
|
true/false, flag to indicate whether to check for antenna violations |
|
true/false, flag to indicate whether to repair antenna violations |
|
true/false, when true turns off via generation in detailed router and only uses the specified tech vias |
|
when set this specifies to the detailed router the specific process node |
|
TODO |
|
TODO |
|
TODO |
|
true/false, when true performs a via ripup step after detailed routing to remove power vias that are causing DRC violations |
|
list of default vias to use for detail routing |
|
list of layers to treat as unidirectional regardless of what the tech lef specifies |
|
true/false, when true enables adding fill, if enabled by the PDK, to the design |
|
list of parasitic extraction corners to use |
3.11.10.3. Files#
Parameters |
Help |
list of files to use for specifying global connections |
|
tap cell insertion script |
|
script to generate a padring using ICeWall in OpenROAD |
|
script constrain pin placement |
|
list of files to use for power grid generation |
|
file used to specify the parasitics for estimation |
3.11.11. screenshot#
Generate a PNG file from a layout file
Setup file: screenshot.py
Built using target: asap7_demo
3.11.11.1. Configuration#
Keypath |
Value |
|
^\[WARNING|^Warning |
|
^\[ERROR |
-exit -metrics reports/metrics.json -no_init -gui |
|
|
<path> |
|
10 |
|
true |
|
true |
|
16 |
|
16 |
|
0.0 |
|
0.0 |
|
10 |
|
typical |
|
0 |
|
site |
|
|
|
|
|
false |
|
true |
|
true |
|
0.60 |
|
2 |
|
true |
|
true |
|
0.00 |
|
true |
|
1 |
|
0 |
|
false |
|
true |
|
0 |
|
BUFx4_ASAP7_75t_R |
|
60 |
|
100 |
|
30 |
|
true |
|
true |
|
0.0 |
|
0.0 |
|
0.0 |
|
0.0 |
|
false |
|
false |
|
true |
|
true |
|
100 |
|
false |
|
100 |
|
0 |
|
false |
|
false |
|
M2 |
|
M7 |
|
M2 |
|
M7 |
|
3 |
|
0 |
|
true |
|
true |
|
false |
|
false |
|
true |
|
typical |
|
true |
|
1024 |
|
false |
|
|
|
|
|
|
|
|
|
|
2 |
3.11.11.2. Variables#
Parameters |
Help |
Task script variables specified as key value pairs. Variable names and value types must match the name and type of task and reference script consuming the variable. |
|
list of “tool key level” to enable debugging of OpenROAD |
|
Factor to apply when writing the abstract lef |
|
true/false, fill all layers when writing the abstract lef |
|
true/false, enable generating images of the design at the end of the task |
|
number of X bins to use for heatmap image generation |
|
number of Y bins to use for heatmap image generation |
|
timing derating factor to use for hold corners |
|
timing derating factor to use for setup corners |
|
number of paths to report timing for |
|
corner to use for power analysis |
|
buffer cell to use when auto generating timing constraints |
|
maximum distance between tie high/low cells in microns |
|
Snapping strategy to use when placing macros. Allowed values: none, site, manufacturing_grid |
|
additional arguments to pass along to the pin placer. |
|
macro halo to use when performing automated macro placement ([x, y] in microns) |
|
macro channel to use when performing automated macro placement ([x, y] in microns) |
|
true/false, enables the RTLMP macro placement |
|
minimum number of instances to use while clustering for macro placement |
|
maximum number of instances to use while clustering for macro placement |
|
minimum number of macros to use while clustering for macro placement |
|
maximum number of macros to use while clustering for macro placement |
|
true/false, when true enables power grid generation |
|
true/false, when true enables IR drop analysis |
|
list of nets to skip power grid analysis on |
|
global placement density (0.0 - 1.0) |
|
global placement cell padding in number of sites |
|
true/false, when true global placement will consider the routability of the design |
|
true/false, when true global placement will consider the timing performance of the design |
|
percent of remaining area density to apply above uniform density (0.00 - 0.99) |
|
true/false, when enabled a global placement is performed without considering the impact of the pin placements |
|
detailed placement cell padding in number of sites |
|
maximum cell movement in detailed placement in microns, 0 will result in the tool default maximum displacement |
|
true/false, disallow single site gaps in detail placement |
|
true/false, when true the detailed placement optimization will be performed |
|
maximum cell movement in detailed placement optimization in microns, 0 will result in the tool default maximum displacement |
|
buffer to use during clock tree synthesis |
|
maximum distance between buffers during clock tree synthesis in microns |
|
clustering distance to use during clock tree synthesis in microns |
|
number of instances in a cluster to use during clock tree synthesis |
|
perform level balancing in clock tree synthesis |
|
make clock tree synthesis aware of obstructions |
|
specifies the margin to apply when performing setup repair in library timing units |
|
specifies the margin to apply when performing setup repair in library timing units |
|
specifies the amount of margin to apply to max slew repairs in percent (0 - 100) |
|
specifies the amount of margin to apply to max capacitance repairs in percent (0 - 100) |
|
true/false, when true enables adding buffers to the input ports |
|
true/false, when true enables adding buffers to the output ports |
|
true/false, skip pin swap optimization |
|
true/false, skip gate cloning optimization |
|
percentage of violating nets to attempt to repair (0 - 100) |
|
true/false, when true perform pin access before global routing |
|
maximum number of iterations to use in global routing when attempting to solve overflow |
|
macro extension distance in number of gcells, this can be useful when the detailed router needs additional space to avoid DRCs |
|
true/false, when true allow global routing to finish with congestion |
|
true/false, when true allow global routing to finish with overflow |
|
minimum layer to use for global routing of signals |
|
maximum layer to use for global routing of signals |
|
minimum layer to use for global routing of clock nets |
|
maximum layer to use for global routing of clock nets |
|
maximum number of repair iterations to use during antenna repairs |
|
adds a margin to the antenna ratios (0 - 100) |
|
true/false, flag to indicate whether to check for antenna violations |
|
true/false, flag to indicate whether to repair antenna violations |
|
true/false, when true turns off via generation in detailed router and only uses the specified tech vias |
|
when set this specifies to the detailed router the specific process node |
|
TODO |
|
TODO |
|
TODO |
|
true/false, when true performs a via ripup step after detailed routing to remove power vias that are causing DRC violations |
|
list of default vias to use for detail routing |
|
list of layers to treat as unidirectional regardless of what the tech lef specifies |
|
true/false, when true enables adding fill, if enabled by the PDK, to the design |
|
list of parasitic extraction corners to use |
|
Task script variables specified as key value pairs. Variable names and value types must match the name and type of task and reference script consuming the variable. |
|
Task script variables specified as key value pairs. Variable names and value types must match the name and type of task and reference script consuming the variable. |
|
true/false, include the images in reports/ |
3.11.11.3. Files#
Parameters |
Help |
list of files to use for specifying global connections |
|
tap cell insertion script |
|
script to generate a padring using ICeWall in OpenROAD |
|
script constrain pin placement |
|
list of files to use for power grid generation |
|
file used to specify the parasitics for estimation |
3.11.12. show#
Show a design in openroad
Setup file: show.py
Built using target: asap7_demo
3.11.12.1. Configuration#
Keypath |
Value |
^\[WARNING|^Warning |
|
^\[ERROR |
|
-metrics reports/metrics.json -no_init -gui |
|
|
<path> |
|
10 |
|
true |
|
true |
|
16 |
|
16 |
|
0.0 |
|
0.0 |
|
10 |
typical |
|
|
0 |
|
site |
|
|
|
|
false |
|
true |
|
true |
|
|
0.60 |
|
2 |
|
true |
|
true |
|
0.00 |
|
true |
|
1 |
|
0 |
|
false |
true |
|
|
0 |
|
BUFx4_ASAP7_75t_R |
|
60 |
|
100 |
|
30 |
|
true |
|
true |
|
0.0 |
|
0.0 |
|
0.0 |
|
0.0 |
|
false |
|
false |
|
true |
|
true |
|
100 |
|
false |
|
100 |
|
0 |
|
false |
|
false |
|
M2 |
|
M7 |
|
M2 |
|
M7 |
|
3 |
0 |
|
true |
|
true |
|
|
false |
|
false |
true |
|
typical |
|
false |
|
|
|
|
|
|
|
|
|
|
|
2 |
3.11.12.2. Variables#
Parameters |
Help |
Task script variables specified as key value pairs. Variable names and value types must match the name and type of task and reference script consuming the variable. |
|
list of “tool key level” to enable debugging of OpenROAD |
|
Factor to apply when writing the abstract lef |
|
true/false, fill all layers when writing the abstract lef |
|
true/false, enable generating images of the design at the end of the task |
|
number of X bins to use for heatmap image generation |
|
number of Y bins to use for heatmap image generation |
|
timing derating factor to use for hold corners |
|
timing derating factor to use for setup corners |
|
number of paths to report timing for |
|
corner to use for power analysis |
|
buffer cell to use when auto generating timing constraints |
|
maximum distance between tie high/low cells in microns |
|
Snapping strategy to use when placing macros. Allowed values: none, site, manufacturing_grid |
|
additional arguments to pass along to the pin placer. |
|
macro halo to use when performing automated macro placement ([x, y] in microns) |
|
macro channel to use when performing automated macro placement ([x, y] in microns) |
|
true/false, enables the RTLMP macro placement |
|
minimum number of instances to use while clustering for macro placement |
|
maximum number of instances to use while clustering for macro placement |
|
minimum number of macros to use while clustering for macro placement |
|
maximum number of macros to use while clustering for macro placement |
|
true/false, when true enables power grid generation |
|
true/false, when true enables IR drop analysis |
|
list of nets to skip power grid analysis on |
|
global placement density (0.0 - 1.0) |
|
global placement cell padding in number of sites |
|
true/false, when true global placement will consider the routability of the design |
|
true/false, when true global placement will consider the timing performance of the design |
|
percent of remaining area density to apply above uniform density (0.00 - 0.99) |
|
true/false, when enabled a global placement is performed without considering the impact of the pin placements |
|
detailed placement cell padding in number of sites |
|
maximum cell movement in detailed placement in microns, 0 will result in the tool default maximum displacement |
|
true/false, disallow single site gaps in detail placement |
|
true/false, when true the detailed placement optimization will be performed |
|
maximum cell movement in detailed placement optimization in microns, 0 will result in the tool default maximum displacement |
|
buffer to use during clock tree synthesis |
|
maximum distance between buffers during clock tree synthesis in microns |
|
clustering distance to use during clock tree synthesis in microns |
|
number of instances in a cluster to use during clock tree synthesis |
|
perform level balancing in clock tree synthesis |
|
make clock tree synthesis aware of obstructions |
|
specifies the margin to apply when performing setup repair in library timing units |
|
specifies the margin to apply when performing setup repair in library timing units |
|
specifies the amount of margin to apply to max slew repairs in percent (0 - 100) |
|
specifies the amount of margin to apply to max capacitance repairs in percent (0 - 100) |
|
true/false, when true enables adding buffers to the input ports |
|
true/false, when true enables adding buffers to the output ports |
|
true/false, skip pin swap optimization |
|
true/false, skip gate cloning optimization |
|
percentage of violating nets to attempt to repair (0 - 100) |
|
true/false, when true perform pin access before global routing |
|
maximum number of iterations to use in global routing when attempting to solve overflow |
|
macro extension distance in number of gcells, this can be useful when the detailed router needs additional space to avoid DRCs |
|
true/false, when true allow global routing to finish with congestion |
|
true/false, when true allow global routing to finish with overflow |
|
minimum layer to use for global routing of signals |
|
maximum layer to use for global routing of signals |
|
minimum layer to use for global routing of clock nets |
|
maximum layer to use for global routing of clock nets |
|
maximum number of repair iterations to use during antenna repairs |
|
adds a margin to the antenna ratios (0 - 100) |
|
true/false, flag to indicate whether to check for antenna violations |
|
true/false, flag to indicate whether to repair antenna violations |
|
true/false, when true turns off via generation in detailed router and only uses the specified tech vias |
|
when set this specifies to the detailed router the specific process node |
|
TODO |
|
TODO |
|
TODO |
|
true/false, when true performs a via ripup step after detailed routing to remove power vias that are causing DRC violations |
|
list of default vias to use for detail routing |
|
list of layers to treat as unidirectional regardless of what the tech lef specifies |
|
true/false, when true enables adding fill, if enabled by the PDK, to the design |
|
list of parasitic extraction corners to use |
|
Task script variables specified as key value pairs. Variable names and value types must match the name and type of task and reference script consuming the variable. |
3.11.12.3. Files#
Parameters |
Help |
list of files to use for specifying global connections |
|
tap cell insertion script |
|
script to generate a padring using ICeWall in OpenROAD |
|
script constrain pin placement |
|
list of files to use for power grid generation |
|
file used to specify the parasitics for estimation |
3.12. surelog#
Surelog is a SystemVerilog pre-processor, parser, elaborator, and UHDM compiler that provdes IEEE design and testbench C/C++ VPI and a Python AST API.
Documentation: chipsalliance/Surelog
Sources: chipsalliance/Surelog
Installation: chipsalliance/Surelog
Setup file: surelog.py
Keypath |
Value |
surelog |
|
--version |
|
>=1.51 |
3.12.1. parse#
Import verilog files
Setup file: parse.py
3.12.1.1. Configuration#
Keypath |
Value |
^\[WRN: |
|
^\[(ERR|FTL|SNT): |
|
|
|
|
false |
|
false |
false |
|
false |
|
|
|
2 |
3.12.1.2. Variables#
Parameters |
Help |
true/false, when true instructs Surelog to minimize its maximum memory usage. |
|
true/false, when true instructs Surelog to not write to its cache. |
|
true/false, when true instructs Surelog to not log infos. |
|
true/false, when true instructs Surelog to not log notes. |
3.13. sv2v#
sv2v converts SystemVerilog (IEEE 1800-2017) to Verilog (IEEE 1364-2005), with an emphasis on supporting synthesizable language constructs. The primary goal of this project is to create a completely free and open-source tool for converting SystemVerilog to Verilog. While methods for performing this conversion already exist, they generally either rely on commercial tools, or are limited in scope.
Documentation: zachjs/sv2v
Sources: zachjs/sv2v
Installation: zachjs/sv2v
Setup file: sv2v.py
Keypath |
Value |
sv2v |
|
--numeric-version |
|
>=0.0.9 |
3.13.1. convert#
Convert SystemVerilog to verilog
Setup file: convert.py
3.13.1.1. Configuration#
Keypath |
Value |
|
|
|
|
|
|
2 |
3.14. verilator#
Verilator is a free and open-source software tool which converts Verilog (a hardware description language) to a cycle-accurate behavioral model in C++ or SystemC.
All Verilator tasks may consume input either from a single pickled Verilog file
(inputs/<design>.v) generated by a preceding task, or if that file does not
exist, through the following keypaths:
For all tasks, this driver runs Verilator using the -sv switch to enable
parsing a subset of SystemVerilog features. All tasks also support using
['option', 'relax'] to make warnings nonfatal.
Documentation: https://verilator.org/guide/latest
Sources: verilator/verilator
Installation: https://verilator.org/guide/latest/install.html
Setup file: verilator.py
3.14.1. Data sources#
Package |
Specifications |
lambdapdk |
|
Keypath |
Value |
verilator |
|
--version |
|
>=4.034 |
3.14.2. compile#
Compiles Verilog and C/C++ sources into an executable. In addition to the
standard RTL inputs, this task reads C/C++ sources from ['input', 'hll', 'c']. Outputs an executable in outputs/<design>.vexe.
This task supports using the ['option', 'trace'] parameter to enable
Verilator’s --trace flag.
Setup file: compile.py
Built using target: freepdk45_demo
3.14.2.1. Configuration#
Keypath |
Value |
|
^\%Warning |
^\%Error |
|
|
false |
cc |
|
|
vcd |
input,hll,c |
|
2 |
3.14.2.2. Variables#
Parameters |
Help |
true/false, when true assertions are enabled in Verilator. |
|
defines compilation mode for Verilator. Valid options are ‘cc’ for C++, or ‘systemc’ for SystemC. |
|
specifies type of wave file to create when [option, trace] is set. Valid options are ‘vcd’ or ‘fst’. Defaults to ‘vcd’. |
|
flags to provide to the C++ compiler invoked by Verilator |
|
flags to provide to the linker invoked by Verilator |
|
controls datatypes used to represent SystemC inputs/outputs. See –pins-bv in Verilator docs for more info. |
3.14.2.3. Files#
Parameters |
Help |
Verilator configuration file |
3.14.3. lint#
Lints Verilog source. Results of linting can be programmatically queried using errors/warnings metrics.
Setup file: lint.py
Built using target: freepdk45_demo
3.14.3.1. Configuration#
Keypath |
Value |
^\%Warning |
|
^\%Error |
|
|
false |
2 |
3.14.3.2. Variables#
Parameters |
Help |
true/false, when true assertions are enabled in Verilator. |
3.14.3.3. Files#
Parameters |
Help |
Verilator configuration file |
3.15. vivado#
Vivado is an FPGA programming tool suite from Xilinx used to program Xilinx devices.
Documentation: https://www.xilinx.com/products/design-tools/vivado.html
Setup file: vivado.py
3.15.1. Data sources#
Package |
Specifications |
siliconcompiler_data |
|
Keypath |
Value |
vivado |
|
-version |
|
xilinx |
|
>=2021 |
|
tcl |
3.15.2. bitstream#
Generates bitstream of implemented design.
Setup file: bitstream.py
Built using target: fpgaflow_demo
3.15.2.1. Configuration#
Keypath |
Value |
^ERROR: |
|
|
^(CRITICAL )?WARNING: |
|
|
|
|
|
|
|
|
|
|
2 |
3.15.3. place#
Performs placement.
Setup file: place.py
Built using target: fpgaflow_demo
3.15.3.1. Configuration#
Keypath |
Value |
^ERROR: |
|
^(CRITICAL )?WARNING: |
|
|
|
|
|
|
|
|
|
|
|
2 |
3.15.4. route#
Performs routing.
Setup file: route.py
Built using target: fpgaflow_demo
3.15.4.1. Configuration#
Keypath |
Value |
^ERROR: |
|
^(CRITICAL )?WARNING: |
|
|
|
|
|
|
|
|
|
|
|
2 |
3.15.5. syn_fpga#
Performs FPGA synthesis.
Setup file: syn_fpga.py
Built using target: fpgaflow_demo
3.15.5.1. Configuration#
Keypath |
Value |
^ERROR: |
|
^(CRITICAL )?WARNING: |
|
|
|
|
|
|
|
|
|
|
|
2 |
3.16. vpr#
VPR (Versatile Place and Route) is an open source CAD tool designed for the exploration of new FPGA architectures and CAD algorithms, at the packing, placement and routing phases of the CAD flow. VPR takes, as input, a description of an FPGA architecture along with a technology-mapped user circuit. It then performs packing, placement, and routing to map the circuit onto the FPGA. The output of VPR includes the FPGA configuration needed to implement the circuit and statistics about the final mapped design (eg. critical path delay, area, etc).
Documentation: https://docs.verilogtorouting.org/en/latest
Sources: verilog-to-routing/vtr-verilog-to-routing
Installation: verilog-to-routing/vtr-verilog-to-routing
Setup file: vpr.py
3.16.1. Data sources#
Package |
Specifications |
siliconcompiler_data |
|
Keypath |
Value |
vpr |
|
--version |
|
>=8.1.0 |
3.16.2. place#
Perform automated place and route with VPR
Setup file: place.py
Built using target: fpgaflow_demo
3.16.3. route#
Perform automated place and route with VPR
Setup file: route.py
Built using target: fpgaflow_demo
3.16.4. screenshot#
Screenshot placed and/or routed designs
Setup file: screenshot.py
Built using target: fpgaflow_demo
3.16.5. show#
Show placed and/or routed designs in VPR GUI
Setup file: show.py
Built using target: fpgaflow_demo
3.17. xyce#
Xyce is a high performance SPICE-compatible circuit simulator capable capable of solving extremely large circuit problems by supporting large-scale parallel computing platforms. It also supports serial execution on all common desktop platforms, and small-scale parallel runs on Unix-like systems.
Documentation: https://xyce.sandia.gov/documentation-tutorials/
Sources: Xyce/Xyce
Installation: https://xyce.sandia.gov/documentation-tutorials/building-guide/
Status: SC integration WIP
Setup file: xyce.py
Keypath |
Value |
xyce |
|
0.0 |
3.18. yosys#
Yosys is a framework for RTL synthesis that takes synthesizable Verilog-2005 design and converts it to BLIF, EDIF, BTOR, SMT, Verilog netlist etc. The tool supports logical synthesis and tech mapping to ASIC standard cell libraries, FPGA architectures. In addition it has built in formal methods for property and equivalence checking.
Documentation: https://yosyshq.readthedocs.io/projects/yosys/en/latest/
Sources: YosysHQ/yosys
Installation: YosysHQ/yosys
Setup file: yosys.py
3.18.1. Data sources#
Package |
Specifications |
siliconcompiler |
|
lambdapdk |
|
Keypath |
Value |
yosys |
|
--version |
|
>=0.38+92 |
|
tcl |
3.18.2. lec#
Perform logical equivalence checks
Setup file: lec.py
Built using target: asap7_demo
3.18.2.1. Configuration#
Keypath |
Value |
Warning: |
|
^ERROR |
|
-c |
|
true |
|
10 |
|
1000 |
|
true |
|
true |
|
true |
|
slow |
|
|
BUFx2_ASAP7_75t_R |
|
|
|
|
|
|
|
3.18.2.2. Variables#
Parameters |
Help |
true/false, invoke synth with the -flatten option |
|
Number of iterations to attempt to determine the hierarchy to flatten |
|
Instance limit for the number of cells in a module to preserve. |
|
true/false, call autoname to rename wires based on registers |
|
true/false, flag to indicate whether to add buffers or not. |
|
true/false, techmap adders in Yosys |
|
Timing corner to use for synthesis |
|
Buffer that drives the abc techmapping, defaults to first buffer specified |
|
List of modules in input files to prevent flatten from “flattening” |
|
List of modules in input files to exclude from synthesis by replacing them with empty blackboxes” |
|
Capacitive load for the abc techmapping in fF, if not specified it will not be used |
|
Clock period to use for synthesis in ps, if more than one clock is specified, the smallest period is used. |
|
Used to derate the clock period to further constrain the clock, values between 0 and 1 |
|
ABC synthesis strategy. Allowed values are DELAY0-4, AREA0-3, or if the strategy starts with a + it is assumed to be actual commands for ABC. |
3.18.2.3. Files#
Parameters |
Help |
Liberty file to use for flip-flop mapping, if not specified the first in the logiclib is used |
|
File used to pass in constraints to abc |
|
File to use for techmapping in Yosys |
|
File to use for the DFF mapping stage of Yosys |
3.18.3. syn_asic#
Perform ASIC synthesis
Setup file: syn_asic.py
Built using target: asap7_demo
3.18.3.1. Configuration#
Keypath |
Value |
Warning: |
|
^ERROR |
|
-c |
|
true |
|
|
10 |
|
1000 |
true |
|
true |
|
true |
|
|
slow |
|
BUFx2_ASAP7_75t_R |
|
|
|
|
|
|
|
|
|
3.18.3.2. Variables#
Parameters |
Help |
true/false, invoke synth with the -flatten option |
|
Number of iterations to attempt to determine the hierarchy to flatten |
|
Instance limit for the number of cells in a module to preserve. |
|
true/false, call autoname to rename wires based on registers |
|
true/false, flag to indicate whether to add buffers or not. |
|
true/false, techmap adders in Yosys |
|
Timing corner to use for synthesis |
|
Buffer that drives the abc techmapping, defaults to first buffer specified |
|
List of modules in input files to prevent flatten from “flattening” |
|
List of modules in input files to exclude from synthesis by replacing them with empty blackboxes” |
|
Capacitive load for the abc techmapping in fF, if not specified it will not be used |
|
Clock period to use for synthesis in ps, if more than one clock is specified, the smallest period is used. |
|
Used to derate the clock period to further constrain the clock, values between 0 and 1 |
|
ABC synthesis strategy. Allowed values are DELAY0-4, AREA0-3, or if the strategy starts with a + it is assumed to be actual commands for ABC. |
3.18.3.3. Files#
Parameters |
Help |
Liberty file to use for flip-flop mapping, if not specified the first in the logiclib is used |
|
File used to pass in constraints to abc |
|
File to use for techmapping in Yosys |
|
File to use for the DFF mapping stage of Yosys |
3.18.4. syn_fpga#
Perform FPGA synthesis
Setup file: syn_fpga.py
Built using target: fpgaflow_demo
3.18.4.1. Configuration#
Keypath |
Value |
Warning: |
|
^ERROR |
|
-c |
|
|
|
|
|
fpga,ice40up5k-sg48,lutsize |
|
|
|
|