3. Pre-Defined Tools#

The following are examples of pre-built tool drivers that come with SiliconCompiler which you can use for your own builds.

See the pre-built targets for examples on how these are used in conjunction with pdks, flows and libraries.

3.1. bambu#

The primary objective of the PandA project is to develop a usable framework that will enable the research of new ideas in the HW-SW Co-Design field.

The PandA framework includes methodologies supporting the research on high-level synthesis of hardware accelerators, on parallelism extraction for embedded systems, on hardware/software partitioning and mapping, on metrics for performance estimation of embedded software applications and on dynamic reconfigurable devices.

Documentation: https://github.com/ferrandi/PandA-bambu

Sources: https://github.com/ferrandi/PandA-bambu

Installation: https://panda.dei.polimi.it/?page_id=88

Setup file: bambu.py

Keypath	Value
`['tool', 'bambu', 'exe']`	`bambu`
`['tool', 'bambu', 'vswitch']`	`--version`
`['tool', 'bambu', 'version']`	`>=0.9.6`

3.1.1. convert#

Performs high level synthesis to generate a verilog output

Setup file: convert.py

3.1.1.1. Configuration#

3.2. bluespec#

Bluespec is a high-level hardware description language. It has a variety of advanced features including a powerful type system that can prevent errors prior to synthesis time, and its most distinguishing feature, Guarded Atomic Actions, allow you to define hardware components in a modular manner based on their invariants, and let the compiler pick a scheduler.

Documentation: https://github.com/B-Lang-org/bsc#documentation

Sources: https://github.com/B-Lang-org/bsc

Installation: https://github.com/B-Lang-org/bsc#download

Setup file: bluespec.py

Keypath	Value
`['tool', 'bluespec', 'exe']`	`bsc`
`['tool', 'bluespec', 'vswitch']`	`-v`
`['tool', 'bluespec', 'version']`	`>=2021.07`

3.2.1. convert#

Performs high level synthesis to generate a verilog output

Setup file: convert.py

3.2.1.1. Configuration#

3.3. builtin#

Builtin tools for SiliconCompiler

Setup file: builtin.py

3.3.1. join#

Merges outputs from a list of input tasks.

Setup file: join.py

3.3.1.1. Configuration#

3.3.2. maximum#

Selects the task with the maximum metric score from a list of inputs.

Sequence of operation:

Check list of input tasks to see if all metrics meets goals
Check list of input tasks to find global min/max for each metric
Select MAX value if all metrics are met.
Normalize the min value as sel = (val - MIN) / (MAX - MIN)
Return normalized value and task name

Meeting metric goals takes precedence over compute metric scores. Only goals with values set and metrics with weights set are considered in the calculation.

Setup file: maximum.py

3.3.2.1. Configuration#

3.3.3. minimum#

Selects the task with the minimum metric score from a list of inputs.

Sequence of operation:

Check list of input tasks to see if all metrics meets goals
Check list of input tasks to find global min/max for each metric
Select MIN value if all metrics are met.
Normalize the min value as sel = (val - MIN) / (MAX - MIN)
Return normalized value and task name

Meeting metric goals takes precedence over compute metric scores. Only goals with values set and metrics with weights set are considered in the calculation.

Setup file: minimum.py

3.3.3.1. Configuration#

3.3.4. mux#

Selects a task from a list of inputs.

The selector criteria provided is used to create a custom function for selecting the best step/index pair from the inputs. Metrics and weights are passed in and used to select the step/index based on the minimum or maximum score depending on the ‘op’ argument from [‘flowgraph’, flow, step, index, ‘args’] in the form ‘minimum(metric)’ or ‘maximum(metric)’.

The function can be used to bypass the flows weight functions for the purpose of conditional flow execution and verification.

Setup file: mux.py

3.3.4.1. Configuration#

3.3.5. nop#

A no-operation that passes inputs to outputs.

Setup file: nop.py

3.3.5.1. Configuration#

3.3.6. verify#

Tests an assertion on an input task.

The input to this task is verified to ensure that all assertions are True. If any of the assertions fail, False is returned. Assertions are passed in using [‘flowgraph’, flow, step, index, ‘args’] in the form ‘metric==0.0’. The allowed conditional operators are: >, <, >=, <=, ==

Setup file: verify.py

3.3.6.1. Configuration#

3.4. chisel#

Chisel is a hardware design language that facilitates advanced circuit generation and design reuse for both ASIC and FPGA digital logic designs. Chisel adds hardware construction primitives to the Scala programming language, providing designers with the power of a modern programming language to write complex, parameterizable circuit generators that produce synthesizable Verilog.

Documentation: https://www.chisel-lang.org/chisel3/docs/introduction.html

Sources: https://github.com/chipsalliance/chisel

Installation: The Chisel plugin relies on having the Scala Build Tool (sbt) installed. Instructions: https://www.scala-sbt.org/download.html.

Setup file: chisel.py

Keypath	Value
`['tool', 'chisel', 'exe']`	`sbt`
`['tool', 'chisel', 'vswitch']`	`--version`
`['tool', 'chisel', 'version']`	`>=1.5.5`

3.4.1. convert#

Performs high level synthesis to generate a verilog output

Setup file: convert.py

3.4.1.1. Configuration#

3.5. genfasm#

Generate a FSAM file from the output of VPR

Documentation: https://docs.verilogtorouting.org/en/latest/utils/fasm/

Sources: https://github.com/verilog-to-routing/vtr-verilog-to-routing/tree/master/utils/fasm

Setup file: genfasm.py

Keypath	Value
`['tool', 'genfasm', 'exe']`	`genfasm`
`['tool', 'genfasm', 'version']`	`0.0`

3.5.1. bitstream#

Generates a bitstream

Setup file: bitstream.py

3.5.1.1. Configuration#

3.6. ghdl#

GHDL is an open-source analyzer, compiler, simulator and (experimental) synthesizer for VHDL. It allows you to analyse and elaborate sources for generating machine code from your design. Native program execution is the only way for high speed simulation.

Documentation: https://ghdl.readthedocs.io/en/latest

Sources: https://github.com/ghdl/ghdl

Installation: https://github.com/ghdl/ghdl

Setup file: ghdl.py

Keypath	Value
`['tool', 'ghdl', 'exe']`	`ghdl`
`['tool', 'ghdl', 'vswitch']`	`--version`
`['tool', 'ghdl', 'version']`	`>=2.0.0-dev`

3.6.1. convert#

Imports VHDL and converts it to verilog

Setup file: convert.py

3.6.1.1. Configuration#

3.7. icarus#

Icarus is a verilog simulator with full support for Verilog IEEE-1364. Icarus can simulate synthesizable as well as behavioral Verilog.

Documentation: https://steveicarus.github.io/iverilog/

Sources: https://github.com/steveicarus/iverilog

Installation: https://github.com/steveicarus/iverilog

Setup file: icarus.py

Keypath	Value
`['tool', 'icarus', 'exe']`	`iverilog`
`['tool', 'icarus', 'vswitch']`	`-V`
`['tool', 'icarus', 'version']`	`>=10.3`

3.7.1. compile#

Compile the input verilog into a vvp file that can be simulated.

Setup file: compile.py

3.7.1.1. Configuration#

3.8. icepack#

Icepack converts an ASCII bitstream file to a .bin file for the ICE40 FPGA.

Documentation: https://clifford.at/icestorm

Sources: https://github.com/YosysHQ/icestorm

Installation: https://github.com/YosysHQ/icestorm

Setup file: icepack.py

Keypath	Value
`['tool', 'icepack', 'exe']`	`icepack`

3.8.1. bitstream#

Generate a bitstream for the ICE40 FPGA

Setup file: bitstream.py

3.8.1.1. Configuration#

3.9. klayout#

Klayout is a production grade viewer and editor of GDSII and Oasis data with customizable Python and Ruby interfaces.

Documentation: https://www.klayout.de

Sources: https://github.com/KLayout/klayout

Installation: https://www.klayout.de/build.html

Setup file: klayout.py

Keypath	Value
`['tool', 'klayout', 'exe']`	`klayout`
`['tool', 'klayout', 'vswitch']`	`-zz` `-v`
`['tool', 'klayout', 'version']`	`>=0.27.6`
`['tool', 'klayout', 'format']`	`json`

3.9.1. export#

Generate a GDSII file from an input DEF file

Setup file: export.py

Built using target: freepdk45_demo

3.9.1.1. Configuration#

Keypath	Value
`['tool', 'klayout', 'task', 'export', 'regex', 'warnings']`	`(WARNING\|warning)`
`['tool', 'klayout', 'task', 'export', 'regex', 'errors']`	`ERROR`
`['tool', 'klayout', 'task', 'export', 'option']`	`-z` `-nc` `-rx` `-r`
`['tool', 'klayout', 'task', 'export', 'var', 'stream']`	`gds`
`['tool', 'klayout', 'task', 'export', 'var', 'timestamps']`	`true`
`['tool', 'klayout', 'task', 'export', 'var', 'screenshot']`	`true`
`['tool', 'klayout', 'task', 'export', 'var', 'show_horizontal_resolution']`	`4096`
`['tool', 'klayout', 'task', 'export', 'var', 'show_vertical_resolution']`	`4096`
`['tool', 'klayout', 'task', 'export', 'input']`	`<design>.def`
`['tool', 'klayout', 'task', 'export', 'output']`	`<design>.gds` `<design>.lyt`
`['tool', 'klayout', 'task', 'export', 'require']`	`asic,logiclib` `option,stackup` `pdk,freepdk45,layermap,klayout,def,klayout,10M` `library,nangate45,output,10M,gds` `library,nangate45,output,10M,lef`
`['tool', 'klayout', 'task', 'export', 'refdir']`	`tools/klayout`
`['tool', 'klayout', 'task', 'export', 'script']`	`klayout_export.py`

3.9.1.2. Variables#

Parameters	Help
`[..., 'var', 'stream']`	Extension to use for stream generation ((‘gds’, ‘oas’))
`[..., 'var', 'timestamps']`	Export GDSII with timestamps
`[..., 'var', 'screenshot']`	true/false: true will cause KLayout to generate a screenshot of the layout
`[..., 'var', 'hide_layers']`	List of layers to hide
`[..., 'var', 'show_horizontal_resolution']`	Screenshot horizontal resolution in pixels
`[..., 'var', 'show_vertical_resolution']`	Screenshot vertical resolution in pixels

3.9.2. operations#

Perform unit operations on stream files. Currently supports:

rotating (rotate)

renaming (rename)

merging streams (merge)

adding streams together (add)

adding outline to top (outline)

swapping cells (swap)

adding new top cell (add_top)

writing (write)

converting properties into text labels on design (convert_property)

To rotate:

>>> chip.add('tool', 'klayout, 'task', 'operations', 'var', 'operations', 'rotate')

To rename:

>>> chip.add('tool', 'klayout, 'task', 'operations', 'var', 'operations', \
    'rename:tool,klayout,task,operations,var,new_name')
>>> chip.set('tool', 'klayout, 'task', 'operations', 'var', 'new_name', \
    'chip_top')

To merge streams:

>>> chip.add('tool', 'klayout, 'task', 'operations', 'var', 'operations', \
    'merge:tool,klayout,task,operations,file,fill_stream')
>>> chip.set('tool', 'klayout, 'task', 'operations', 'file', 'fill_stream', \
    './fill.gds')

or to get it from the inputs to this task:

>>> chip.add('tool', 'klayout, 'task', 'operations', 'var', 'operations', \
    'merge:fill.gds')

To add streams:

>>> chip.add('tool', 'klayout, 'task', 'operations', 'var', 'operations', \
    'add:tool,klayout,task,operations,file,fill_stream')
>>> chip.set('tool', 'klayout, 'task', 'operations', 'file', 'fill_stream', \
    './fill.gds')

or to get it from the inputs to this task:

>>> chip.add('tool', 'klayout, 'task', 'operations', 'var', 'operations', \
    'add:fill.gds')

To add outline:

>>> chip.add('tool', 'klayout, 'task', 'operations', 'var', 'operations', \
    'outline:tool,klayout,task,operations,var,outline')
>>> chip.set('tool', 'klayout, 'task', 'operations', 'var', 'outline', \
    ['10', '1'])  # layer / purpose pair

To swap layout cells:

>>> chip.add('tool', 'klayout, 'task', 'operations', 'var', 'operations', \
    'swap:tool,klayout,task,operations,var,cell_swap')
>>> chip.set('tool', 'klayout, 'task', 'operations', 'var', 'cell_swap', \
    ['dummy_ANDX2=ANDX2', 'dummy_NANDX2=NANDX2'])

To add new top cell:

>>> chip.add('tool', 'klayout, 'task', 'operations', 'var', 'operations', \
    'add_top:tool,klayout,task,operations,var,new_name')
>>> chip.set('tool', 'klayout, 'task', 'operations', 'var', 'new_name', \
    'chip_top')

To write out a new file:

>>> chip.add('tool', 'klayout, 'task', 'operations', 'var', 'operations', \
    'write:combined.gds')

To convert stream properties to text labels:

>>> chip.add('tool', 'klayout, 'task', 'operations', 'var', 'operations', \
    'convert_property:tool,klayout,task,operations,var,convert_c4_bumps')
>>> chip.set('tool', 'klayout, 'task', 'operations', 'var', 'convert_c4_bumps', \
    ['10', '2', \  # layer / purpose pair for the source of the labels
     '3' \  # stream property number
     '85', '5'])  #  (optional) destination layer / purpose pair, if not provided
                  # the source pair will be used instead.

Setup file: operations.py

Built using target: freepdk45_demo

3.9.2.1. Configuration#

Keypath	Value
`['tool', 'klayout', 'task', 'operations', 'regex', 'warnings']`	`(WARNING\|warning)`
`['tool', 'klayout', 'task', 'operations', 'regex', 'errors']`	`ERROR`
`['tool', 'klayout', 'task', 'operations', 'option']`	`-z` `-nc` `-rx` `-r`
`['tool', 'klayout', 'task', 'operations', 'var', 'stream']`	`gds`
`['tool', 'klayout', 'task', 'operations', 'var', 'timestamps']`	`true`
`['tool', 'klayout', 'task', 'operations', 'output']`	`<design>.gds`
`['tool', 'klayout', 'task', 'operations', 'require']`	`input,layout,gds`
`['tool', 'klayout', 'task', 'operations', 'refdir']`	`tools/klayout`
`['tool', 'klayout', 'task', 'operations', 'script']`	`klayout_operations.py`

3.9.2.2. Variables#

Parameters	Help
`[..., 'var', 'stream']`	Extension to use for stream generation ((‘gds’, ‘oas’))
`[..., 'var', 'timestamps']`	Export GDSII with timestamps

3.9.3. screenshot#

Generate a PNG file from a layout file

Setup file: screenshot.py

Built using target: freepdk45_demo

3.9.3.1. Configuration#

Keypath	Value
`['tool', 'klayout', 'task', 'screenshot', 'regex', 'warnings']`	`(WARNING\|warning)`
`['tool', 'klayout', 'task', 'screenshot', 'regex', 'errors']`	`ERROR`
`['tool', 'klayout', 'task', 'screenshot', 'option']`	`-nc` `-z` `-rm`
`['tool', 'klayout', 'task', 'screenshot', 'var', 'show_filepath']`	`<path>`
`['tool', 'klayout', 'task', 'screenshot', 'var', 'show_exit']`	`true`
`['tool', 'klayout', 'task', 'screenshot', 'var', 'show_horizontal_resolution']`	`4096`
`['tool', 'klayout', 'task', 'screenshot', 'var', 'show_vertical_resolution']`	`4096`
`['tool', 'klayout', 'task', 'screenshot', 'output']`	`<design>.png`
`['tool', 'klayout', 'task', 'screenshot', 'require']`	`tool,klayout,task,screenshot,var,show_filepath`
`['tool', 'klayout', 'task', 'screenshot', 'refdir']`	`tools/klayout`
`['tool', 'klayout', 'task', 'screenshot', 'script']`	`klayout_show.py`

3.9.3.2. Variables#

Parameters	Help
`[..., 'var', 'show_filepath']`	File to open
`[..., 'var', 'show_exit']`	true/false: true will cause kLayout to exit when complete
`[..., 'var', 'hide_layers']`	List of layers to hide
`[..., 'var', 'show_filetype']`	File type to look for in the inputs
`[..., 'var', 'show_horizontal_resolution']`	Horizontal resolution in pixels
`[..., 'var', 'show_vertical_resolution']`	Vertical resolution in pixels

3.9.4. show#

Show a layout in kLayout

Setup file: show.py

Built using target: freepdk45_demo

3.9.4.1. Configuration#

Keypath	Value
`['tool', 'klayout', 'task', 'show', 'regex', 'warnings']`	`(WARNING\|warning)`
`['tool', 'klayout', 'task', 'show', 'regex', 'errors']`	`ERROR`
`['tool', 'klayout', 'task', 'show', 'option']`	`-nc` `-rm`
`['tool', 'klayout', 'task', 'show', 'var', 'show_filepath']`	`<path>`
`['tool', 'klayout', 'task', 'show', 'var', 'show_exit']`	`false`
`['tool', 'klayout', 'task', 'show', 'require']`	`tool,klayout,task,show,var,show_filepath`
`['tool', 'klayout', 'task', 'show', 'refdir']`	`tools/klayout`
`['tool', 'klayout', 'task', 'show', 'script']`	`klayout_show.py`

3.9.4.2. Variables#

Parameters	Help
`[..., 'var', 'show_filepath']`	File to open
`[..., 'var', 'show_exit']`	true/false: true will cause kLayout to exit when complete
`[..., 'var', 'hide_layers']`	List of layers to hide
`[..., 'var', 'show_filetype']`	File type to look for in the inputs

3.10. magic#

Magic is a chip layout viewer, editor, and circuit verifier with built in DRC and LVS engines.

Documentation: http://opencircuitdesign.com/magic/userguide.html

Installation: https://github.com/RTimothyEdwards/magic

Sources: https://github.com/RTimothyEdwards/magic

Setup file: magic.py

Keypath	Value
`['tool', 'magic', 'exe']`	`magic`
`['tool', 'magic', 'vswitch']`	`--version`
`['tool', 'magic', 'version']`	`>=8.3.196`
`['tool', 'magic', 'format']`	`tcl`

3.10.1. drc#

Perform DRC checks

Setup file: drc.py

Built using target: freepdk45_demo

3.10.1.1. Configuration#

Keypath	Value
`['tool', 'magic', 'task', 'drc', 'regex', 'errors']`	`^Error`
`['tool', 'magic', 'task', 'drc', 'regex', 'warnings']`	`warning`
`['tool', 'magic', 'task', 'drc', 'option']`	`-noc` `-dnull`
`['tool', 'magic', 'task', 'drc', 'input']`	`<design>.gds`
`['tool', 'magic', 'task', 'drc', 'refdir']`	`tools/magic`
`['tool', 'magic', 'task', 'drc', 'script']`	`sc_magic.tcl`
`['tool', 'magic', 'task', 'drc', 'threads']`	`2`

3.10.2. extspice#

Extract spice netlists from a GDS file for simulation use

Setup file: extspice.py

Built using target: freepdk45_demo

3.10.2.1. Configuration#

Keypath	Value
`['tool', 'magic', 'task', 'extspice', 'regex', 'errors']`	`^Error`
`['tool', 'magic', 'task', 'extspice', 'regex', 'warnings']`	`warning`
`['tool', 'magic', 'task', 'extspice', 'option']`	`-noc` `-dnull`
`['tool', 'magic', 'task', 'extspice', 'input']`	`<design>.gds`
`['tool', 'magic', 'task', 'extspice', 'output']`	`<design>.spice`
`['tool', 'magic', 'task', 'extspice', 'refdir']`	`tools/magic`
`['tool', 'magic', 'task', 'extspice', 'script']`	`sc_magic.tcl`
`['tool', 'magic', 'task', 'extspice', 'threads']`	`2`

3.11. netgen#

Netgen is a tool for comparing netlists. By comparing a Verilog netlist with one extracted from a circuit layout, it can be used to perform LVS verification.

Documentation: http://www.opencircuitdesign.com/netgen/

Installation: https://github.com/RTimothyEdwards/netgen

Sources: https://github.com/RTimothyEdwards/netgen

Setup file: netgen.py

Keypath	Value
`['tool', 'netgen', 'exe']`	`netgen`
`['tool', 'netgen', 'vswitch']`	`-batch`
`['tool', 'netgen', 'version']`	`>=1.5.192`
`['tool', 'netgen', 'format']`	`tcl`

3.11.1. lvs#

Perform LVS on the supplied netlists

Setup file: lvs.py

3.11.1.1. Configuration#

3.12. nextpnr#

nextpnr is a vendor neutral FPGA place and route tool with support for the ICE40, ECP5, and Nexus devices from Lattice.

Documentation: https://github.com/YosysHQ/nextpnr

Sources: https://github.com/YosysHQ/nextpnr

Installation: https://github.com/YosysHQ/nextpnr

Setup file: nextpnr.py

Keypath	Value
`['tool', 'nextpnr', 'exe']`	`nextpnr-ice40`
`['tool', 'nextpnr', 'vswitch']`	`--version`
`['tool', 'nextpnr', 'version']`	`>=0.2`

3.12.1. apr#

Perform automated place and route on FPGAs

Setup file: apr.py

3.12.1.1. Configuration#

3.13. openfpgaloader#

The OpenFPGALoader is a universal utility for programming FPGAs. Compatible with many boards, cables and FPGA from major manufacturers (Xilinx, Altera/Intel, Lattice, Gowin, Efinix, Anlogic). openFPGALoader works on Linux, Windows and macOS.

Documentation: https://github.com/trabucayre/openFPGALoader

Sources: https://github.com/trabucayre/openFPGALoader

Installation: https://github.com/trabucayre/openFPGALoader

Status: SC integration WIP

Setup file: openfpgaloader.py

Keypath	Value
`['tool', 'openfpgaloader', 'exe']`	`openfpgaloader`
`['tool', 'openfpgaloader', 'vswitch']`	`--Version`
`['tool', 'openfpgaloader', 'version']`	`0.5.0`

3.14. openroad#

OpenROAD is an automated physical design platform for integrated circuit design with a complete set of features needed to translate a synthesized netlist to a tapeout ready GDSII.

Documentation: https://openroad.readthedocs.io/

Sources: https://github.com/The-OpenROAD-Project/OpenROAD

Installation: https://github.com/The-OpenROAD-Project/OpenROAD

Setup file: openroad.py

Keypath	Value
`['tool', 'openroad', 'exe']`	`openroad`
`['tool', 'openroad', 'vswitch']`	`-version`
`['tool', 'openroad', 'version']`	`>=v2.0-7761`
`['tool', 'openroad', 'format']`	`tcl`

3.14.1. cts#

Perform clock tree synthesis and timing repair

Setup file: cts.py

Built using target: asap7_demo

3.14.1.1. Configuration#

Keypath	Value
`['tool', 'openroad', 'task', 'cts', 'regex', 'warnings']`	`^\[WARNING\|^Warning`
`['tool', 'openroad', 'task', 'cts', 'regex', 'errors']`	`^\[ERROR`
`['tool', 'openroad', 'task', 'cts', 'option']`	`-exit -metrics reports/metrics.json`
`['tool', 'openroad', 'task', 'cts', 'var', 'timing_corners']`	`fast` `slow` `typical`
`['tool', 'openroad', 'task', 'cts', 'var', 'pex_corners']`	`typical`
`['tool', 'openroad', 'task', 'cts', 'var', 'power_corner']`	`typical`
`['tool', 'openroad', 'task', 'cts', 'var', 'place_density']`	`0.60`
`['tool', 'openroad', 'task', 'cts', 'var', 'pad_global_place']`	`2`
`['tool', 'openroad', 'task', 'cts', 'var', 'pad_detail_place']`	`1`
`['tool', 'openroad', 'task', 'cts', 'var', 'macro_place_halo']`	`10` `10`
`['tool', 'openroad', 'task', 'cts', 'var', 'macro_place_channel']`	`12` `12`
`['tool', 'openroad', 'task', 'cts', 'var', 'ifp_tie_separation']`	`0`
`['tool', 'openroad', 'task', 'cts', 'var', 'ifp_snap_strategy']`	`site`
`['tool', 'openroad', 'task', 'cts', 'var', 'pdn_enable']`	`true`
`['tool', 'openroad', 'task', 'cts', 'var', 'gpl_routability_driven']`	`true`
`['tool', 'openroad', 'task', 'cts', 'var', 'gpl_timing_driven']`	`true`
`['tool', 'openroad', 'task', 'cts', 'var', 'dpo_enable']`	`true`
`['tool', 'openroad', 'task', 'cts', 'var', 'dpo_max_displacement']`	`0`
`['tool', 'openroad', 'task', 'cts', 'var', 'dpl_max_displacement']`	`0`
`['tool', 'openroad', 'task', 'cts', 'var', 'dpl_disallow_one_site']`	`false`
`['tool', 'openroad', 'task', 'cts', 'var', 'cts_clock_buffer']`	`BUFx2_ASAP7_75t_R`
`['tool', 'openroad', 'task', 'cts', 'var', 'cts_distance_between_buffers']`	`100`
`['tool', 'openroad', 'task', 'cts', 'var', 'cts_cluster_diameter']`	`100`
`['tool', 'openroad', 'task', 'cts', 'var', 'cts_cluster_size']`	`30`
`['tool', 'openroad', 'task', 'cts', 'var', 'cts_balance_levels']`	`true`
`['tool', 'openroad', 'task', 'cts', 'var', 'ant_iterations']`	`3`
`['tool', 'openroad', 'task', 'cts', 'var', 'ant_margin']`	`0`
`['tool', 'openroad', 'task', 'cts', 'var', 'ant_check']`	`true`
`['tool', 'openroad', 'task', 'cts', 'var', 'ant_repair']`	`true`
`['tool', 'openroad', 'task', 'cts', 'var', 'grt_use_pin_access']`	`false`
`['tool', 'openroad', 'task', 'cts', 'var', 'grt_overflow_iter']`	`100`
`['tool', 'openroad', 'task', 'cts', 'var', 'grt_macro_extension']`	`2`
`['tool', 'openroad', 'task', 'cts', 'var', 'grt_allow_congestion']`	`false`
`['tool', 'openroad', 'task', 'cts', 'var', 'grt_allow_overflow']`	`false`
`['tool', 'openroad', 'task', 'cts', 'var', 'grt_signal_min_layer']`	`M2`
`['tool', 'openroad', 'task', 'cts', 'var', 'grt_signal_max_layer']`	`M7`
`['tool', 'openroad', 'task', 'cts', 'var', 'grt_clock_min_layer']`	`M2`
`['tool', 'openroad', 'task', 'cts', 'var', 'grt_clock_max_layer']`	`M7`
`['tool', 'openroad', 'task', 'cts', 'var', 'drt_disable_via_gen']`	`false`
`['tool', 'openroad', 'task', 'cts', 'var', 'drt_process_node']`	`false`
`['tool', 'openroad', 'task', 'cts', 'var', 'drt_via_in_pin_bottom_layer']`	`false`
`['tool', 'openroad', 'task', 'cts', 'var', 'drt_via_in_pin_top_layer']`	`false`
`['tool', 'openroad', 'task', 'cts', 'var', 'drt_repair_pdn_vias']`	`false`
`['tool', 'openroad', 'task', 'cts', 'var', 'drt_via_repair_post_route']`	`false`
`['tool', 'openroad', 'task', 'cts', 'var', 'rsz_setup_slack_margin']`	`0.0`
`['tool', 'openroad', 'task', 'cts', 'var', 'rsz_hold_slack_margin']`	`0.0`
`['tool', 'openroad', 'task', 'cts', 'var', 'rsz_slew_margin']`	`0.0`
`['tool', 'openroad', 'task', 'cts', 'var', 'rsz_cap_margin']`	`0.0`
`['tool', 'openroad', 'task', 'cts', 'var', 'rsz_buffer_inputs']`	`false`
`['tool', 'openroad', 'task', 'cts', 'var', 'rsz_buffer_outputs']`	`false`
`['tool', 'openroad', 'task', 'cts', 'var', 'sta_early_timing_derate']`	`0.0`
`['tool', 'openroad', 'task', 'cts', 'var', 'sta_late_timing_derate']`	`0.0`
`['tool', 'openroad', 'task', 'cts', 'var', 'fin_add_fill']`	`true`
`['tool', 'openroad', 'task', 'cts', 'var', 'psm_enable']`	`true`
`['tool', 'openroad', 'task', 'cts', 'file', 'parasitics']`	`/home/docs/checkouts/readthedocs.org/user_builds/siliconcompiler/checkouts/stable/docs/build/<design>/job0/<step>/<index>/inputs/sc_parasitics.tcl`
`['tool', 'openroad', 'task', 'cts', 'input']`	`<design>.def`
`['tool', 'openroad', 'task', 'cts', 'output']`	`<design>.sdc` `<design>.vg` `<design>.def` `<design>.odb`
`['tool', 'openroad', 'task', 'cts', 'require']`	`asic,logiclib` `option,stackup` `library,asap7sc7p5t_rvt,asic,site,7p5t` `pdk,asap7,aprtech,openroad,10M,7p5t,lef` `library,asap7sc7p5t_rvt,output,typical,nldm` `library,asap7sc7p5t_rvt,output,fast,nldm` `library,asap7sc7p5t_rvt,output,slow,nldm` `library,asap7sc7p5t_rvt,output,10M,lef` `pdk,asap7,var,openroad,rclayer_signal,10M` `pdk,asap7,var,openroad,rclayer_clock,10M` `pdk,asap7,var,openroad,pin_layer_horizontal,10M` `pdk,asap7,var,openroad,pin_layer_vertical,10M` `library,asap7sc7p5t_rvt,option,var,openroad_place_density` `tool,openroad,task,cts,var,place_density` `library,asap7sc7p5t_rvt,option,var,openroad_pad_global_place` `tool,openroad,task,cts,var,pad_global_place` `library,asap7sc7p5t_rvt,option,var,openroad_pad_detail_place` `tool,openroad,task,cts,var,pad_detail_place` `library,asap7sc7p5t_rvt,option,var,openroad_macro_place_halo` `tool,openroad,task,cts,var,macro_place_halo` `library,asap7sc7p5t_rvt,option,var,openroad_macro_place_channel` `tool,openroad,task,cts,var,macro_place_channel` `tool,openroad,task,cts,var,cts_clock_buffer`
`['tool', 'openroad', 'task', 'cts', 'refdir']`	`tools/openroad`
`['tool', 'openroad', 'task', 'cts', 'script']`	`sc_apr.tcl`
`['tool', 'openroad', 'task', 'cts', 'threads']`	`2`

3.14.1.2. Variables#

Parameters	Help
`[..., 'var', 'timing_corners']`	list of timing corners to use
`[..., 'var', 'pex_corners']`	list of parasitic extraction corners to use
`[..., 'var', 'power_corner']`	corner to use for power analysis
`[..., 'var', 'place_density']`	global placement density (0.0 - 1.0)
`[..., 'var', 'pad_global_place']`	global placement cell padding in number of sites
`[..., 'var', 'pad_detail_place']`	detailed placement cell padding in number of sites
`[..., 'var', 'macro_place_halo']`	macro halo to use when performing automated macro placement ([x, y] in microns)
`[..., 'var', 'macro_place_channel']`	macro channel to use when performing automated macro placement ([x, y] in microns)
`[..., 'var', 'detailed_route_default_via']`	list of default vias to use for detail routing
`[..., 'var', 'detailed_route_unidirectional_layer']`	list of layers to treat as unidirectional regardless of what the tech lef specifies
`[..., 'var', 'ifp_tie_separation']`	maximum distance between tie high/low cells in microns
`[..., 'var', 'ifp_snap_strategy']`	Snapping strategy to use when placing macros. Allowed values: none, site, manufacturing_grid
`[..., 'var', 'pdn_enable']`	true/false, when true enables power grid generation
`[..., 'var', 'gpl_routability_driven']`	true/false, when true global placement will consider the routability of the design
`[..., 'var', 'gpl_timing_driven']`	true/false, when true global placement will consider the timing performance of the design
`[..., 'var', 'dpo_enable']`	true/false, when true the detailed placement optimization will be performed
`[..., 'var', 'dpo_max_displacement']`	maximum cell movement in detailed placement optimization in microns, 0 will result in the tool default maximum displacement
`[..., 'var', 'dpl_max_displacement']`	maximum cell movement in detailed placement in microns, 0 will result in the tool default maximum displacement
`[..., 'var', 'dpl_disallow_one_site']`	true/false, disallow single site gaps in detail placement
`[..., 'var', 'cts_clock_buffer']`	buffer to use during clock tree synthesis
`[..., 'var', 'cts_distance_between_buffers']`	maximum distance between buffers during clock tree synthesis in microns
`[..., 'var', 'cts_cluster_diameter']`	clusting distance to use during clock tree synthesis in microns
`[..., 'var', 'cts_cluster_size']`	number of instances in a cluster to use during clock tree synthesis
`[..., 'var', 'cts_balance_levels']`	perform level balancing in clock tree synthesis
`[..., 'var', 'ant_iterations']`	maximum number of repair iterations to use during antenna repairs
`[..., 'var', 'ant_margin']`	adds a margin to the antenna ratios (0 - 100)
`[..., 'var', 'ant_check']`	true/false, flag to indicate whether to check for antenna violations
`[..., 'var', 'ant_repair']`	true/false, flag to indicate whether to repair antenna violations
`[..., 'var', 'grt_use_pin_access']`	true/false, when true perform pin access before global routing
`[..., 'var', 'grt_overflow_iter']`	maximum number of iterations to use in flobal routing when attempting to solve overflow
`[..., 'var', 'grt_macro_extension']`	macro extension distance in number of gcells, this can be useful when the detailed router needs additional space to avoid DRCs
`[..., 'var', 'grt_allow_congestion']`	true/false, when true allow global routing to finish with congestion
`[..., 'var', 'grt_allow_overflow']`	true/false, when true allow global routing to finish with overflow
`[..., 'var', 'grt_signal_min_layer']`	minimum layer to use for global routing of signals
`[..., 'var', 'grt_signal_max_layer']`	maximum layer to use for global routing of signals
`[..., 'var', 'grt_clock_min_layer']`	minimum layer to use for global routing of clock nets
`[..., 'var', 'grt_clock_max_layer']`	maximum layer to use for global routing of clock nets
`[..., 'var', 'drt_disable_via_gen']`	true/false, when true turns off via generation in detailed router and only uses the specified tech vias
`[..., 'var', 'drt_process_node']`	false or value, when set this specifies to the detailed router the specific process node
`[..., 'var', 'drt_via_in_pin_bottom_layer']`	false or value, TODO
`[..., 'var', 'drt_via_in_pin_top_layer']`	false or value, TODO
`[..., 'var', 'drt_repair_pdn_vias']`	false or value, TODO
`[..., 'var', 'drt_via_repair_post_route']`	true/false, when true performs a via ripup step after detailed routing to remove power vias that are causing DRC violations
`[..., 'var', 'rsz_setup_slack_margin']`	specifies the margin to apply when performing setup repair in library timing units
`[..., 'var', 'rsz_hold_slack_margin']`	specifies the margin to apply when performing hold repair in library timing units
`[..., 'var', 'rsz_slew_margin']`	specifies the amount of margin to apply to max slew repairs in percent (0 - 100)
`[..., 'var', 'rsz_cap_margin']`	specifies the amount of margin to apply to max capacitance repairs in percent (0 - 100)
`[..., 'var', 'rsz_buffer_inputs']`	true/false, when true enables adding buffers to the input ports
`[..., 'var', 'rsz_buffer_outputs']`	true/false, when true enables adding buffers to the output ports
`[..., 'var', 'sta_early_timing_derate']`	timing derating factor to use for hold corners
`[..., 'var', 'sta_late_timing_derate']`	timing derating factor to use for setup corners
`[..., 'var', 'fin_add_fill']`	true/false, when true enables adding fill, if enabled by the PDK, to the design
`[..., 'var', 'psm_enable']`	true/false, when true enables IR drop analysis
`[..., 'var', 'debug_level']`	list of “tool key level” to enable debugging of OpenROAD
`[..., 'var', 'sdc_buffer']`	Buffer cell to use when auto generating timing constraints

3.14.1.3. Files#

Parameters	Help
`[..., 'file', 'ifp_tapcell']`	tap cell insertion script
`[..., 'file', 'parasitics']`	file used to specify the parasitics for estimation
`[..., 'file', 'pdn_config']`	list of files to use for power grid generation
`[..., 'file', 'global_connect']`	list of files to use for specifying global connections
`[..., 'file', 'padring']`	script to generate a padring using ICeWall in OpenROAD
`[..., 'file', 'ppl_constraints']`	script constrain pin placement

3.14.2. dfm#

Design for manufacturing step will insert fill if specified

Setup file: dfm.py

Built using target: asap7_demo

3.14.2.1. Configuration#

Keypath	Value
`['tool', 'openroad', 'task', 'dfm', 'regex', 'warnings']`	`^\[WARNING\|^Warning`
`['tool', 'openroad', 'task', 'dfm', 'regex', 'errors']`	`^\[ERROR`
`['tool', 'openroad', 'task', 'dfm', 'option']`	`-exit -metrics reports/metrics.json`
`['tool', 'openroad', 'task', 'dfm', 'var', 'timing_corners']`	`fast` `slow` `typical`
`['tool', 'openroad', 'task', 'dfm', 'var', 'pex_corners']`	`typical`
`['tool', 'openroad', 'task', 'dfm', 'var', 'power_corner']`	`typical`
`['tool', 'openroad', 'task', 'dfm', 'var', 'place_density']`	`0.60`
`['tool', 'openroad', 'task', 'dfm', 'var', 'pad_global_place']`	`2`
`['tool', 'openroad', 'task', 'dfm', 'var', 'pad_detail_place']`	`1`
`['tool', 'openroad', 'task', 'dfm', 'var', 'macro_place_halo']`	`10` `10`
`['tool', 'openroad', 'task', 'dfm', 'var', 'macro_place_channel']`	`12` `12`
`['tool', 'openroad', 'task', 'dfm', 'var', 'ifp_tie_separation']`	`0`
`['tool', 'openroad', 'task', 'dfm', 'var', 'ifp_snap_strategy']`	`site`
`['tool', 'openroad', 'task', 'dfm', 'var', 'pdn_enable']`	`true`
`['tool', 'openroad', 'task', 'dfm', 'var', 'gpl_routability_driven']`	`true`
`['tool', 'openroad', 'task', 'dfm', 'var', 'gpl_timing_driven']`	`true`
`['tool', 'openroad', 'task', 'dfm', 'var', 'dpo_enable']`	`true`
`['tool', 'openroad', 'task', 'dfm', 'var', 'dpo_max_displacement']`	`0`
`['tool', 'openroad', 'task', 'dfm', 'var', 'dpl_max_displacement']`	`0`
`['tool', 'openroad', 'task', 'dfm', 'var', 'dpl_disallow_one_site']`	`false`
`['tool', 'openroad', 'task', 'dfm', 'var', 'cts_clock_buffer']`	`BUFx2_ASAP7_75t_R`
`['tool', 'openroad', 'task', 'dfm', 'var', 'cts_distance_between_buffers']`	`100`
`['tool', 'openroad', 'task', 'dfm', 'var', 'cts_cluster_diameter']`	`100`
`['tool', 'openroad', 'task', 'dfm', 'var', 'cts_cluster_size']`	`30`
`['tool', 'openroad', 'task', 'dfm', 'var', 'cts_balance_levels']`	`true`
`['tool', 'openroad', 'task', 'dfm', 'var', 'ant_iterations']`	`3`
`['tool', 'openroad', 'task', 'dfm', 'var', 'ant_margin']`	`0`
`['tool', 'openroad', 'task', 'dfm', 'var', 'ant_check']`	`true`
`['tool', 'openroad', 'task', 'dfm', 'var', 'ant_repair']`	`true`
`['tool', 'openroad', 'task', 'dfm', 'var', 'grt_use_pin_access']`	`false`
`['tool', 'openroad', 'task', 'dfm', 'var', 'grt_overflow_iter']`	`100`
`['tool', 'openroad', 'task', 'dfm', 'var', 'grt_macro_extension']`	`2`
`['tool', 'openroad', 'task', 'dfm', 'var', 'grt_allow_congestion']`	`false`
`['tool', 'openroad', 'task', 'dfm', 'var', 'grt_allow_overflow']`	`false`
`['tool', 'openroad', 'task', 'dfm', 'var', 'grt_signal_min_layer']`	`M2`
`['tool', 'openroad', 'task', 'dfm', 'var', 'grt_signal_max_layer']`	`M7`
`['tool', 'openroad', 'task', 'dfm', 'var', 'grt_clock_min_layer']`	`M2`
`['tool', 'openroad', 'task', 'dfm', 'var', 'grt_clock_max_layer']`	`M7`
`['tool', 'openroad', 'task', 'dfm', 'var', 'drt_disable_via_gen']`	`false`
`['tool', 'openroad', 'task', 'dfm', 'var', 'drt_process_node']`	`false`
`['tool', 'openroad', 'task', 'dfm', 'var', 'drt_via_in_pin_bottom_layer']`	`false`
`['tool', 'openroad', 'task', 'dfm', 'var', 'drt_via_in_pin_top_layer']`	`false`
`['tool', 'openroad', 'task', 'dfm', 'var', 'drt_repair_pdn_vias']`	`false`
`['tool', 'openroad', 'task', 'dfm', 'var', 'drt_via_repair_post_route']`	`false`
`['tool', 'openroad', 'task', 'dfm', 'var', 'rsz_setup_slack_margin']`	`0.0`
`['tool', 'openroad', 'task', 'dfm', 'var', 'rsz_hold_slack_margin']`	`0.0`
`['tool', 'openroad', 'task', 'dfm', 'var', 'rsz_slew_margin']`	`0.0`
`['tool', 'openroad', 'task', 'dfm', 'var', 'rsz_cap_margin']`	`0.0`
`['tool', 'openroad', 'task', 'dfm', 'var', 'rsz_buffer_inputs']`	`false`
`['tool', 'openroad', 'task', 'dfm', 'var', 'rsz_buffer_outputs']`	`false`
`['tool', 'openroad', 'task', 'dfm', 'var', 'sta_early_timing_derate']`	`0.0`
`['tool', 'openroad', 'task', 'dfm', 'var', 'sta_late_timing_derate']`	`0.0`
`['tool', 'openroad', 'task', 'dfm', 'var', 'fin_add_fill']`	`true`
`['tool', 'openroad', 'task', 'dfm', 'var', 'psm_enable']`	`true`
`['tool', 'openroad', 'task', 'dfm', 'file', 'parasitics']`	`/home/docs/checkouts/readthedocs.org/user_builds/siliconcompiler/checkouts/stable/docs/build/<design>/job0/<step>/<index>/inputs/sc_parasitics.tcl`
`['tool', 'openroad', 'task', 'dfm', 'input']`	`<design>.def`
`['tool', 'openroad', 'task', 'dfm', 'output']`	`<design>.sdc` `<design>.vg` `<design>.def` `<design>.odb`
`['tool', 'openroad', 'task', 'dfm', 'require']`	`asic,logiclib` `option,stackup` `library,asap7sc7p5t_rvt,asic,site,7p5t` `pdk,asap7,aprtech,openroad,10M,7p5t,lef` `library,asap7sc7p5t_rvt,output,typical,nldm` `library,asap7sc7p5t_rvt,output,fast,nldm` `library,asap7sc7p5t_rvt,output,slow,nldm` `library,asap7sc7p5t_rvt,output,10M,lef` `pdk,asap7,var,openroad,rclayer_signal,10M` `pdk,asap7,var,openroad,rclayer_clock,10M` `pdk,asap7,var,openroad,pin_layer_horizontal,10M` `pdk,asap7,var,openroad,pin_layer_vertical,10M` `library,asap7sc7p5t_rvt,option,var,openroad_place_density` `tool,openroad,task,dfm,var,place_density` `library,asap7sc7p5t_rvt,option,var,openroad_pad_global_place` `tool,openroad,task,dfm,var,pad_global_place` `library,asap7sc7p5t_rvt,option,var,openroad_pad_detail_place` `tool,openroad,task,dfm,var,pad_detail_place` `library,asap7sc7p5t_rvt,option,var,openroad_macro_place_halo` `tool,openroad,task,dfm,var,macro_place_halo` `library,asap7sc7p5t_rvt,option,var,openroad_macro_place_channel` `tool,openroad,task,dfm,var,macro_place_channel` `tool,openroad,task,dfm,var,cts_clock_buffer`
`['tool', 'openroad', 'task', 'dfm', 'refdir']`	`tools/openroad`
`['tool', 'openroad', 'task', 'dfm', 'script']`	`sc_apr.tcl`
`['tool', 'openroad', 'task', 'dfm', 'threads']`	`2`

3.14.2.2. Variables#

Parameters	Help
`[..., 'var', 'timing_corners']`	list of timing corners to use
`[..., 'var', 'pex_corners']`	list of parasitic extraction corners to use
`[..., 'var', 'power_corner']`	corner to use for power analysis
`[..., 'var', 'place_density']`	global placement density (0.0 - 1.0)
`[..., 'var', 'pad_global_place']`	global placement cell padding in number of sites
`[..., 'var', 'pad_detail_place']`	detailed placement cell padding in number of sites
`[..., 'var', 'macro_place_halo']`	macro halo to use when performing automated macro placement ([x, y] in microns)
`[..., 'var', 'macro_place_channel']`	macro channel to use when performing automated macro placement ([x, y] in microns)
`[..., 'var', 'detailed_route_default_via']`	list of default vias to use for detail routing
`[..., 'var', 'detailed_route_unidirectional_layer']`	list of layers to treat as unidirectional regardless of what the tech lef specifies
`[..., 'var', 'ifp_tie_separation']`	maximum distance between tie high/low cells in microns
`[..., 'var', 'ifp_snap_strategy']`	Snapping strategy to use when placing macros. Allowed values: none, site, manufacturing_grid
`[..., 'var', 'pdn_enable']`	true/false, when true enables power grid generation
`[..., 'var', 'gpl_routability_driven']`	true/false, when true global placement will consider the routability of the design
`[..., 'var', 'gpl_timing_driven']`	true/false, when true global placement will consider the timing performance of the design
`[..., 'var', 'dpo_enable']`	true/false, when true the detailed placement optimization will be performed
`[..., 'var', 'dpo_max_displacement']`	maximum cell movement in detailed placement optimization in microns, 0 will result in the tool default maximum displacement
`[..., 'var', 'dpl_max_displacement']`	maximum cell movement in detailed placement in microns, 0 will result in the tool default maximum displacement
`[..., 'var', 'dpl_disallow_one_site']`	true/false, disallow single site gaps in detail placement
`[..., 'var', 'cts_clock_buffer']`	buffer to use during clock tree synthesis
`[..., 'var', 'cts_distance_between_buffers']`	maximum distance between buffers during clock tree synthesis in microns
`[..., 'var', 'cts_cluster_diameter']`	clusting distance to use during clock tree synthesis in microns
`[..., 'var', 'cts_cluster_size']`	number of instances in a cluster to use during clock tree synthesis
`[..., 'var', 'cts_balance_levels']`	perform level balancing in clock tree synthesis
`[..., 'var', 'ant_iterations']`	maximum number of repair iterations to use during antenna repairs
`[..., 'var', 'ant_margin']`	adds a margin to the antenna ratios (0 - 100)
`[..., 'var', 'ant_check']`	true/false, flag to indicate whether to check for antenna violations
`[..., 'var', 'ant_repair']`	true/false, flag to indicate whether to repair antenna violations
`[..., 'var', 'grt_use_pin_access']`	true/false, when true perform pin access before global routing
`[..., 'var', 'grt_overflow_iter']`	maximum number of iterations to use in flobal routing when attempting to solve overflow
`[..., 'var', 'grt_macro_extension']`	macro extension distance in number of gcells, this can be useful when the detailed router needs additional space to avoid DRCs
`[..., 'var', 'grt_allow_congestion']`	true/false, when true allow global routing to finish with congestion
`[..., 'var', 'grt_allow_overflow']`	true/false, when true allow global routing to finish with overflow
`[..., 'var', 'grt_signal_min_layer']`	minimum layer to use for global routing of signals
`[..., 'var', 'grt_signal_max_layer']`	maximum layer to use for global routing of signals
`[..., 'var', 'grt_clock_min_layer']`	minimum layer to use for global routing of clock nets
`[..., 'var', 'grt_clock_max_layer']`	maximum layer to use for global routing of clock nets
`[..., 'var', 'drt_disable_via_gen']`	true/false, when true turns off via generation in detailed router and only uses the specified tech vias
`[..., 'var', 'drt_process_node']`	false or value, when set this specifies to the detailed router the specific process node
`[..., 'var', 'drt_via_in_pin_bottom_layer']`	false or value, TODO
`[..., 'var', 'drt_via_in_pin_top_layer']`	false or value, TODO
`[..., 'var', 'drt_repair_pdn_vias']`	false or value, TODO
`[..., 'var', 'drt_via_repair_post_route']`	true/false, when true performs a via ripup step after detailed routing to remove power vias that are causing DRC violations
`[..., 'var', 'rsz_setup_slack_margin']`	specifies the margin to apply when performing setup repair in library timing units
`[..., 'var', 'rsz_hold_slack_margin']`	specifies the margin to apply when performing hold repair in library timing units
`[..., 'var', 'rsz_slew_margin']`	specifies the amount of margin to apply to max slew repairs in percent (0 - 100)
`[..., 'var', 'rsz_cap_margin']`	specifies the amount of margin to apply to max capacitance repairs in percent (0 - 100)
`[..., 'var', 'rsz_buffer_inputs']`	true/false, when true enables adding buffers to the input ports
`[..., 'var', 'rsz_buffer_outputs']`	true/false, when true enables adding buffers to the output ports
`[..., 'var', 'sta_early_timing_derate']`	timing derating factor to use for hold corners
`[..., 'var', 'sta_late_timing_derate']`	timing derating factor to use for setup corners
`[..., 'var', 'fin_add_fill']`	true/false, when true enables adding fill, if enabled by the PDK, to the design
`[..., 'var', 'psm_enable']`	true/false, when true enables IR drop analysis
`[..., 'var', 'debug_level']`	list of “tool key level” to enable debugging of OpenROAD
`[..., 'var', 'sdc_buffer']`	Buffer cell to use when auto generating timing constraints

3.14.2.3. Files#

Parameters	Help
`[..., 'file', 'ifp_tapcell']`	tap cell insertion script
`[..., 'file', 'parasitics']`	file used to specify the parasitics for estimation
`[..., 'file', 'pdn_config']`	list of files to use for power grid generation
`[..., 'file', 'global_connect']`	list of files to use for specifying global connections
`[..., 'file', 'padring']`	script to generate a padring using ICeWall in OpenROAD
`[..., 'file', 'ppl_constraints']`	script constrain pin placement

3.14.3. export#

Generate abstract views (LEF), timing libraries (liberty files), circuit descriptions (CDL), and parasitic annotation files (SPEF)

Setup file: export.py

Built using target: asap7_demo

3.14.3.1. Configuration#

Keypath	Value
`['tool', 'openroad', 'task', 'export', 'regex', 'warnings']`	`^\[WARNING\|^Warning`
`['tool', 'openroad', 'task', 'export', 'regex', 'errors']`	`^\[ERROR`
`['tool', 'openroad', 'task', 'export', 'option']`	`-exit -metrics reports/metrics.json`
`['tool', 'openroad', 'task', 'export', 'var', 'timing_corners']`	`fast` `slow` `typical`
`['tool', 'openroad', 'task', 'export', 'var', 'pex_corners']`	`typical`
`['tool', 'openroad', 'task', 'export', 'var', 'power_corner']`	`typical`
`['tool', 'openroad', 'task', 'export', 'var', 'place_density']`	`0.60`
`['tool', 'openroad', 'task', 'export', 'var', 'pad_global_place']`	`2`
`['tool', 'openroad', 'task', 'export', 'var', 'pad_detail_place']`	`1`
`['tool', 'openroad', 'task', 'export', 'var', 'macro_place_halo']`	`10` `10`
`['tool', 'openroad', 'task', 'export', 'var', 'macro_place_channel']`	`12` `12`
`['tool', 'openroad', 'task', 'export', 'var', 'ifp_tie_separation']`	`0`
`['tool', 'openroad', 'task', 'export', 'var', 'ifp_snap_strategy']`	`site`
`['tool', 'openroad', 'task', 'export', 'var', 'pdn_enable']`	`true`
`['tool', 'openroad', 'task', 'export', 'var', 'gpl_routability_driven']`	`true`
`['tool', 'openroad', 'task', 'export', 'var', 'gpl_timing_driven']`	`true`
`['tool', 'openroad', 'task', 'export', 'var', 'dpo_enable']`	`true`
`['tool', 'openroad', 'task', 'export', 'var', 'dpo_max_displacement']`	`0`
`['tool', 'openroad', 'task', 'export', 'var', 'dpl_max_displacement']`	`0`
`['tool', 'openroad', 'task', 'export', 'var', 'dpl_disallow_one_site']`	`false`
`['tool', 'openroad', 'task', 'export', 'var', 'cts_clock_buffer']`	`BUFx2_ASAP7_75t_R`
`['tool', 'openroad', 'task', 'export', 'var', 'cts_distance_between_buffers']`	`100`
`['tool', 'openroad', 'task', 'export', 'var', 'cts_cluster_diameter']`	`100`
`['tool', 'openroad', 'task', 'export', 'var', 'cts_cluster_size']`	`30`
`['tool', 'openroad', 'task', 'export', 'var', 'cts_balance_levels']`	`true`
`['tool', 'openroad', 'task', 'export', 'var', 'ant_iterations']`	`3`
`['tool', 'openroad', 'task', 'export', 'var', 'ant_margin']`	`0`
`['tool', 'openroad', 'task', 'export', 'var', 'ant_check']`	`true`
`['tool', 'openroad', 'task', 'export', 'var', 'ant_repair']`	`true`
`['tool', 'openroad', 'task', 'export', 'var', 'grt_use_pin_access']`	`false`
`['tool', 'openroad', 'task', 'export', 'var', 'grt_overflow_iter']`	`100`
`['tool', 'openroad', 'task', 'export', 'var', 'grt_macro_extension']`	`2`
`['tool', 'openroad', 'task', 'export', 'var', 'grt_allow_congestion']`	`false`
`['tool', 'openroad', 'task', 'export', 'var', 'grt_allow_overflow']`	`false`
`['tool', 'openroad', 'task', 'export', 'var', 'grt_signal_min_layer']`	`M2`
`['tool', 'openroad', 'task', 'export', 'var', 'grt_signal_max_layer']`	`M7`
`['tool', 'openroad', 'task', 'export', 'var', 'grt_clock_min_layer']`	`M2`
`['tool', 'openroad', 'task', 'export', 'var', 'grt_clock_max_layer']`	`M7`
`['tool', 'openroad', 'task', 'export', 'var', 'drt_disable_via_gen']`	`false`
`['tool', 'openroad', 'task', 'export', 'var', 'drt_process_node']`	`false`
`['tool', 'openroad', 'task', 'export', 'var', 'drt_via_in_pin_bottom_layer']`	`false`
`['tool', 'openroad', 'task', 'export', 'var', 'drt_via_in_pin_top_layer']`	`false`
`['tool', 'openroad', 'task', 'export', 'var', 'drt_repair_pdn_vias']`	`false`
`['tool', 'openroad', 'task', 'export', 'var', 'drt_via_repair_post_route']`	`false`
`['tool', 'openroad', 'task', 'export', 'var', 'rsz_setup_slack_margin']`	`0.0`
`['tool', 'openroad', 'task', 'export', 'var', 'rsz_hold_slack_margin']`	`0.0`
`['tool', 'openroad', 'task', 'export', 'var', 'rsz_slew_margin']`	`0.0`
`['tool', 'openroad', 'task', 'export', 'var', 'rsz_cap_margin']`	`0.0`
`['tool', 'openroad', 'task', 'export', 'var', 'rsz_buffer_inputs']`	`false`
`['tool', 'openroad', 'task', 'export', 'var', 'rsz_buffer_outputs']`	`false`
`['tool', 'openroad', 'task', 'export', 'var', 'sta_early_timing_derate']`	`0.0`
`['tool', 'openroad', 'task', 'export', 'var', 'sta_late_timing_derate']`	`0.0`
`['tool', 'openroad', 'task', 'export', 'var', 'fin_add_fill']`	`true`
`['tool', 'openroad', 'task', 'export', 'var', 'psm_enable']`	`true`
`['tool', 'openroad', 'task', 'export', 'var', 'write_cdl']`	`false`
`['tool', 'openroad', 'task', 'export', 'file', 'parasitics']`	`/home/docs/checkouts/readthedocs.org/user_builds/siliconcompiler/checkouts/stable/docs/build/<design>/job0/<step>/<index>/inputs/sc_parasitics.tcl`
`['tool', 'openroad', 'task', 'export', 'input']`	`<design>.def`
`['tool', 'openroad', 'task', 'export', 'output']`	`<design>.sdc` `<design>.vg` `<design>.def` `<design>.odb` `<design>.lef` `<design>.typical.spef` `<design>.fast.lib` `<design>.slow.lib` `<design>.typical.lib`
`['tool', 'openroad', 'task', 'export', 'require']`	`asic,logiclib` `option,stackup` `library,asap7sc7p5t_rvt,asic,site,7p5t` `pdk,asap7,aprtech,openroad,10M,7p5t,lef` `library,asap7sc7p5t_rvt,output,typical,nldm` `library,asap7sc7p5t_rvt,output,fast,nldm` `library,asap7sc7p5t_rvt,output,slow,nldm` `library,asap7sc7p5t_rvt,output,10M,lef` `pdk,asap7,var,openroad,rclayer_signal,10M` `pdk,asap7,var,openroad,rclayer_clock,10M` `pdk,asap7,var,openroad,pin_layer_horizontal,10M` `pdk,asap7,var,openroad,pin_layer_vertical,10M` `library,asap7sc7p5t_rvt,option,var,openroad_place_density` `tool,openroad,task,export,var,place_density` `library,asap7sc7p5t_rvt,option,var,openroad_pad_global_place` `tool,openroad,task,export,var,pad_global_place` `library,asap7sc7p5t_rvt,option,var,openroad_pad_detail_place` `tool,openroad,task,export,var,pad_detail_place` `library,asap7sc7p5t_rvt,option,var,openroad_macro_place_halo` `tool,openroad,task,export,var,macro_place_halo` `library,asap7sc7p5t_rvt,option,var,openroad_macro_place_channel` `tool,openroad,task,export,var,macro_place_channel` `tool,openroad,task,export,var,cts_clock_buffer` `pdk,asap7,pexmodel,openroad-openrcx,10M,typical`
`['tool', 'openroad', 'task', 'export', 'refdir']`	`tools/openroad`
`['tool', 'openroad', 'task', 'export', 'script']`	`sc_apr.tcl`
`['tool', 'openroad', 'task', 'export', 'threads']`	`1`

3.14.3.2. Variables#

Parameters	Help
`[..., 'var', 'timing_corners']`	list of timing corners to use
`[..., 'var', 'pex_corners']`	list of parasitic extraction corners to use
`[..., 'var', 'power_corner']`	corner to use for power analysis
`[..., 'var', 'place_density']`	global placement density (0.0 - 1.0)
`[..., 'var', 'pad_global_place']`	global placement cell padding in number of sites
`[..., 'var', 'pad_detail_place']`	detailed placement cell padding in number of sites
`[..., 'var', 'macro_place_halo']`	macro halo to use when performing automated macro placement ([x, y] in microns)
`[..., 'var', 'macro_place_channel']`	macro channel to use when performing automated macro placement ([x, y] in microns)
`[..., 'var', 'detailed_route_default_via']`	list of default vias to use for detail routing
`[..., 'var', 'detailed_route_unidirectional_layer']`	list of layers to treat as unidirectional regardless of what the tech lef specifies
`[..., 'var', 'ifp_tie_separation']`	maximum distance between tie high/low cells in microns
`[..., 'var', 'ifp_snap_strategy']`	Snapping strategy to use when placing macros. Allowed values: none, site, manufacturing_grid
`[..., 'var', 'pdn_enable']`	true/false, when true enables power grid generation
`[..., 'var', 'gpl_routability_driven']`	true/false, when true global placement will consider the routability of the design
`[..., 'var', 'gpl_timing_driven']`	true/false, when true global placement will consider the timing performance of the design
`[..., 'var', 'dpo_enable']`	true/false, when true the detailed placement optimization will be performed
`[..., 'var', 'dpo_max_displacement']`	maximum cell movement in detailed placement optimization in microns, 0 will result in the tool default maximum displacement
`[..., 'var', 'dpl_max_displacement']`	maximum cell movement in detailed placement in microns, 0 will result in the tool default maximum displacement
`[..., 'var', 'dpl_disallow_one_site']`	true/false, disallow single site gaps in detail placement
`[..., 'var', 'cts_clock_buffer']`	buffer to use during clock tree synthesis
`[..., 'var', 'cts_distance_between_buffers']`	maximum distance between buffers during clock tree synthesis in microns
`[..., 'var', 'cts_cluster_diameter']`	clusting distance to use during clock tree synthesis in microns
`[..., 'var', 'cts_cluster_size']`	number of instances in a cluster to use during clock tree synthesis
`[..., 'var', 'cts_balance_levels']`	perform level balancing in clock tree synthesis
`[..., 'var', 'ant_iterations']`	maximum number of repair iterations to use during antenna repairs
`[..., 'var', 'ant_margin']`	adds a margin to the antenna ratios (0 - 100)
`[..., 'var', 'ant_check']`	true/false, flag to indicate whether to check for antenna violations
`[..., 'var', 'ant_repair']`	true/false, flag to indicate whether to repair antenna violations
`[..., 'var', 'grt_use_pin_access']`	true/false, when true perform pin access before global routing
`[..., 'var', 'grt_overflow_iter']`	maximum number of iterations to use in flobal routing when attempting to solve overflow
`[..., 'var', 'grt_macro_extension']`	macro extension distance in number of gcells, this can be useful when the detailed router needs additional space to avoid DRCs
`[..., 'var', 'grt_allow_congestion']`	true/false, when true allow global routing to finish with congestion
`[..., 'var', 'grt_allow_overflow']`	true/false, when true allow global routing to finish with overflow
`[..., 'var', 'grt_signal_min_layer']`	minimum layer to use for global routing of signals
`[..., 'var', 'grt_signal_max_layer']`	maximum layer to use for global routing of signals
`[..., 'var', 'grt_clock_min_layer']`	minimum layer to use for global routing of clock nets
`[..., 'var', 'grt_clock_max_layer']`	maximum layer to use for global routing of clock nets
`[..., 'var', 'drt_disable_via_gen']`	true/false, when true turns off via generation in detailed router and only uses the specified tech vias
`[..., 'var', 'drt_process_node']`	false or value, when set this specifies to the detailed router the specific process node
`[..., 'var', 'drt_via_in_pin_bottom_layer']`	false or value, TODO
`[..., 'var', 'drt_via_in_pin_top_layer']`	false or value, TODO
`[..., 'var', 'drt_repair_pdn_vias']`	false or value, TODO
`[..., 'var', 'drt_via_repair_post_route']`	true/false, when true performs a via ripup step after detailed routing to remove power vias that are causing DRC violations
`[..., 'var', 'rsz_setup_slack_margin']`	specifies the margin to apply when performing setup repair in library timing units
`[..., 'var', 'rsz_hold_slack_margin']`	specifies the margin to apply when performing hold repair in library timing units
`[..., 'var', 'rsz_slew_margin']`	specifies the amount of margin to apply to max slew repairs in percent (0 - 100)
`[..., 'var', 'rsz_cap_margin']`	specifies the amount of margin to apply to max capacitance repairs in percent (0 - 100)
`[..., 'var', 'rsz_buffer_inputs']`	true/false, when true enables adding buffers to the input ports
`[..., 'var', 'rsz_buffer_outputs']`	true/false, when true enables adding buffers to the output ports
`[..., 'var', 'sta_early_timing_derate']`	timing derating factor to use for hold corners
`[..., 'var', 'sta_late_timing_derate']`	timing derating factor to use for setup corners
`[..., 'var', 'fin_add_fill']`	true/false, when true enables adding fill, if enabled by the PDK, to the design
`[..., 'var', 'psm_enable']`	true/false, when true enables IR drop analysis
`[..., 'var', 'debug_level']`	list of “tool key level” to enable debugging of OpenROAD
`[..., 'var', 'sdc_buffer']`	Buffer cell to use when auto generating timing constraints
`[..., 'var', 'write_cdl']`	true/false, when true enables writing the CDL file for the design

3.14.3.3. Files#

Parameters	Help
`[..., 'file', 'ifp_tapcell']`	tap cell insertion script
`[..., 'file', 'parasitics']`	file used to specify the parasitics for estimation
`[..., 'file', 'pdn_config']`	list of files to use for power grid generation
`[..., 'file', 'global_connect']`	list of files to use for specifying global connections
`[..., 'file', 'padring']`	script to generate a padring using ICeWall in OpenROAD
`[..., 'file', 'ppl_constraints']`	script constrain pin placement

3.14.4. floorplan#

Perform floorplanning, pin placements, macro placements and power grid generation

Setup file: floorplan.py

Built using target: asap7_demo

3.14.4.1. Configuration#

Keypath	Value
`['tool', 'openroad', 'task', 'floorplan', 'regex', 'warnings']`	`^\[WARNING\|^Warning`
`['tool', 'openroad', 'task', 'floorplan', 'regex', 'errors']`	`^\[ERROR`
`['tool', 'openroad', 'task', 'floorplan', 'option']`	`-exit -metrics reports/metrics.json`
`['tool', 'openroad', 'task', 'floorplan', 'var', 'timing_corners']`	`fast` `slow` `typical`
`['tool', 'openroad', 'task', 'floorplan', 'var', 'pex_corners']`	`typical`
`['tool', 'openroad', 'task', 'floorplan', 'var', 'power_corner']`	`typical`
`['tool', 'openroad', 'task', 'floorplan', 'var', 'place_density']`	`0.60`
`['tool', 'openroad', 'task', 'floorplan', 'var', 'pad_global_place']`	`2`
`['tool', 'openroad', 'task', 'floorplan', 'var', 'pad_detail_place']`	`1`
`['tool', 'openroad', 'task', 'floorplan', 'var', 'macro_place_halo']`	`10` `10`
`['tool', 'openroad', 'task', 'floorplan', 'var', 'macro_place_channel']`	`12` `12`
`['tool', 'openroad', 'task', 'floorplan', 'var', 'ifp_tie_separation']`	`0`
`['tool', 'openroad', 'task', 'floorplan', 'var', 'ifp_snap_strategy']`	`site`
`['tool', 'openroad', 'task', 'floorplan', 'var', 'pdn_enable']`	`true`
`['tool', 'openroad', 'task', 'floorplan', 'var', 'gpl_routability_driven']`	`true`
`['tool', 'openroad', 'task', 'floorplan', 'var', 'gpl_timing_driven']`	`true`
`['tool', 'openroad', 'task', 'floorplan', 'var', 'dpo_enable']`	`true`
`['tool', 'openroad', 'task', 'floorplan', 'var', 'dpo_max_displacement']`	`0`
`['tool', 'openroad', 'task', 'floorplan', 'var', 'dpl_max_displacement']`	`0`
`['tool', 'openroad', 'task', 'floorplan', 'var', 'dpl_disallow_one_site']`	`false`
`['tool', 'openroad', 'task', 'floorplan', 'var', 'cts_clock_buffer']`	`BUFx2_ASAP7_75t_R`
`['tool', 'openroad', 'task', 'floorplan', 'var', 'cts_distance_between_buffers']`	`100`
`['tool', 'openroad', 'task', 'floorplan', 'var', 'cts_cluster_diameter']`	`100`
`['tool', 'openroad', 'task', 'floorplan', 'var', 'cts_cluster_size']`	`30`
`['tool', 'openroad', 'task', 'floorplan', 'var', 'cts_balance_levels']`	`true`
`['tool', 'openroad', 'task', 'floorplan', 'var', 'ant_iterations']`	`3`
`['tool', 'openroad', 'task', 'floorplan', 'var', 'ant_margin']`	`0`
`['tool', 'openroad', 'task', 'floorplan', 'var', 'ant_check']`	`true`
`['tool', 'openroad', 'task', 'floorplan', 'var', 'ant_repair']`	`true`
`['tool', 'openroad', 'task', 'floorplan', 'var', 'grt_use_pin_access']`	`false`
`['tool', 'openroad', 'task', 'floorplan', 'var', 'grt_overflow_iter']`	`100`
`['tool', 'openroad', 'task', 'floorplan', 'var', 'grt_macro_extension']`	`2`
`['tool', 'openroad', 'task', 'floorplan', 'var', 'grt_allow_congestion']`	`false`
`['tool', 'openroad', 'task', 'floorplan', 'var', 'grt_allow_overflow']`	`false`
`['tool', 'openroad', 'task', 'floorplan', 'var', 'grt_signal_min_layer']`	`M2`
`['tool', 'openroad', 'task', 'floorplan', 'var', 'grt_signal_max_layer']`	`M7`
`['tool', 'openroad', 'task', 'floorplan', 'var', 'grt_clock_min_layer']`	`M2`
`['tool', 'openroad', 'task', 'floorplan', 'var', 'grt_clock_max_layer']`	`M7`
`['tool', 'openroad', 'task', 'floorplan', 'var', 'drt_disable_via_gen']`	`false`
`['tool', 'openroad', 'task', 'floorplan', 'var', 'drt_process_node']`	`false`
`['tool', 'openroad', 'task', 'floorplan', 'var', 'drt_via_in_pin_bottom_layer']`	`false`
`['tool', 'openroad', 'task', 'floorplan', 'var', 'drt_via_in_pin_top_layer']`	`false`
`['tool', 'openroad', 'task', 'floorplan', 'var', 'drt_repair_pdn_vias']`	`false`
`['tool', 'openroad', 'task', 'floorplan', 'var', 'drt_via_repair_post_route']`	`false`
`['tool', 'openroad', 'task', 'floorplan', 'var', 'rsz_setup_slack_margin']`	`0.0`
`['tool', 'openroad', 'task', 'floorplan', 'var', 'rsz_hold_slack_margin']`	`0.0`
`['tool', 'openroad', 'task', 'floorplan', 'var', 'rsz_slew_margin']`	`0.0`
`['tool', 'openroad', 'task', 'floorplan', 'var', 'rsz_cap_margin']`	`0.0`
`['tool', 'openroad', 'task', 'floorplan', 'var', 'rsz_buffer_inputs']`	`false`
`['tool', 'openroad', 'task', 'floorplan', 'var', 'rsz_buffer_outputs']`	`false`
`['tool', 'openroad', 'task', 'floorplan', 'var', 'sta_early_timing_derate']`	`0.0`
`['tool', 'openroad', 'task', 'floorplan', 'var', 'sta_late_timing_derate']`	`0.0`
`['tool', 'openroad', 'task', 'floorplan', 'var', 'fin_add_fill']`	`true`
`['tool', 'openroad', 'task', 'floorplan', 'var', 'psm_enable']`	`true`
`['tool', 'openroad', 'task', 'floorplan', 'file', 'parasitics']`	`/home/docs/checkouts/readthedocs.org/user_builds/siliconcompiler/checkouts/stable/docs/build/<design>/job0/<step>/<index>/inputs/sc_parasitics.tcl`
`['tool', 'openroad', 'task', 'floorplan', 'input']`	`<design>.vg`
`['tool', 'openroad', 'task', 'floorplan', 'output']`	`<design>.sdc` `<design>.vg` `<design>.def` `<design>.odb`
`['tool', 'openroad', 'task', 'floorplan', 'require']`	`asic,logiclib` `option,stackup` `library,asap7sc7p5t_rvt,asic,site,7p5t` `pdk,asap7,aprtech,openroad,10M,7p5t,lef` `library,asap7sc7p5t_rvt,output,typical,nldm` `library,asap7sc7p5t_rvt,output,fast,nldm` `library,asap7sc7p5t_rvt,output,slow,nldm` `library,asap7sc7p5t_rvt,output,10M,lef` `pdk,asap7,var,openroad,rclayer_signal,10M` `pdk,asap7,var,openroad,rclayer_clock,10M` `pdk,asap7,var,openroad,pin_layer_horizontal,10M` `pdk,asap7,var,openroad,pin_layer_vertical,10M` `library,asap7sc7p5t_rvt,option,var,openroad_place_density` `tool,openroad,task,floorplan,var,place_density` `library,asap7sc7p5t_rvt,option,var,openroad_pad_global_place` `tool,openroad,task,floorplan,var,pad_global_place` `library,asap7sc7p5t_rvt,option,var,openroad_pad_detail_place` `tool,openroad,task,floorplan,var,pad_detail_place` `library,asap7sc7p5t_rvt,option,var,openroad_macro_place_halo` `tool,openroad,task,floorplan,var,macro_place_halo` `library,asap7sc7p5t_rvt,option,var,openroad_macro_place_channel` `tool,openroad,task,floorplan,var,macro_place_channel` `tool,openroad,task,floorplan,var,cts_clock_buffer`
`['tool', 'openroad', 'task', 'floorplan', 'refdir']`	`tools/openroad`
`['tool', 'openroad', 'task', 'floorplan', 'script']`	`sc_apr.tcl`
`['tool', 'openroad', 'task', 'floorplan', 'threads']`	`2`

3.14.4.2. Variables#

Parameters	Help
`[..., 'var', 'timing_corners']`	list of timing corners to use
`[..., 'var', 'pex_corners']`	list of parasitic extraction corners to use
`[..., 'var', 'power_corner']`	corner to use for power analysis
`[..., 'var', 'place_density']`	global placement density (0.0 - 1.0)
`[..., 'var', 'pad_global_place']`	global placement cell padding in number of sites
`[..., 'var', 'pad_detail_place']`	detailed placement cell padding in number of sites
`[..., 'var', 'macro_place_halo']`	macro halo to use when performing automated macro placement ([x, y] in microns)
`[..., 'var', 'macro_place_channel']`	macro channel to use when performing automated macro placement ([x, y] in microns)
`[..., 'var', 'detailed_route_default_via']`	list of default vias to use for detail routing
`[..., 'var', 'detailed_route_unidirectional_layer']`	list of layers to treat as unidirectional regardless of what the tech lef specifies
`[..., 'var', 'ifp_tie_separation']`	maximum distance between tie high/low cells in microns
`[..., 'var', 'ifp_snap_strategy']`	Snapping strategy to use when placing macros. Allowed values: none, site, manufacturing_grid
`[..., 'var', 'pdn_enable']`	true/false, when true enables power grid generation
`[..., 'var', 'gpl_routability_driven']`	true/false, when true global placement will consider the routability of the design
`[..., 'var', 'gpl_timing_driven']`	true/false, when true global placement will consider the timing performance of the design
`[..., 'var', 'dpo_enable']`	true/false, when true the detailed placement optimization will be performed
`[..., 'var', 'dpo_max_displacement']`	maximum cell movement in detailed placement optimization in microns, 0 will result in the tool default maximum displacement
`[..., 'var', 'dpl_max_displacement']`	maximum cell movement in detailed placement in microns, 0 will result in the tool default maximum displacement
`[..., 'var', 'dpl_disallow_one_site']`	true/false, disallow single site gaps in detail placement
`[..., 'var', 'cts_clock_buffer']`	buffer to use during clock tree synthesis
`[..., 'var', 'cts_distance_between_buffers']`	maximum distance between buffers during clock tree synthesis in microns
`[..., 'var', 'cts_cluster_diameter']`	clusting distance to use during clock tree synthesis in microns
`[..., 'var', 'cts_cluster_size']`	number of instances in a cluster to use during clock tree synthesis
`[..., 'var', 'cts_balance_levels']`	perform level balancing in clock tree synthesis
`[..., 'var', 'ant_iterations']`	maximum number of repair iterations to use during antenna repairs
`[..., 'var', 'ant_margin']`	adds a margin to the antenna ratios (0 - 100)
`[..., 'var', 'ant_check']`	true/false, flag to indicate whether to check for antenna violations
`[..., 'var', 'ant_repair']`	true/false, flag to indicate whether to repair antenna violations
`[..., 'var', 'grt_use_pin_access']`	true/false, when true perform pin access before global routing
`[..., 'var', 'grt_overflow_iter']`	maximum number of iterations to use in flobal routing when attempting to solve overflow
`[..., 'var', 'grt_macro_extension']`	macro extension distance in number of gcells, this can be useful when the detailed router needs additional space to avoid DRCs
`[..., 'var', 'grt_allow_congestion']`	true/false, when true allow global routing to finish with congestion
`[..., 'var', 'grt_allow_overflow']`	true/false, when true allow global routing to finish with overflow
`[..., 'var', 'grt_signal_min_layer']`	minimum layer to use for global routing of signals
`[..., 'var', 'grt_signal_max_layer']`	maximum layer to use for global routing of signals
`[..., 'var', 'grt_clock_min_layer']`	minimum layer to use for global routing of clock nets
`[..., 'var', 'grt_clock_max_layer']`	maximum layer to use for global routing of clock nets
`[..., 'var', 'drt_disable_via_gen']`	true/false, when true turns off via generation in detailed router and only uses the specified tech vias
`[..., 'var', 'drt_process_node']`	false or value, when set this specifies to the detailed router the specific process node
`[..., 'var', 'drt_via_in_pin_bottom_layer']`	false or value, TODO
`[..., 'var', 'drt_via_in_pin_top_layer']`	false or value, TODO
`[..., 'var', 'drt_repair_pdn_vias']`	false or value, TODO
`[..., 'var', 'drt_via_repair_post_route']`	true/false, when true performs a via ripup step after detailed routing to remove power vias that are causing DRC violations
`[..., 'var', 'rsz_setup_slack_margin']`	specifies the margin to apply when performing setup repair in library timing units
`[..., 'var', 'rsz_hold_slack_margin']`	specifies the margin to apply when performing hold repair in library timing units
`[..., 'var', 'rsz_slew_margin']`	specifies the amount of margin to apply to max slew repairs in percent (0 - 100)
`[..., 'var', 'rsz_cap_margin']`	specifies the amount of margin to apply to max capacitance repairs in percent (0 - 100)
`[..., 'var', 'rsz_buffer_inputs']`	true/false, when true enables adding buffers to the input ports
`[..., 'var', 'rsz_buffer_outputs']`	true/false, when true enables adding buffers to the output ports
`[..., 'var', 'sta_early_timing_derate']`	timing derating factor to use for hold corners
`[..., 'var', 'sta_late_timing_derate']`	timing derating factor to use for setup corners
`[..., 'var', 'fin_add_fill']`	true/false, when true enables adding fill, if enabled by the PDK, to the design
`[..., 'var', 'psm_enable']`	true/false, when true enables IR drop analysis
`[..., 'var', 'debug_level']`	list of “tool key level” to enable debugging of OpenROAD
`[..., 'var', 'sdc_buffer']`	Buffer cell to use when auto generating timing constraints

3.14.4.3. Files#

Parameters	Help
`[..., 'file', 'ifp_tapcell']`	tap cell insertion script
`[..., 'file', 'parasitics']`	file used to specify the parasitics for estimation
`[..., 'file', 'pdn_config']`	list of files to use for power grid generation
`[..., 'file', 'global_connect']`	list of files to use for specifying global connections
`[..., 'file', 'padring']`	script to insert the padring
`[..., 'file', 'ppl_constraints']`	script constrain pin placement

3.14.5. physyn#

Not implemented yet

Setup file: physyn.py

Built using target: asap7_demo

3.14.5.1. Configuration#

Keypath	Value
`['tool', 'openroad', 'task', 'physyn', 'regex', 'warnings']`	`^\[WARNING\|^Warning`
`['tool', 'openroad', 'task', 'physyn', 'regex', 'errors']`	`^\[ERROR`
`['tool', 'openroad', 'task', 'physyn', 'option']`	`-exit -metrics reports/metrics.json`
`['tool', 'openroad', 'task', 'physyn', 'var', 'timing_corners']`	`fast` `slow` `typical`
`['tool', 'openroad', 'task', 'physyn', 'var', 'pex_corners']`	`typical`
`['tool', 'openroad', 'task', 'physyn', 'var', 'power_corner']`	`typical`
`['tool', 'openroad', 'task', 'physyn', 'var', 'place_density']`	`0.60`
`['tool', 'openroad', 'task', 'physyn', 'var', 'pad_global_place']`	`2`
`['tool', 'openroad', 'task', 'physyn', 'var', 'pad_detail_place']`	`1`
`['tool', 'openroad', 'task', 'physyn', 'var', 'macro_place_halo']`	`10` `10`
`['tool', 'openroad', 'task', 'physyn', 'var', 'macro_place_channel']`	`12` `12`
`['tool', 'openroad', 'task', 'physyn', 'var', 'ifp_tie_separation']`	`0`
`['tool', 'openroad', 'task', 'physyn', 'var', 'ifp_snap_strategy']`	`site`
`['tool', 'openroad', 'task', 'physyn', 'var', 'pdn_enable']`	`true`
`['tool', 'openroad', 'task', 'physyn', 'var', 'gpl_routability_driven']`	`true`
`['tool', 'openroad', 'task', 'physyn', 'var', 'gpl_timing_driven']`	`true`
`['tool', 'openroad', 'task', 'physyn', 'var', 'dpo_enable']`	`true`
`['tool', 'openroad', 'task', 'physyn', 'var', 'dpo_max_displacement']`	`0`
`['tool', 'openroad', 'task', 'physyn', 'var', 'dpl_max_displacement']`	`0`
`['tool', 'openroad', 'task', 'physyn', 'var', 'dpl_disallow_one_site']`	`false`
`['tool', 'openroad', 'task', 'physyn', 'var', 'cts_clock_buffer']`	`BUFx2_ASAP7_75t_R`
`['tool', 'openroad', 'task', 'physyn', 'var', 'cts_distance_between_buffers']`	`100`
`['tool', 'openroad', 'task', 'physyn', 'var', 'cts_cluster_diameter']`	`100`
`['tool', 'openroad', 'task', 'physyn', 'var', 'cts_cluster_size']`	`30`
`['tool', 'openroad', 'task', 'physyn', 'var', 'cts_balance_levels']`	`true`
`['tool', 'openroad', 'task', 'physyn', 'var', 'ant_iterations']`	`3`
`['tool', 'openroad', 'task', 'physyn', 'var', 'ant_margin']`	`0`
`['tool', 'openroad', 'task', 'physyn', 'var', 'ant_check']`	`true`
`['tool', 'openroad', 'task', 'physyn', 'var', 'ant_repair']`	`true`
`['tool', 'openroad', 'task', 'physyn', 'var', 'grt_use_pin_access']`	`false`
`['tool', 'openroad', 'task', 'physyn', 'var', 'grt_overflow_iter']`	`100`
`['tool', 'openroad', 'task', 'physyn', 'var', 'grt_macro_extension']`	`2`
`['tool', 'openroad', 'task', 'physyn', 'var', 'grt_allow_congestion']`	`false`
`['tool', 'openroad', 'task', 'physyn', 'var', 'grt_allow_overflow']`	`false`
`['tool', 'openroad', 'task', 'physyn', 'var', 'grt_signal_min_layer']`	`M2`
`['tool', 'openroad', 'task', 'physyn', 'var', 'grt_signal_max_layer']`	`M7`
`['tool', 'openroad', 'task', 'physyn', 'var', 'grt_clock_min_layer']`	`M2`
`['tool', 'openroad', 'task', 'physyn', 'var', 'grt_clock_max_layer']`	`M7`
`['tool', 'openroad', 'task', 'physyn', 'var', 'drt_disable_via_gen']`	`false`
`['tool', 'openroad', 'task', 'physyn', 'var', 'drt_process_node']`	`false`
`['tool', 'openroad', 'task', 'physyn', 'var', 'drt_via_in_pin_bottom_layer']`	`false`
`['tool', 'openroad', 'task', 'physyn', 'var', 'drt_via_in_pin_top_layer']`	`false`
`['tool', 'openroad', 'task', 'physyn', 'var', 'drt_repair_pdn_vias']`	`false`
`['tool', 'openroad', 'task', 'physyn', 'var', 'drt_via_repair_post_route']`	`false`
`['tool', 'openroad', 'task', 'physyn', 'var', 'rsz_setup_slack_margin']`	`0.0`
`['tool', 'openroad', 'task', 'physyn', 'var', 'rsz_hold_slack_margin']`	`0.0`
`['tool', 'openroad', 'task', 'physyn', 'var', 'rsz_slew_margin']`	`0.0`
`['tool', 'openroad', 'task', 'physyn', 'var', 'rsz_cap_margin']`	`0.0`
`['tool', 'openroad', 'task', 'physyn', 'var', 'rsz_buffer_inputs']`	`false`
`['tool', 'openroad', 'task', 'physyn', 'var', 'rsz_buffer_outputs']`	`false`
`['tool', 'openroad', 'task', 'physyn', 'var', 'sta_early_timing_derate']`	`0.0`
`['tool', 'openroad', 'task', 'physyn', 'var', 'sta_late_timing_derate']`	`0.0`
`['tool', 'openroad', 'task', 'physyn', 'var', 'fin_add_fill']`	`true`
`['tool', 'openroad', 'task', 'physyn', 'var', 'psm_enable']`	`true`
`['tool', 'openroad', 'task', 'physyn', 'file', 'parasitics']`	`/home/docs/checkouts/readthedocs.org/user_builds/siliconcompiler/checkouts/stable/docs/build/<design>/job0/<step>/<index>/inputs/sc_parasitics.tcl`
`['tool', 'openroad', 'task', 'physyn', 'input']`	`<design>.def`
`['tool', 'openroad', 'task', 'physyn', 'output']`	`<design>.sdc` `<design>.vg` `<design>.def` `<design>.odb`
`['tool', 'openroad', 'task', 'physyn', 'require']`	`asic,logiclib` `option,stackup` `library,asap7sc7p5t_rvt,asic,site,7p5t` `pdk,asap7,aprtech,openroad,10M,7p5t,lef` `library,asap7sc7p5t_rvt,output,typical,nldm` `library,asap7sc7p5t_rvt,output,fast,nldm` `library,asap7sc7p5t_rvt,output,slow,nldm` `library,asap7sc7p5t_rvt,output,10M,lef` `pdk,asap7,var,openroad,rclayer_signal,10M` `pdk,asap7,var,openroad,rclayer_clock,10M` `pdk,asap7,var,openroad,pin_layer_horizontal,10M` `pdk,asap7,var,openroad,pin_layer_vertical,10M` `library,asap7sc7p5t_rvt,option,var,openroad_place_density` `tool,openroad,task,physyn,var,place_density` `library,asap7sc7p5t_rvt,option,var,openroad_pad_global_place` `tool,openroad,task,physyn,var,pad_global_place` `library,asap7sc7p5t_rvt,option,var,openroad_pad_detail_place` `tool,openroad,task,physyn,var,pad_detail_place` `library,asap7sc7p5t_rvt,option,var,openroad_macro_place_halo` `tool,openroad,task,physyn,var,macro_place_halo` `library,asap7sc7p5t_rvt,option,var,openroad_macro_place_channel` `tool,openroad,task,physyn,var,macro_place_channel` `tool,openroad,task,physyn,var,cts_clock_buffer`
`['tool', 'openroad', 'task', 'physyn', 'refdir']`	`tools/openroad`
`['tool', 'openroad', 'task', 'physyn', 'script']`	`sc_apr.tcl`
`['tool', 'openroad', 'task', 'physyn', 'threads']`	`2`

3.14.5.2. Variables#

Parameters	Help
`[..., 'var', 'timing_corners']`	list of timing corners to use
`[..., 'var', 'pex_corners']`	list of parasitic extraction corners to use
`[..., 'var', 'power_corner']`	corner to use for power analysis
`[..., 'var', 'place_density']`	global placement density (0.0 - 1.0)
`[..., 'var', 'pad_global_place']`	global placement cell padding in number of sites
`[..., 'var', 'pad_detail_place']`	detailed placement cell padding in number of sites
`[..., 'var', 'macro_place_halo']`	macro halo to use when performing automated macro placement ([x, y] in microns)
`[..., 'var', 'macro_place_channel']`	macro channel to use when performing automated macro placement ([x, y] in microns)
`[..., 'var', 'detailed_route_default_via']`	list of default vias to use for detail routing
`[..., 'var', 'detailed_route_unidirectional_layer']`	list of layers to treat as unidirectional regardless of what the tech lef specifies
`[..., 'var', 'ifp_tie_separation']`	maximum distance between tie high/low cells in microns
`[..., 'var', 'ifp_snap_strategy']`	Snapping strategy to use when placing macros. Allowed values: none, site, manufacturing_grid
`[..., 'var', 'pdn_enable']`	true/false, when true enables power grid generation
`[..., 'var', 'gpl_routability_driven']`	true/false, when true global placement will consider the routability of the design
`[..., 'var', 'gpl_timing_driven']`	true/false, when true global placement will consider the timing performance of the design
`[..., 'var', 'dpo_enable']`	true/false, when true the detailed placement optimization will be performed
`[..., 'var', 'dpo_max_displacement']`	maximum cell movement in detailed placement optimization in microns, 0 will result in the tool default maximum displacement
`[..., 'var', 'dpl_max_displacement']`	maximum cell movement in detailed placement in microns, 0 will result in the tool default maximum displacement
`[..., 'var', 'dpl_disallow_one_site']`	true/false, disallow single site gaps in detail placement
`[..., 'var', 'cts_clock_buffer']`	buffer to use during clock tree synthesis
`[..., 'var', 'cts_distance_between_buffers']`	maximum distance between buffers during clock tree synthesis in microns
`[..., 'var', 'cts_cluster_diameter']`	clusting distance to use during clock tree synthesis in microns
`[..., 'var', 'cts_cluster_size']`	number of instances in a cluster to use during clock tree synthesis
`[..., 'var', 'cts_balance_levels']`	perform level balancing in clock tree synthesis
`[..., 'var', 'ant_iterations']`	maximum number of repair iterations to use during antenna repairs
`[..., 'var', 'ant_margin']`	adds a margin to the antenna ratios (0 - 100)
`[..., 'var', 'ant_check']`	true/false, flag to indicate whether to check for antenna violations
`[..., 'var', 'ant_repair']`	true/false, flag to indicate whether to repair antenna violations
`[..., 'var', 'grt_use_pin_access']`	true/false, when true perform pin access before global routing
`[..., 'var', 'grt_overflow_iter']`	maximum number of iterations to use in flobal routing when attempting to solve overflow
`[..., 'var', 'grt_macro_extension']`	macro extension distance in number of gcells, this can be useful when the detailed router needs additional space to avoid DRCs
`[..., 'var', 'grt_allow_congestion']`	true/false, when true allow global routing to finish with congestion
`[..., 'var', 'grt_allow_overflow']`	true/false, when true allow global routing to finish with overflow
`[..., 'var', 'grt_signal_min_layer']`	minimum layer to use for global routing of signals
`[..., 'var', 'grt_signal_max_layer']`	maximum layer to use for global routing of signals
`[..., 'var', 'grt_clock_min_layer']`	minimum layer to use for global routing of clock nets
`[..., 'var', 'grt_clock_max_layer']`	maximum layer to use for global routing of clock nets
`[..., 'var', 'drt_disable_via_gen']`	true/false, when true turns off via generation in detailed router and only uses the specified tech vias
`[..., 'var', 'drt_process_node']`	false or value, when set this specifies to the detailed router the specific process node
`[..., 'var', 'drt_via_in_pin_bottom_layer']`	false or value, TODO
`[..., 'var', 'drt_via_in_pin_top_layer']`	false or value, TODO
`[..., 'var', 'drt_repair_pdn_vias']`	false or value, TODO
`[..., 'var', 'drt_via_repair_post_route']`	true/false, when true performs a via ripup step after detailed routing to remove power vias that are causing DRC violations
`[..., 'var', 'rsz_setup_slack_margin']`	specifies the margin to apply when performing setup repair in library timing units
`[..., 'var', 'rsz_hold_slack_margin']`	specifies the margin to apply when performing hold repair in library timing units
`[..., 'var', 'rsz_slew_margin']`	specifies the amount of margin to apply to max slew repairs in percent (0 - 100)
`[..., 'var', 'rsz_cap_margin']`	specifies the amount of margin to apply to max capacitance repairs in percent (0 - 100)
`[..., 'var', 'rsz_buffer_inputs']`	true/false, when true enables adding buffers to the input ports
`[..., 'var', 'rsz_buffer_outputs']`	true/false, when true enables adding buffers to the output ports
`[..., 'var', 'sta_early_timing_derate']`	timing derating factor to use for hold corners
`[..., 'var', 'sta_late_timing_derate']`	timing derating factor to use for setup corners
`[..., 'var', 'fin_add_fill']`	true/false, when true enables adding fill, if enabled by the PDK, to the design
`[..., 'var', 'psm_enable']`	true/false, when true enables IR drop analysis
`[..., 'var', 'debug_level']`	list of “tool key level” to enable debugging of OpenROAD
`[..., 'var', 'sdc_buffer']`	Buffer cell to use when auto generating timing constraints

3.14.5.3. Files#

Parameters	Help
`[..., 'file', 'ifp_tapcell']`	tap cell insertion script
`[..., 'file', 'parasitics']`	file used to specify the parasitics for estimation
`[..., 'file', 'pdn_config']`	list of files to use for power grid generation
`[..., 'file', 'global_connect']`	list of files to use for specifying global connections
`[..., 'file', 'padring']`	script to generate a padring using ICeWall in OpenROAD
`[..., 'file', 'ppl_constraints']`	script constrain pin placement

3.14.6. place#

Perform global and detail placements along with design violation repairs

Setup file: place.py

Built using target: asap7_demo

3.14.6.1. Configuration#

Keypath	Value
`['tool', 'openroad', 'task', 'place', 'regex', 'warnings']`	`^\[WARNING\|^Warning`
`['tool', 'openroad', 'task', 'place', 'regex', 'errors']`	`^\[ERROR`
`['tool', 'openroad', 'task', 'place', 'option']`	`-exit -metrics reports/metrics.json`
`['tool', 'openroad', 'task', 'place', 'var', 'timing_corners']`	`fast` `slow` `typical`
`['tool', 'openroad', 'task', 'place', 'var', 'pex_corners']`	`typical`
`['tool', 'openroad', 'task', 'place', 'var', 'power_corner']`	`typical`
`['tool', 'openroad', 'task', 'place', 'var', 'place_density']`	`0.60`
`['tool', 'openroad', 'task', 'place', 'var', 'pad_global_place']`	`2`
`['tool', 'openroad', 'task', 'place', 'var', 'pad_detail_place']`	`1`
`['tool', 'openroad', 'task', 'place', 'var', 'macro_place_halo']`	`10` `10`
`['tool', 'openroad', 'task', 'place', 'var', 'macro_place_channel']`	`12` `12`
`['tool', 'openroad', 'task', 'place', 'var', 'ifp_tie_separation']`	`0`
`['tool', 'openroad', 'task', 'place', 'var', 'ifp_snap_strategy']`	`site`
`['tool', 'openroad', 'task', 'place', 'var', 'pdn_enable']`	`true`
`['tool', 'openroad', 'task', 'place', 'var', 'gpl_routability_driven']`	`true`
`['tool', 'openroad', 'task', 'place', 'var', 'gpl_timing_driven']`	`true`
`['tool', 'openroad', 'task', 'place', 'var', 'dpo_enable']`	`true`
`['tool', 'openroad', 'task', 'place', 'var', 'dpo_max_displacement']`	`0`
`['tool', 'openroad', 'task', 'place', 'var', 'dpl_max_displacement']`	`0`
`['tool', 'openroad', 'task', 'place', 'var', 'dpl_disallow_one_site']`	`false`
`['tool', 'openroad', 'task', 'place', 'var', 'cts_clock_buffer']`	`BUFx2_ASAP7_75t_R`
`['tool', 'openroad', 'task', 'place', 'var', 'cts_distance_between_buffers']`	`100`
`['tool', 'openroad', 'task', 'place', 'var', 'cts_cluster_diameter']`	`100`
`['tool', 'openroad', 'task', 'place', 'var', 'cts_cluster_size']`	`30`
`['tool', 'openroad', 'task', 'place', 'var', 'cts_balance_levels']`	`true`
`['tool', 'openroad', 'task', 'place', 'var', 'ant_iterations']`	`3`
`['tool', 'openroad', 'task', 'place', 'var', 'ant_margin']`	`0`
`['tool', 'openroad', 'task', 'place', 'var', 'ant_check']`	`true`
`['tool', 'openroad', 'task', 'place', 'var', 'ant_repair']`	`true`
`['tool', 'openroad', 'task', 'place', 'var', 'grt_use_pin_access']`	`false`
`['tool', 'openroad', 'task', 'place', 'var', 'grt_overflow_iter']`	`100`
`['tool', 'openroad', 'task', 'place', 'var', 'grt_macro_extension']`	`2`
`['tool', 'openroad', 'task', 'place', 'var', 'grt_allow_congestion']`	`false`
`['tool', 'openroad', 'task', 'place', 'var', 'grt_allow_overflow']`	`false`
`['tool', 'openroad', 'task', 'place', 'var', 'grt_signal_min_layer']`	`M2`
`['tool', 'openroad', 'task', 'place', 'var', 'grt_signal_max_layer']`	`M7`
`['tool', 'openroad', 'task', 'place', 'var', 'grt_clock_min_layer']`	`M2`
`['tool', 'openroad', 'task', 'place', 'var', 'grt_clock_max_layer']`	`M7`
`['tool', 'openroad', 'task', 'place', 'var', 'drt_disable_via_gen']`	`false`
`['tool', 'openroad', 'task', 'place', 'var', 'drt_process_node']`	`false`
`['tool', 'openroad', 'task', 'place', 'var', 'drt_via_in_pin_bottom_layer']`	`false`
`['tool', 'openroad', 'task', 'place', 'var', 'drt_via_in_pin_top_layer']`	`false`
`['tool', 'openroad', 'task', 'place', 'var', 'drt_repair_pdn_vias']`	`false`
`['tool', 'openroad', 'task', 'place', 'var', 'drt_via_repair_post_route']`	`false`
`['tool', 'openroad', 'task', 'place', 'var', 'rsz_setup_slack_margin']`	`0.0`
`['tool', 'openroad', 'task', 'place', 'var', 'rsz_hold_slack_margin']`	`0.0`
`['tool', 'openroad', 'task', 'place', 'var', 'rsz_slew_margin']`	`0.0`
`['tool', 'openroad', 'task', 'place', 'var', 'rsz_cap_margin']`	`0.0`
`['tool', 'openroad', 'task', 'place', 'var', 'rsz_buffer_inputs']`	`false`
`['tool', 'openroad', 'task', 'place', 'var', 'rsz_buffer_outputs']`	`false`
`['tool', 'openroad', 'task', 'place', 'var', 'sta_early_timing_derate']`	`0.0`
`['tool', 'openroad', 'task', 'place', 'var', 'sta_late_timing_derate']`	`0.0`
`['tool', 'openroad', 'task', 'place', 'var', 'fin_add_fill']`	`true`
`['tool', 'openroad', 'task', 'place', 'var', 'psm_enable']`	`true`
`['tool', 'openroad', 'task', 'place', 'file', 'parasitics']`	`/home/docs/checkouts/readthedocs.org/user_builds/siliconcompiler/checkouts/stable/docs/build/<design>/job0/<step>/<index>/inputs/sc_parasitics.tcl`
`['tool', 'openroad', 'task', 'place', 'input']`	`<design>.def`
`['tool', 'openroad', 'task', 'place', 'output']`	`<design>.sdc` `<design>.vg` `<design>.def` `<design>.odb`
`['tool', 'openroad', 'task', 'place', 'require']`	`asic,logiclib` `option,stackup` `library,asap7sc7p5t_rvt,asic,site,7p5t` `pdk,asap7,aprtech,openroad,10M,7p5t,lef` `library,asap7sc7p5t_rvt,output,typical,nldm` `library,asap7sc7p5t_rvt,output,fast,nldm` `library,asap7sc7p5t_rvt,output,slow,nldm` `library,asap7sc7p5t_rvt,output,10M,lef` `pdk,asap7,var,openroad,rclayer_signal,10M` `pdk,asap7,var,openroad,rclayer_clock,10M` `pdk,asap7,var,openroad,pin_layer_horizontal,10M` `pdk,asap7,var,openroad,pin_layer_vertical,10M` `library,asap7sc7p5t_rvt,option,var,openroad_place_density` `tool,openroad,task,place,var,place_density` `library,asap7sc7p5t_rvt,option,var,openroad_pad_global_place` `tool,openroad,task,place,var,pad_global_place` `library,asap7sc7p5t_rvt,option,var,openroad_pad_detail_place` `tool,openroad,task,place,var,pad_detail_place` `library,asap7sc7p5t_rvt,option,var,openroad_macro_place_halo` `tool,openroad,task,place,var,macro_place_halo` `library,asap7sc7p5t_rvt,option,var,openroad_macro_place_channel` `tool,openroad,task,place,var,macro_place_channel` `tool,openroad,task,place,var,cts_clock_buffer`
`['tool', 'openroad', 'task', 'place', 'refdir']`	`tools/openroad`
`['tool', 'openroad', 'task', 'place', 'script']`	`sc_apr.tcl`
`['tool', 'openroad', 'task', 'place', 'threads']`	`2`

3.14.6.2. Variables#

Parameters	Help
`[..., 'var', 'timing_corners']`	list of timing corners to use
`[..., 'var', 'pex_corners']`	list of parasitic extraction corners to use
`[..., 'var', 'power_corner']`	corner to use for power analysis
`[..., 'var', 'place_density']`	global placement density (0.0 - 1.0)
`[..., 'var', 'pad_global_place']`	global placement cell padding in number of sites
`[..., 'var', 'pad_detail_place']`	detailed placement cell padding in number of sites
`[..., 'var', 'macro_place_halo']`	macro halo to use when performing automated macro placement ([x, y] in microns)
`[..., 'var', 'macro_place_channel']`	macro channel to use when performing automated macro placement ([x, y] in microns)
`[..., 'var', 'detailed_route_default_via']`	list of default vias to use for detail routing
`[..., 'var', 'detailed_route_unidirectional_layer']`	list of layers to treat as unidirectional regardless of what the tech lef specifies
`[..., 'var', 'ifp_tie_separation']`	maximum distance between tie high/low cells in microns
`[..., 'var', 'ifp_snap_strategy']`	Snapping strategy to use when placing macros. Allowed values: none, site, manufacturing_grid
`[..., 'var', 'pdn_enable']`	true/false, when true enables power grid generation
`[..., 'var', 'gpl_routability_driven']`	true/false, when true global placement will consider the routability of the design
`[..., 'var', 'gpl_timing_driven']`	true/false, when true global placement will consider the timing performance of the design
`[..., 'var', 'dpo_enable']`	true/false, when true the detailed placement optimization will be performed
`[..., 'var', 'dpo_max_displacement']`	maximum cell movement in detailed placement optimization in microns, 0 will result in the tool default maximum displacement
`[..., 'var', 'dpl_max_displacement']`	maximum cell movement in detailed placement in microns, 0 will result in the tool default maximum displacement
`[..., 'var', 'dpl_disallow_one_site']`	true/false, disallow single site gaps in detail placement
`[..., 'var', 'cts_clock_buffer']`	buffer to use during clock tree synthesis
`[..., 'var', 'cts_distance_between_buffers']`	maximum distance between buffers during clock tree synthesis in microns
`[..., 'var', 'cts_cluster_diameter']`	clusting distance to use during clock tree synthesis in microns
`[..., 'var', 'cts_cluster_size']`	number of instances in a cluster to use during clock tree synthesis
`[..., 'var', 'cts_balance_levels']`	perform level balancing in clock tree synthesis
`[..., 'var', 'ant_iterations']`	maximum number of repair iterations to use during antenna repairs
`[..., 'var', 'ant_margin']`	adds a margin to the antenna ratios (0 - 100)
`[..., 'var', 'ant_check']`	true/false, flag to indicate whether to check for antenna violations
`[..., 'var', 'ant_repair']`	true/false, flag to indicate whether to repair antenna violations
`[..., 'var', 'grt_use_pin_access']`	true/false, when true perform pin access before global routing
`[..., 'var', 'grt_overflow_iter']`	maximum number of iterations to use in flobal routing when attempting to solve overflow
`[..., 'var', 'grt_macro_extension']`	macro extension distance in number of gcells, this can be useful when the detailed router needs additional space to avoid DRCs
`[..., 'var', 'grt_allow_congestion']`	true/false, when true allow global routing to finish with congestion
`[..., 'var', 'grt_allow_overflow']`	true/false, when true allow global routing to finish with overflow
`[..., 'var', 'grt_signal_min_layer']`	minimum layer to use for global routing of signals
`[..., 'var', 'grt_signal_max_layer']`	maximum layer to use for global routing of signals
`[..., 'var', 'grt_clock_min_layer']`	minimum layer to use for global routing of clock nets
`[..., 'var', 'grt_clock_max_layer']`	maximum layer to use for global routing of clock nets
`[..., 'var', 'drt_disable_via_gen']`	true/false, when true turns off via generation in detailed router and only uses the specified tech vias
`[..., 'var', 'drt_process_node']`	false or value, when set this specifies to the detailed router the specific process node
`[..., 'var', 'drt_via_in_pin_bottom_layer']`	false or value, TODO
`[..., 'var', 'drt_via_in_pin_top_layer']`	false or value, TODO
`[..., 'var', 'drt_repair_pdn_vias']`	false or value, TODO
`[..., 'var', 'drt_via_repair_post_route']`	true/false, when true performs a via ripup step after detailed routing to remove power vias that are causing DRC violations
`[..., 'var', 'rsz_setup_slack_margin']`	specifies the margin to apply when performing setup repair in library timing units
`[..., 'var', 'rsz_hold_slack_margin']`	specifies the margin to apply when performing hold repair in library timing units
`[..., 'var', 'rsz_slew_margin']`	specifies the amount of margin to apply to max slew repairs in percent (0 - 100)
`[..., 'var', 'rsz_cap_margin']`	specifies the amount of margin to apply to max capacitance repairs in percent (0 - 100)
`[..., 'var', 'rsz_buffer_inputs']`	true/false, when true enables adding buffers to the input ports
`[..., 'var', 'rsz_buffer_outputs']`	true/false, when true enables adding buffers to the output ports
`[..., 'var', 'sta_early_timing_derate']`	timing derating factor to use for hold corners
`[..., 'var', 'sta_late_timing_derate']`	timing derating factor to use for setup corners
`[..., 'var', 'fin_add_fill']`	true/false, when true enables adding fill, if enabled by the PDK, to the design
`[..., 'var', 'psm_enable']`	true/false, when true enables IR drop analysis
`[..., 'var', 'debug_level']`	list of “tool key level” to enable debugging of OpenROAD
`[..., 'var', 'sdc_buffer']`	Buffer cell to use when auto generating timing constraints

3.14.6.3. Files#

Parameters	Help
`[..., 'file', 'ifp_tapcell']`	tap cell insertion script
`[..., 'file', 'parasitics']`	file used to specify the parasitics for estimation
`[..., 'file', 'pdn_config']`	list of files to use for power grid generation
`[..., 'file', 'global_connect']`	list of files to use for specifying global connections
`[..., 'file', 'padring']`	script to generate a padring using ICeWall in OpenROAD
`[..., 'file', 'ppl_constraints']`	script constrain pin placement

3.14.7. route#

Performs filler insertion, global routing, antenna repair, and detailed routing

Setup file: route.py

Built using target: asap7_demo

3.14.7.1. Configuration#

Keypath	Value
`['tool', 'openroad', 'task', 'route', 'regex', 'warnings']`	`^\[WARNING\|^Warning`
`['tool', 'openroad', 'task', 'route', 'regex', 'errors']`	`^\[ERROR`
`['tool', 'openroad', 'task', 'route', 'option']`	`-exit -metrics reports/metrics.json`
`['tool', 'openroad', 'task', 'route', 'var', 'timing_corners']`	`fast` `slow` `typical`
`['tool', 'openroad', 'task', 'route', 'var', 'pex_corners']`	`typical`
`['tool', 'openroad', 'task', 'route', 'var', 'power_corner']`	`typical`
`['tool', 'openroad', 'task', 'route', 'var', 'place_density']`	`0.60`
`['tool', 'openroad', 'task', 'route', 'var', 'pad_global_place']`	`2`
`['tool', 'openroad', 'task', 'route', 'var', 'pad_detail_place']`	`1`
`['tool', 'openroad', 'task', 'route', 'var', 'macro_place_halo']`	`10` `10`
`['tool', 'openroad', 'task', 'route', 'var', 'macro_place_channel']`	`12` `12`
`['tool', 'openroad', 'task', 'route', 'var', 'ifp_tie_separation']`	`0`
`['tool', 'openroad', 'task', 'route', 'var', 'ifp_snap_strategy']`	`site`
`['tool', 'openroad', 'task', 'route', 'var', 'pdn_enable']`	`true`
`['tool', 'openroad', 'task', 'route', 'var', 'gpl_routability_driven']`	`true`
`['tool', 'openroad', 'task', 'route', 'var', 'gpl_timing_driven']`	`true`
`['tool', 'openroad', 'task', 'route', 'var', 'dpo_enable']`	`true`
`['tool', 'openroad', 'task', 'route', 'var', 'dpo_max_displacement']`	`0`
`['tool', 'openroad', 'task', 'route', 'var', 'dpl_max_displacement']`	`0`
`['tool', 'openroad', 'task', 'route', 'var', 'dpl_disallow_one_site']`	`false`
`['tool', 'openroad', 'task', 'route', 'var', 'cts_clock_buffer']`	`BUFx2_ASAP7_75t_R`
`['tool', 'openroad', 'task', 'route', 'var', 'cts_distance_between_buffers']`	`100`
`['tool', 'openroad', 'task', 'route', 'var', 'cts_cluster_diameter']`	`100`
`['tool', 'openroad', 'task', 'route', 'var', 'cts_cluster_size']`	`30`
`['tool', 'openroad', 'task', 'route', 'var', 'cts_balance_levels']`	`true`
`['tool', 'openroad', 'task', 'route', 'var', 'ant_iterations']`	`3`
`['tool', 'openroad', 'task', 'route', 'var', 'ant_margin']`	`0`
`['tool', 'openroad', 'task', 'route', 'var', 'ant_check']`	`true`
`['tool', 'openroad', 'task', 'route', 'var', 'ant_repair']`	`true`
`['tool', 'openroad', 'task', 'route', 'var', 'grt_use_pin_access']`	`false`
`['tool', 'openroad', 'task', 'route', 'var', 'grt_overflow_iter']`	`100`
`['tool', 'openroad', 'task', 'route', 'var', 'grt_macro_extension']`	`2`
`['tool', 'openroad', 'task', 'route', 'var', 'grt_allow_congestion']`	`false`
`['tool', 'openroad', 'task', 'route', 'var', 'grt_allow_overflow']`	`false`
`['tool', 'openroad', 'task', 'route', 'var', 'grt_signal_min_layer']`	`M2`
`['tool', 'openroad', 'task', 'route', 'var', 'grt_signal_max_layer']`	`M7`
`['tool', 'openroad', 'task', 'route', 'var', 'grt_clock_min_layer']`	`M2`
`['tool', 'openroad', 'task', 'route', 'var', 'grt_clock_max_layer']`	`M7`
`['tool', 'openroad', 'task', 'route', 'var', 'drt_disable_via_gen']`	`false`
`['tool', 'openroad', 'task', 'route', 'var', 'drt_process_node']`	`false`
`['tool', 'openroad', 'task', 'route', 'var', 'drt_via_in_pin_bottom_layer']`	`false`
`['tool', 'openroad', 'task', 'route', 'var', 'drt_via_in_pin_top_layer']`	`false`
`['tool', 'openroad', 'task', 'route', 'var', 'drt_repair_pdn_vias']`	`false`
`['tool', 'openroad', 'task', 'route', 'var', 'drt_via_repair_post_route']`	`false`
`['tool', 'openroad', 'task', 'route', 'var', 'rsz_setup_slack_margin']`	`0.0`
`['tool', 'openroad', 'task', 'route', 'var', 'rsz_hold_slack_margin']`	`0.0`
`['tool', 'openroad', 'task', 'route', 'var', 'rsz_slew_margin']`	`0.0`
`['tool', 'openroad', 'task', 'route', 'var', 'rsz_cap_margin']`	`0.0`
`['tool', 'openroad', 'task', 'route', 'var', 'rsz_buffer_inputs']`	`false`
`['tool', 'openroad', 'task', 'route', 'var', 'rsz_buffer_outputs']`	`false`
`['tool', 'openroad', 'task', 'route', 'var', 'sta_early_timing_derate']`	`0.0`
`['tool', 'openroad', 'task', 'route', 'var', 'sta_late_timing_derate']`	`0.0`
`['tool', 'openroad', 'task', 'route', 'var', 'fin_add_fill']`	`true`
`['tool', 'openroad', 'task', 'route', 'var', 'psm_enable']`	`true`
`['tool', 'openroad', 'task', 'route', 'file', 'parasitics']`	`/home/docs/checkouts/readthedocs.org/user_builds/siliconcompiler/checkouts/stable/docs/build/<design>/job0/<step>/<index>/inputs/sc_parasitics.tcl`
`['tool', 'openroad', 'task', 'route', 'input']`	`<design>.def`
`['tool', 'openroad', 'task', 'route', 'output']`	`<design>.sdc` `<design>.vg` `<design>.def` `<design>.odb`
`['tool', 'openroad', 'task', 'route', 'require']`	`asic,logiclib` `option,stackup` `library,asap7sc7p5t_rvt,asic,site,7p5t` `pdk,asap7,aprtech,openroad,10M,7p5t,lef` `library,asap7sc7p5t_rvt,output,typical,nldm` `library,asap7sc7p5t_rvt,output,fast,nldm` `library,asap7sc7p5t_rvt,output,slow,nldm` `library,asap7sc7p5t_rvt,output,10M,lef` `pdk,asap7,var,openroad,rclayer_signal,10M` `pdk,asap7,var,openroad,rclayer_clock,10M` `pdk,asap7,var,openroad,pin_layer_horizontal,10M` `pdk,asap7,var,openroad,pin_layer_vertical,10M` `library,asap7sc7p5t_rvt,option,var,openroad_place_density` `tool,openroad,task,route,var,place_density` `library,asap7sc7p5t_rvt,option,var,openroad_pad_global_place` `tool,openroad,task,route,var,pad_global_place` `library,asap7sc7p5t_rvt,option,var,openroad_pad_detail_place` `tool,openroad,task,route,var,pad_detail_place` `library,asap7sc7p5t_rvt,option,var,openroad_macro_place_halo` `tool,openroad,task,route,var,macro_place_halo` `library,asap7sc7p5t_rvt,option,var,openroad_macro_place_channel` `tool,openroad,task,route,var,macro_place_channel` `tool,openroad,task,route,var,cts_clock_buffer`
`['tool', 'openroad', 'task', 'route', 'refdir']`	`tools/openroad`
`['tool', 'openroad', 'task', 'route', 'script']`	`sc_apr.tcl`
`['tool', 'openroad', 'task', 'route', 'threads']`	`2`

3.14.7.2. Variables#

Parameters	Help
`[..., 'var', 'timing_corners']`	list of timing corners to use
`[..., 'var', 'pex_corners']`	list of parasitic extraction corners to use
`[..., 'var', 'power_corner']`	corner to use for power analysis
`[..., 'var', 'place_density']`	global placement density (0.0 - 1.0)
`[..., 'var', 'pad_global_place']`	global placement cell padding in number of sites
`[..., 'var', 'pad_detail_place']`	detailed placement cell padding in number of sites
`[..., 'var', 'macro_place_halo']`	macro halo to use when performing automated macro placement ([x, y] in microns)
`[..., 'var', 'macro_place_channel']`	macro channel to use when performing automated macro placement ([x, y] in microns)
`[..., 'var', 'detailed_route_default_via']`	list of default vias to use for detail routing
`[..., 'var', 'detailed_route_unidirectional_layer']`	list of layers to treat as unidirectional regardless of what the tech lef specifies
`[..., 'var', 'ifp_tie_separation']`	maximum distance between tie high/low cells in microns
`[..., 'var', 'ifp_snap_strategy']`	Snapping strategy to use when placing macros. Allowed values: none, site, manufacturing_grid
`[..., 'var', 'pdn_enable']`	true/false, when true enables power grid generation
`[..., 'var', 'gpl_routability_driven']`	true/false, when true global placement will consider the routability of the design
`[..., 'var', 'gpl_timing_driven']`	true/false, when true global placement will consider the timing performance of the design
`[..., 'var', 'dpo_enable']`	true/false, when true the detailed placement optimization will be performed
`[..., 'var', 'dpo_max_displacement']`	maximum cell movement in detailed placement optimization in microns, 0 will result in the tool default maximum displacement
`[..., 'var', 'dpl_max_displacement']`	maximum cell movement in detailed placement in microns, 0 will result in the tool default maximum displacement
`[..., 'var', 'dpl_disallow_one_site']`	true/false, disallow single site gaps in detail placement
`[..., 'var', 'cts_clock_buffer']`	buffer to use during clock tree synthesis
`[..., 'var', 'cts_distance_between_buffers']`	maximum distance between buffers during clock tree synthesis in microns
`[..., 'var', 'cts_cluster_diameter']`	clusting distance to use during clock tree synthesis in microns
`[..., 'var', 'cts_cluster_size']`	number of instances in a cluster to use during clock tree synthesis
`[..., 'var', 'cts_balance_levels']`	perform level balancing in clock tree synthesis
`[..., 'var', 'ant_iterations']`	maximum number of repair iterations to use during antenna repairs
`[..., 'var', 'ant_margin']`	adds a margin to the antenna ratios (0 - 100)
`[..., 'var', 'ant_check']`	true/false, flag to indicate whether to check for antenna violations
`[..., 'var', 'ant_repair']`	true/false, flag to indicate whether to repair antenna violations
`[..., 'var', 'grt_use_pin_access']`	true/false, when true perform pin access before global routing
`[..., 'var', 'grt_overflow_iter']`	maximum number of iterations to use in flobal routing when attempting to solve overflow
`[..., 'var', 'grt_macro_extension']`	macro extension distance in number of gcells, this can be useful when the detailed router needs additional space to avoid DRCs
`[..., 'var', 'grt_allow_congestion']`	true/false, when true allow global routing to finish with congestion
`[..., 'var', 'grt_allow_overflow']`	true/false, when true allow global routing to finish with overflow
`[..., 'var', 'grt_signal_min_layer']`	minimum layer to use for global routing of signals
`[..., 'var', 'grt_signal_max_layer']`	maximum layer to use for global routing of signals
`[..., 'var', 'grt_clock_min_layer']`	minimum layer to use for global routing of clock nets
`[..., 'var', 'grt_clock_max_layer']`	maximum layer to use for global routing of clock nets
`[..., 'var', 'drt_disable_via_gen']`	true/false, when true turns off via generation in detailed router and only uses the specified tech vias
`[..., 'var', 'drt_process_node']`	false or value, when set this specifies to the detailed router the specific process node
`[..., 'var', 'drt_via_in_pin_bottom_layer']`	false or value, TODO
`[..., 'var', 'drt_via_in_pin_top_layer']`	false or value, TODO
`[..., 'var', 'drt_repair_pdn_vias']`	false or value, TODO
`[..., 'var', 'drt_via_repair_post_route']`	true/false, when true performs a via ripup step after detailed routing to remove power vias that are causing DRC violations
`[..., 'var', 'rsz_setup_slack_margin']`	specifies the margin to apply when performing setup repair in library timing units
`[..., 'var', 'rsz_hold_slack_margin']`	specifies the margin to apply when performing hold repair in library timing units
`[..., 'var', 'rsz_slew_margin']`	specifies the amount of margin to apply to max slew repairs in percent (0 - 100)
`[..., 'var', 'rsz_cap_margin']`	specifies the amount of margin to apply to max capacitance repairs in percent (0 - 100)
`[..., 'var', 'rsz_buffer_inputs']`	true/false, when true enables adding buffers to the input ports
`[..., 'var', 'rsz_buffer_outputs']`	true/false, when true enables adding buffers to the output ports
`[..., 'var', 'sta_early_timing_derate']`	timing derating factor to use for hold corners
`[..., 'var', 'sta_late_timing_derate']`	timing derating factor to use for setup corners
`[..., 'var', 'fin_add_fill']`	true/false, when true enables adding fill, if enabled by the PDK, to the design
`[..., 'var', 'psm_enable']`	true/false, when true enables IR drop analysis
`[..., 'var', 'debug_level']`	list of “tool key level” to enable debugging of OpenROAD
`[..., 'var', 'sdc_buffer']`	Buffer cell to use when auto generating timing constraints

3.14.7.3. Files#

Parameters	Help
`[..., 'file', 'ifp_tapcell']`	tap cell insertion script
`[..., 'file', 'parasitics']`	file used to specify the parasitics for estimation
`[..., 'file', 'pdn_config']`	list of files to use for power grid generation
`[..., 'file', 'global_connect']`	list of files to use for specifying global connections
`[..., 'file', 'padring']`	script to generate a padring using ICeWall in OpenROAD
`[..., 'file', 'ppl_constraints']`	script constrain pin placement

3.14.8. screenshot#

Generate a PNG file from a layout file

Setup file: screenshot.py

Built using target: asap7_demo

3.14.8.1. Configuration#

Keypath	Value
`['tool', 'openroad', 'task', 'screenshot', 'regex', 'warnings']`	`^\[WARNING\|^Warning`
`['tool', 'openroad', 'task', 'screenshot', 'regex', 'errors']`	`^\[ERROR`
`['tool', 'openroad', 'task', 'screenshot', 'option']`	`-exit -metrics reports/metrics.json -no_init -gui`
`['tool', 'openroad', 'task', 'screenshot', 'var', 'show_filepath']`	`<path>`
`['tool', 'openroad', 'task', 'screenshot', 'var', 'timing_corners']`	`fast` `slow` `typical`
`['tool', 'openroad', 'task', 'screenshot', 'var', 'pex_corners']`	`typical`
`['tool', 'openroad', 'task', 'screenshot', 'var', 'power_corner']`	`typical`
`['tool', 'openroad', 'task', 'screenshot', 'var', 'place_density']`	`0.60`
`['tool', 'openroad', 'task', 'screenshot', 'var', 'pad_global_place']`	`2`
`['tool', 'openroad', 'task', 'screenshot', 'var', 'pad_detail_place']`	`1`
`['tool', 'openroad', 'task', 'screenshot', 'var', 'macro_place_halo']`	`10` `10`
`['tool', 'openroad', 'task', 'screenshot', 'var', 'macro_place_channel']`	`12` `12`
`['tool', 'openroad', 'task', 'screenshot', 'var', 'ifp_tie_separation']`	`0`
`['tool', 'openroad', 'task', 'screenshot', 'var', 'ifp_snap_strategy']`	`site`
`['tool', 'openroad', 'task', 'screenshot', 'var', 'pdn_enable']`	`true`
`['tool', 'openroad', 'task', 'screenshot', 'var', 'gpl_routability_driven']`	`true`
`['tool', 'openroad', 'task', 'screenshot', 'var', 'gpl_timing_driven']`	`true`
`['tool', 'openroad', 'task', 'screenshot', 'var', 'dpo_enable']`	`true`
`['tool', 'openroad', 'task', 'screenshot', 'var', 'dpo_max_displacement']`	`0`
`['tool', 'openroad', 'task', 'screenshot', 'var', 'dpl_max_displacement']`	`0`
`['tool', 'openroad', 'task', 'screenshot', 'var', 'dpl_disallow_one_site']`	`false`
`['tool', 'openroad', 'task', 'screenshot', 'var', 'cts_clock_buffer']`	`BUFx2_ASAP7_75t_R`
`['tool', 'openroad', 'task', 'screenshot', 'var', 'cts_distance_between_buffers']`	`100`
`['tool', 'openroad', 'task', 'screenshot', 'var', 'cts_cluster_diameter']`	`100`
`['tool', 'openroad', 'task', 'screenshot', 'var', 'cts_cluster_size']`	`30`
`['tool', 'openroad', 'task', 'screenshot', 'var', 'cts_balance_levels']`	`true`
`['tool', 'openroad', 'task', 'screenshot', 'var', 'ant_iterations']`	`3`
`['tool', 'openroad', 'task', 'screenshot', 'var', 'ant_margin']`	`0`
`['tool', 'openroad', 'task', 'screenshot', 'var', 'ant_check']`	`true`
`['tool', 'openroad', 'task', 'screenshot', 'var', 'ant_repair']`	`true`
`['tool', 'openroad', 'task', 'screenshot', 'var', 'grt_use_pin_access']`	`false`
`['tool', 'openroad', 'task', 'screenshot', 'var', 'grt_overflow_iter']`	`100`
`['tool', 'openroad', 'task', 'screenshot', 'var', 'grt_macro_extension']`	`2`
`['tool', 'openroad', 'task', 'screenshot', 'var', 'grt_allow_congestion']`	`false`
`['tool', 'openroad', 'task', 'screenshot', 'var', 'grt_allow_overflow']`	`false`
`['tool', 'openroad', 'task', 'screenshot', 'var', 'grt_signal_min_layer']`	`M2`
`['tool', 'openroad', 'task', 'screenshot', 'var', 'grt_signal_max_layer']`	`M7`
`['tool', 'openroad', 'task', 'screenshot', 'var', 'grt_clock_min_layer']`	`M2`
`['tool', 'openroad', 'task', 'screenshot', 'var', 'grt_clock_max_layer']`	`M7`
`['tool', 'openroad', 'task', 'screenshot', 'var', 'drt_disable_via_gen']`	`false`
`['tool', 'openroad', 'task', 'screenshot', 'var', 'drt_process_node']`	`false`
`['tool', 'openroad', 'task', 'screenshot', 'var', 'drt_via_in_pin_bottom_layer']`	`false`
`['tool', 'openroad', 'task', 'screenshot', 'var', 'drt_via_in_pin_top_layer']`	`false`
`['tool', 'openroad', 'task', 'screenshot', 'var', 'drt_repair_pdn_vias']`	`false`
`['tool', 'openroad', 'task', 'screenshot', 'var', 'drt_via_repair_post_route']`	`false`
`['tool', 'openroad', 'task', 'screenshot', 'var', 'rsz_setup_slack_margin']`	`0.0`
`['tool', 'openroad', 'task', 'screenshot', 'var', 'rsz_hold_slack_margin']`	`0.0`
`['tool', 'openroad', 'task', 'screenshot', 'var', 'rsz_slew_margin']`	`0.0`
`['tool', 'openroad', 'task', 'screenshot', 'var', 'rsz_cap_margin']`	`0.0`
`['tool', 'openroad', 'task', 'screenshot', 'var', 'rsz_buffer_inputs']`	`false`
`['tool', 'openroad', 'task', 'screenshot', 'var', 'rsz_buffer_outputs']`	`false`
`['tool', 'openroad', 'task', 'screenshot', 'var', 'sta_early_timing_derate']`	`0.0`
`['tool', 'openroad', 'task', 'screenshot', 'var', 'sta_late_timing_derate']`	`0.0`
`['tool', 'openroad', 'task', 'screenshot', 'var', 'fin_add_fill']`	`true`
`['tool', 'openroad', 'task', 'screenshot', 'var', 'psm_enable']`	`true`
`['tool', 'openroad', 'task', 'screenshot', 'var', 'show_exit']`	`true`
`['tool', 'openroad', 'task', 'screenshot', 'var', 'show_vertical_resolution']`	`1024`
`['tool', 'openroad', 'task', 'screenshot', 'file', 'parasitics']`	`/home/docs/checkouts/readthedocs.org/user_builds/siliconcompiler/checkouts/stable/docs/build/<design>/job0/<step>/<index>/inputs/sc_parasitics.tcl`
`['tool', 'openroad', 'task', 'screenshot', 'output']`	`<design>.sdc` `<design>.vg` `<design>.def` `<design>.odb` `<design>.png`
`['tool', 'openroad', 'task', 'screenshot', 'require']`	`asic,logiclib` `option,stackup` `library,asap7sc7p5t_rvt,asic,site,7p5t` `pdk,asap7,aprtech,openroad,10M,7p5t,lef` `library,asap7sc7p5t_rvt,output,typical,nldm` `library,asap7sc7p5t_rvt,output,fast,nldm` `library,asap7sc7p5t_rvt,output,slow,nldm` `library,asap7sc7p5t_rvt,output,10M,lef` `pdk,asap7,var,openroad,rclayer_signal,10M` `pdk,asap7,var,openroad,rclayer_clock,10M` `pdk,asap7,var,openroad,pin_layer_horizontal,10M` `pdk,asap7,var,openroad,pin_layer_vertical,10M` `library,asap7sc7p5t_rvt,option,var,openroad_place_density` `tool,openroad,task,screenshot,var,place_density` `library,asap7sc7p5t_rvt,option,var,openroad_pad_global_place` `tool,openroad,task,screenshot,var,pad_global_place` `library,asap7sc7p5t_rvt,option,var,openroad_pad_detail_place` `tool,openroad,task,screenshot,var,pad_detail_place` `library,asap7sc7p5t_rvt,option,var,openroad_macro_place_halo` `tool,openroad,task,screenshot,var,macro_place_halo` `library,asap7sc7p5t_rvt,option,var,openroad_macro_place_channel` `tool,openroad,task,screenshot,var,macro_place_channel` `tool,openroad,task,screenshot,var,cts_clock_buffer` `tool,openroad,task,screenshot,var,show_filepath`
`['tool', 'openroad', 'task', 'screenshot', 'refdir']`	`tools/openroad`
`['tool', 'openroad', 'task', 'screenshot', 'script']`	`sc_apr.tcl`
`['tool', 'openroad', 'task', 'screenshot', 'threads']`	`2`

3.14.8.2. Variables#

Parameters	Help
`[..., 'var', 'show_filepath']`	Task script variables specified as key value pairs. Variable names and value types must match the name and type of task and reference script consuming the variable.
`[..., 'var', 'timing_corners']`	list of timing corners to use
`[..., 'var', 'pex_corners']`	list of parasitic extraction corners to use
`[..., 'var', 'power_corner']`	corner to use for power analysis
`[..., 'var', 'place_density']`	global placement density (0.0 - 1.0)
`[..., 'var', 'pad_global_place']`	global placement cell padding in number of sites
`[..., 'var', 'pad_detail_place']`	detailed placement cell padding in number of sites
`[..., 'var', 'macro_place_halo']`	macro halo to use when performing automated macro placement ([x, y] in microns)
`[..., 'var', 'macro_place_channel']`	macro channel to use when performing automated macro placement ([x, y] in microns)
`[..., 'var', 'detailed_route_default_via']`	list of default vias to use for detail routing
`[..., 'var', 'detailed_route_unidirectional_layer']`	list of layers to treat as unidirectional regardless of what the tech lef specifies
`[..., 'var', 'ifp_tie_separation']`	maximum distance between tie high/low cells in microns
`[..., 'var', 'ifp_snap_strategy']`	Snapping strategy to use when placing macros. Allowed values: none, site, manufacturing_grid
`[..., 'var', 'pdn_enable']`	true/false, when true enables power grid generation
`[..., 'var', 'gpl_routability_driven']`	true/false, when true global placement will consider the routability of the design
`[..., 'var', 'gpl_timing_driven']`	true/false, when true global placement will consider the timing performance of the design
`[..., 'var', 'dpo_enable']`	true/false, when true the detailed placement optimization will be performed
`[..., 'var', 'dpo_max_displacement']`	maximum cell movement in detailed placement optimization in microns, 0 will result in the tool default maximum displacement
`[..., 'var', 'dpl_max_displacement']`	maximum cell movement in detailed placement in microns, 0 will result in the tool default maximum displacement
`[..., 'var', 'dpl_disallow_one_site']`	true/false, disallow single site gaps in detail placement
`[..., 'var', 'cts_clock_buffer']`	buffer to use during clock tree synthesis
`[..., 'var', 'cts_distance_between_buffers']`	maximum distance between buffers during clock tree synthesis in microns
`[..., 'var', 'cts_cluster_diameter']`	clusting distance to use during clock tree synthesis in microns
`[..., 'var', 'cts_cluster_size']`	number of instances in a cluster to use during clock tree synthesis
`[..., 'var', 'cts_balance_levels']`	perform level balancing in clock tree synthesis
`[..., 'var', 'ant_iterations']`	maximum number of repair iterations to use during antenna repairs
`[..., 'var', 'ant_margin']`	adds a margin to the antenna ratios (0 - 100)
`[..., 'var', 'ant_check']`	true/false, flag to indicate whether to check for antenna violations
`[..., 'var', 'ant_repair']`	true/false, flag to indicate whether to repair antenna violations
`[..., 'var', 'grt_use_pin_access']`	true/false, when true perform pin access before global routing
`[..., 'var', 'grt_overflow_iter']`	maximum number of iterations to use in flobal routing when attempting to solve overflow
`[..., 'var', 'grt_macro_extension']`	macro extension distance in number of gcells, this can be useful when the detailed router needs additional space to avoid DRCs
`[..., 'var', 'grt_allow_congestion']`	true/false, when true allow global routing to finish with congestion
`[..., 'var', 'grt_allow_overflow']`	true/false, when true allow global routing to finish with overflow
`[..., 'var', 'grt_signal_min_layer']`	minimum layer to use for global routing of signals
`[..., 'var', 'grt_signal_max_layer']`	maximum layer to use for global routing of signals
`[..., 'var', 'grt_clock_min_layer']`	minimum layer to use for global routing of clock nets
`[..., 'var', 'grt_clock_max_layer']`	maximum layer to use for global routing of clock nets
`[..., 'var', 'drt_disable_via_gen']`	true/false, when true turns off via generation in detailed router and only uses the specified tech vias
`[..., 'var', 'drt_process_node']`	false or value, when set this specifies to the detailed router the specific process node
`[..., 'var', 'drt_via_in_pin_bottom_layer']`	false or value, TODO
`[..., 'var', 'drt_via_in_pin_top_layer']`	false or value, TODO
`[..., 'var', 'drt_repair_pdn_vias']`	false or value, TODO
`[..., 'var', 'drt_via_repair_post_route']`	true/false, when true performs a via ripup step after detailed routing to remove power vias that are causing DRC violations
`[..., 'var', 'rsz_setup_slack_margin']`	specifies the margin to apply when performing setup repair in library timing units
`[..., 'var', 'rsz_hold_slack_margin']`	specifies the margin to apply when performing hold repair in library timing units
`[..., 'var', 'rsz_slew_margin']`	specifies the amount of margin to apply to max slew repairs in percent (0 - 100)
`[..., 'var', 'rsz_cap_margin']`	specifies the amount of margin to apply to max capacitance repairs in percent (0 - 100)
`[..., 'var', 'rsz_buffer_inputs']`	true/false, when true enables adding buffers to the input ports
`[..., 'var', 'rsz_buffer_outputs']`	true/false, when true enables adding buffers to the output ports
`[..., 'var', 'sta_early_timing_derate']`	timing derating factor to use for hold corners
`[..., 'var', 'sta_late_timing_derate']`	timing derating factor to use for setup corners
`[..., 'var', 'fin_add_fill']`	true/false, when true enables adding fill, if enabled by the PDK, to the design
`[..., 'var', 'psm_enable']`	true/false, when true enables IR drop analysis
`[..., 'var', 'debug_level']`	list of “tool key level” to enable debugging of OpenROAD
`[..., 'var', 'sdc_buffer']`	Buffer cell to use when auto generating timing constraints
`[..., 'var', 'show_exit']`	Task script variables specified as key value pairs. Variable names and value types must match the name and type of task and reference script consuming the variable.
`[..., 'var', 'show_vertical_resolution']`	Task script variables specified as key value pairs. Variable names and value types must match the name and type of task and reference script consuming the variable.

3.14.8.3. Files#

Parameters	Help
`[..., 'file', 'ifp_tapcell']`	tap cell insertion script
`[..., 'file', 'parasitics']`	file used to specify the parasitics for estimation
`[..., 'file', 'pdn_config']`	list of files to use for power grid generation
`[..., 'file', 'global_connect']`	list of files to use for specifying global connections
`[..., 'file', 'padring']`	script to generate a padring using ICeWall in OpenROAD
`[..., 'file', 'ppl_constraints']`	script constrain pin placement

3.14.9. show#

Show a design in openroad

Setup file: show.py

Built using target: asap7_demo

3.14.9.1. Configuration#

Keypath	Value
`['tool', 'openroad', 'task', 'show', 'regex', 'warnings']`	`^\[WARNING\|^Warning`
`['tool', 'openroad', 'task', 'show', 'regex', 'errors']`	`^\[ERROR`
`['tool', 'openroad', 'task', 'show', 'option']`	`-metrics reports/metrics.json -no_init -gui`
`['tool', 'openroad', 'task', 'show', 'var', 'show_filepath']`	`<path>`
`['tool', 'openroad', 'task', 'show', 'var', 'timing_corners']`	`fast` `slow` `typical`
`['tool', 'openroad', 'task', 'show', 'var', 'pex_corners']`	`typical`
`['tool', 'openroad', 'task', 'show', 'var', 'power_corner']`	`typical`
`['tool', 'openroad', 'task', 'show', 'var', 'place_density']`	`0.60`
`['tool', 'openroad', 'task', 'show', 'var', 'pad_global_place']`	`2`
`['tool', 'openroad', 'task', 'show', 'var', 'pad_detail_place']`	`1`
`['tool', 'openroad', 'task', 'show', 'var', 'macro_place_halo']`	`10` `10`
`['tool', 'openroad', 'task', 'show', 'var', 'macro_place_channel']`	`12` `12`
`['tool', 'openroad', 'task', 'show', 'var', 'ifp_tie_separation']`	`0`
`['tool', 'openroad', 'task', 'show', 'var', 'ifp_snap_strategy']`	`site`
`['tool', 'openroad', 'task', 'show', 'var', 'pdn_enable']`	`true`
`['tool', 'openroad', 'task', 'show', 'var', 'gpl_routability_driven']`	`true`
`['tool', 'openroad', 'task', 'show', 'var', 'gpl_timing_driven']`	`true`
`['tool', 'openroad', 'task', 'show', 'var', 'dpo_enable']`	`true`
`['tool', 'openroad', 'task', 'show', 'var', 'dpo_max_displacement']`	`0`
`['tool', 'openroad', 'task', 'show', 'var', 'dpl_max_displacement']`	`0`
`['tool', 'openroad', 'task', 'show', 'var', 'dpl_disallow_one_site']`	`false`
`['tool', 'openroad', 'task', 'show', 'var', 'cts_clock_buffer']`	`BUFx2_ASAP7_75t_R`
`['tool', 'openroad', 'task', 'show', 'var', 'cts_distance_between_buffers']`	`100`
`['tool', 'openroad', 'task', 'show', 'var', 'cts_cluster_diameter']`	`100`
`['tool', 'openroad', 'task', 'show', 'var', 'cts_cluster_size']`	`30`
`['tool', 'openroad', 'task', 'show', 'var', 'cts_balance_levels']`	`true`
`['tool', 'openroad', 'task', 'show', 'var', 'ant_iterations']`	`3`
`['tool', 'openroad', 'task', 'show', 'var', 'ant_margin']`	`0`
`['tool', 'openroad', 'task', 'show', 'var', 'ant_check']`	`true`
`['tool', 'openroad', 'task', 'show', 'var', 'ant_repair']`	`true`
`['tool', 'openroad', 'task', 'show', 'var', 'grt_use_pin_access']`	`false`
`['tool', 'openroad', 'task', 'show', 'var', 'grt_overflow_iter']`	`100`
`['tool', 'openroad', 'task', 'show', 'var', 'grt_macro_extension']`	`2`
`['tool', 'openroad', 'task', 'show', 'var', 'grt_allow_congestion']`	`false`
`['tool', 'openroad', 'task', 'show', 'var', 'grt_allow_overflow']`	`false`
`['tool', 'openroad', 'task', 'show', 'var', 'grt_signal_min_layer']`	`M2`
`['tool', 'openroad', 'task', 'show', 'var', 'grt_signal_max_layer']`	`M7`
`['tool', 'openroad', 'task', 'show', 'var', 'grt_clock_min_layer']`	`M2`
`['tool', 'openroad', 'task', 'show', 'var', 'grt_clock_max_layer']`	`M7`
`['tool', 'openroad', 'task', 'show', 'var', 'drt_disable_via_gen']`	`false`
`['tool', 'openroad', 'task', 'show', 'var', 'drt_process_node']`	`false`
`['tool', 'openroad', 'task', 'show', 'var', 'drt_via_in_pin_bottom_layer']`	`false`
`['tool', 'openroad', 'task', 'show', 'var', 'drt_via_in_pin_top_layer']`	`false`
`['tool', 'openroad', 'task', 'show', 'var', 'drt_repair_pdn_vias']`	`false`
`['tool', 'openroad', 'task', 'show', 'var', 'drt_via_repair_post_route']`	`false`
`['tool', 'openroad', 'task', 'show', 'var', 'rsz_setup_slack_margin']`	`0.0`
`['tool', 'openroad', 'task', 'show', 'var', 'rsz_hold_slack_margin']`	`0.0`
`['tool', 'openroad', 'task', 'show', 'var', 'rsz_slew_margin']`	`0.0`
`['tool', 'openroad', 'task', 'show', 'var', 'rsz_cap_margin']`	`0.0`
`['tool', 'openroad', 'task', 'show', 'var', 'rsz_buffer_inputs']`	`false`
`['tool', 'openroad', 'task', 'show', 'var', 'rsz_buffer_outputs']`	`false`
`['tool', 'openroad', 'task', 'show', 'var', 'sta_early_timing_derate']`	`0.0`
`['tool', 'openroad', 'task', 'show', 'var', 'sta_late_timing_derate']`	`0.0`
`['tool', 'openroad', 'task', 'show', 'var', 'fin_add_fill']`	`true`
`['tool', 'openroad', 'task', 'show', 'var', 'psm_enable']`	`true`
`['tool', 'openroad', 'task', 'show', 'var', 'show_exit']`	`false`
`['tool', 'openroad', 'task', 'show', 'file', 'parasitics']`	`/home/docs/checkouts/readthedocs.org/user_builds/siliconcompiler/checkouts/stable/docs/build/<design>/job0/<step>/<index>/inputs/sc_parasitics.tcl`
`['tool', 'openroad', 'task', 'show', 'output']`	`<design>.sdc` `<design>.vg` `<design>.def` `<design>.odb`
`['tool', 'openroad', 'task', 'show', 'require']`	`asic,logiclib` `option,stackup` `library,asap7sc7p5t_rvt,asic,site,7p5t` `pdk,asap7,aprtech,openroad,10M,7p5t,lef` `library,asap7sc7p5t_rvt,output,typical,nldm` `library,asap7sc7p5t_rvt,output,fast,nldm` `library,asap7sc7p5t_rvt,output,slow,nldm` `library,asap7sc7p5t_rvt,output,10M,lef` `pdk,asap7,var,openroad,rclayer_signal,10M` `pdk,asap7,var,openroad,rclayer_clock,10M` `pdk,asap7,var,openroad,pin_layer_horizontal,10M` `pdk,asap7,var,openroad,pin_layer_vertical,10M` `library,asap7sc7p5t_rvt,option,var,openroad_place_density` `tool,openroad,task,show,var,place_density` `library,asap7sc7p5t_rvt,option,var,openroad_pad_global_place` `tool,openroad,task,show,var,pad_global_place` `library,asap7sc7p5t_rvt,option,var,openroad_pad_detail_place` `tool,openroad,task,show,var,pad_detail_place` `library,asap7sc7p5t_rvt,option,var,openroad_macro_place_halo` `tool,openroad,task,show,var,macro_place_halo` `library,asap7sc7p5t_rvt,option,var,openroad_macro_place_channel` `tool,openroad,task,show,var,macro_place_channel` `tool,openroad,task,show,var,cts_clock_buffer` `tool,openroad,task,show,var,show_filepath`
`['tool', 'openroad', 'task', 'show', 'refdir']`	`tools/openroad`
`['tool', 'openroad', 'task', 'show', 'script']`	`sc_apr.tcl`
`['tool', 'openroad', 'task', 'show', 'threads']`	`2`

3.14.9.2. Variables#

Parameters	Help
`[..., 'var', 'show_filepath']`	Task script variables specified as key value pairs. Variable names and value types must match the name and type of task and reference script consuming the variable.
`[..., 'var', 'timing_corners']`	list of timing corners to use
`[..., 'var', 'pex_corners']`	list of parasitic extraction corners to use
`[..., 'var', 'power_corner']`	corner to use for power analysis
`[..., 'var', 'place_density']`	global placement density (0.0 - 1.0)
`[..., 'var', 'pad_global_place']`	global placement cell padding in number of sites
`[..., 'var', 'pad_detail_place']`	detailed placement cell padding in number of sites
`[..., 'var', 'macro_place_halo']`	macro halo to use when performing automated macro placement ([x, y] in microns)
`[..., 'var', 'macro_place_channel']`	macro channel to use when performing automated macro placement ([x, y] in microns)
`[..., 'var', 'detailed_route_default_via']`	list of default vias to use for detail routing
`[..., 'var', 'detailed_route_unidirectional_layer']`	list of layers to treat as unidirectional regardless of what the tech lef specifies
`[..., 'var', 'ifp_tie_separation']`	maximum distance between tie high/low cells in microns
`[..., 'var', 'ifp_snap_strategy']`	Snapping strategy to use when placing macros. Allowed values: none, site, manufacturing_grid
`[..., 'var', 'pdn_enable']`	true/false, when true enables power grid generation
`[..., 'var', 'gpl_routability_driven']`	true/false, when true global placement will consider the routability of the design
`[..., 'var', 'gpl_timing_driven']`	true/false, when true global placement will consider the timing performance of the design
`[..., 'var', 'dpo_enable']`	true/false, when true the detailed placement optimization will be performed
`[..., 'var', 'dpo_max_displacement']`	maximum cell movement in detailed placement optimization in microns, 0 will result in the tool default maximum displacement
`[..., 'var', 'dpl_max_displacement']`	maximum cell movement in detailed placement in microns, 0 will result in the tool default maximum displacement
`[..., 'var', 'dpl_disallow_one_site']`	true/false, disallow single site gaps in detail placement
`[..., 'var', 'cts_clock_buffer']`	buffer to use during clock tree synthesis
`[..., 'var', 'cts_distance_between_buffers']`	maximum distance between buffers during clock tree synthesis in microns
`[..., 'var', 'cts_cluster_diameter']`	clusting distance to use during clock tree synthesis in microns
`[..., 'var', 'cts_cluster_size']`	number of instances in a cluster to use during clock tree synthesis
`[..., 'var', 'cts_balance_levels']`	perform level balancing in clock tree synthesis
`[..., 'var', 'ant_iterations']`	maximum number of repair iterations to use during antenna repairs
`[..., 'var', 'ant_margin']`	adds a margin to the antenna ratios (0 - 100)
`[..., 'var', 'ant_check']`	true/false, flag to indicate whether to check for antenna violations
`[..., 'var', 'ant_repair']`	true/false, flag to indicate whether to repair antenna violations
`[..., 'var', 'grt_use_pin_access']`	true/false, when true perform pin access before global routing
`[..., 'var', 'grt_overflow_iter']`	maximum number of iterations to use in flobal routing when attempting to solve overflow
`[..., 'var', 'grt_macro_extension']`	macro extension distance in number of gcells, this can be useful when the detailed router needs additional space to avoid DRCs
`[..., 'var', 'grt_allow_congestion']`	true/false, when true allow global routing to finish with congestion
`[..., 'var', 'grt_allow_overflow']`	true/false, when true allow global routing to finish with overflow
`[..., 'var', 'grt_signal_min_layer']`	minimum layer to use for global routing of signals
`[..., 'var', 'grt_signal_max_layer']`	maximum layer to use for global routing of signals
`[..., 'var', 'grt_clock_min_layer']`	minimum layer to use for global routing of clock nets
`[..., 'var', 'grt_clock_max_layer']`	maximum layer to use for global routing of clock nets
`[..., 'var', 'drt_disable_via_gen']`	true/false, when true turns off via generation in detailed router and only uses the specified tech vias
`[..., 'var', 'drt_process_node']`	false or value, when set this specifies to the detailed router the specific process node
`[..., 'var', 'drt_via_in_pin_bottom_layer']`	false or value, TODO
`[..., 'var', 'drt_via_in_pin_top_layer']`	false or value, TODO
`[..., 'var', 'drt_repair_pdn_vias']`	false or value, TODO
`[..., 'var', 'drt_via_repair_post_route']`	true/false, when true performs a via ripup step after detailed routing to remove power vias that are causing DRC violations
`[..., 'var', 'rsz_setup_slack_margin']`	specifies the margin to apply when performing setup repair in library timing units
`[..., 'var', 'rsz_hold_slack_margin']`	specifies the margin to apply when performing hold repair in library timing units
`[..., 'var', 'rsz_slew_margin']`	specifies the amount of margin to apply to max slew repairs in percent (0 - 100)
`[..., 'var', 'rsz_cap_margin']`	specifies the amount of margin to apply to max capacitance repairs in percent (0 - 100)
`[..., 'var', 'rsz_buffer_inputs']`	true/false, when true enables adding buffers to the input ports
`[..., 'var', 'rsz_buffer_outputs']`	true/false, when true enables adding buffers to the output ports
`[..., 'var', 'sta_early_timing_derate']`	timing derating factor to use for hold corners
`[..., 'var', 'sta_late_timing_derate']`	timing derating factor to use for setup corners
`[..., 'var', 'fin_add_fill']`	true/false, when true enables adding fill, if enabled by the PDK, to the design
`[..., 'var', 'psm_enable']`	true/false, when true enables IR drop analysis
`[..., 'var', 'debug_level']`	list of “tool key level” to enable debugging of OpenROAD
`[..., 'var', 'sdc_buffer']`	Buffer cell to use when auto generating timing constraints
`[..., 'var', 'show_exit']`	Task script variables specified as key value pairs. Variable names and value types must match the name and type of task and reference script consuming the variable.

3.14.9.3. Files#

Parameters	Help
`[..., 'file', 'ifp_tapcell']`	tap cell insertion script
`[..., 'file', 'parasitics']`	file used to specify the parasitics for estimation
`[..., 'file', 'pdn_config']`	list of files to use for power grid generation
`[..., 'file', 'global_connect']`	list of files to use for specifying global connections
`[..., 'file', 'padring']`	script to generate a padring using ICeWall in OpenROAD
`[..., 'file', 'ppl_constraints']`	script constrain pin placement

3.15. surelog#

Surelog is a SystemVerilog pre-processor, parser, elaborator, and UHDM compiler that provdes IEEE design and testbench C/C++ VPI and a Python AST API.

Documentation: https://github.com/chipsalliance/Surelog

Sources: https://github.com/chipsalliance/Surelog

Installation: https://github.com/chipsalliance/Surelog

Setup file: surelog.py

Keypath	Value
`['tool', 'surelog', 'exe']`	`surelog`
`['tool', 'surelog', 'vswitch']`	`--version`
`['tool', 'surelog', 'version']`	`>=1.51`

3.15.1. parse#

Import verilog files

Setup file: parse.py

3.15.1.1. Configuration#

Keypath	Value
`['tool', 'surelog', 'task', 'parse', 'regex', 'warnings']`	`^\[WRN:`
`['tool', 'surelog', 'task', 'parse', 'regex', 'errors']`	`^\[(ERR\|FTL\|SNT):`
`['tool', 'surelog', 'task', 'parse', 'option']`	`-nocache` `-parse` `-nouhdm`
`['tool', 'surelog', 'task', 'parse', 'output']`	`<design>.v`
`['tool', 'surelog', 'task', 'parse', 'require']`	`input,rtl,verilog`
`['tool', 'surelog', 'task', 'parse', 'threads']`	`2`

3.16. sv2v#

sv2v converts SystemVerilog (IEEE 1800-2017) to Verilog (IEEE 1364-2005), with an emphasis on supporting synthesizable language constructs. The primary goal of this project is to create a completely free and open-source tool for converting SystemVerilog to Verilog. While methods for performing this conversion already exist, they generally either rely on commercial tools, or are limited in scope.

Documentation: https://github.com/zachjs/sv2v

Sources: https://github.com/zachjs/sv2v

Installation: https://github.com/zachjs/sv2v

Setup file: sv2v.py

Keypath	Value
`['tool', 'sv2v', 'exe']`	`sv2v`
`['tool', 'sv2v', 'vswitch']`	`--numeric-version`
`['tool', 'sv2v', 'version']`	`>=0.0.9`

3.16.1. convert#

Convert SystemVerilog to verilog

Setup file: convert.py

3.16.1.1. Configuration#

Keypath	Value
`['tool', 'sv2v', 'task', 'convert', 'option']`	`inputs/<design>.v` `--write=outputs/<design>.v`
`['tool', 'sv2v', 'task', 'convert', 'input']`	`<design>.v`
`['tool', 'sv2v', 'task', 'convert', 'output']`	`<design>.v`
`['tool', 'sv2v', 'task', 'convert', 'threads']`	`2`

3.17. verilator#

Verilator is a free and open-source software tool which converts Verilog (a hardware description language) to a cycle-accurate behavioral model in C++ or SystemC.

All Verilator tasks may consume input either from a single pickled Verilog file (inputs/<design>.v) generated by a preceeding task, or if that file does not exist, through the following keypaths:

['input', 'rtl', 'verilog']

['option', 'ydir']

['option', 'vlib']

['option', 'idir']

['option', 'cmdfile']

For all tasks, this driver runs Verilator using the -sv switch to enable parsing a subset of SystemVerilog features. All tasks also support using ['option', 'relax'] to make warnings nonfatal.

Documentation: https://verilator.org/guide/latest

Sources: https://github.com/verilator/verilator

Installation: https://verilator.org/guide/latest/install.html

Setup file: verilator.py

Keypath	Value
`['tool', 'verilator', 'exe']`	`verilator`
`['tool', 'verilator', 'vswitch']`	`--version`
`['tool', 'verilator', 'version']`	`>=4.028`

3.17.1. compile#

Compiles Verilog and C/C++ sources into an executable. In addition to the standard RTL inputs, this task reads C/C++ sources from ['input', 'hll', 'c']. Outputs an executable in outputs/<design>.vexe.

This task supports using the ['option', 'trace'] parameter to enable Verilator’s --trace flag.

Setup file: compile.py

Built using target: freepdk45_demo

3.17.1.1. Configuration#

Keypath	Value
`['tool', 'verilator', 'task', 'compile', 'regex', 'warnings']`	`^\%Warning`
`['tool', 'verilator', 'task', 'compile', 'regex', 'errors']`	`^\%Error`
`['tool', 'verilator', 'task', 'compile', 'option']`	`-sv` `--top-module <design>` `--cc` `--exe` `-o ../outputs/<design>.vexe`
`['tool', 'verilator', 'task', 'compile', 'threads']`	`2`

3.17.1.2. Variables#

Parameters	Help
`[..., 'var', 'cflags']`	flags to provide to the C++ compiler invoked by Verilator
`[..., 'var', 'ldflags']`	flags to provide to the linker invoked by Verilator

3.17.1.3. Files#

Parameters	Help
`[..., 'file', 'config']`	Verilator configuration file

3.17.2. lint#

Lints Verilog source. Results of linting can be programatically queried using errors/warnings metrics.

Setup file: lint.py

Built using target: freepdk45_demo

3.17.2.1. Configuration#

Keypath	Value
`['tool', 'verilator', 'task', 'lint', 'regex', 'warnings']`	`^\%Warning`
`['tool', 'verilator', 'task', 'lint', 'regex', 'errors']`	`^\%Error`
`['tool', 'verilator', 'task', 'lint', 'option']`	`-sv` `--top-module <design>` `--lint-only`
`['tool', 'verilator', 'task', 'lint', 'threads']`	`2`

3.17.2.2. Files#

Parameters	Help
`[..., 'file', 'config']`	Verilator configuration file

3.18. vivado#

Vivado is an FPGA programming tool suite from Xilinx used to program Xilinx devices.

Documentation: https://www.xilinx.com/products/design-tools/vivado.html

Setup file: vivado.py

Keypath	Value
`['tool', 'vivado', 'exe']`	`vivado`
`['tool', 'vivado', 'vswitch']`	`-version`
`['tool', 'vivado', 'vendor']`	`xilinx`
`['tool', 'vivado', 'version']`	`>=2021`
`['tool', 'vivado', 'format']`	`tcl`

3.18.1. bitstream#

Generates bitstream of implemented design.

Setup file: bitstream.py

Built using target: fpgaflow_demo

3.18.1.1. Configuration#

Keypath	Value
`['tool', 'vivado', 'task', 'bitstream', 'regex', 'errors']`	`^ERROR:`
`['tool', 'vivado', 'task', 'bitstream', 'regex', 'warnings']`	`^(CRITICAL )?WARNING:`
`['tool', 'vivado', 'task', 'bitstream', 'option']`	`-nolog` `-nojournal` `-mode` `batch` `-source`
`['tool', 'vivado', 'task', 'bitstream', 'input']`	`<design>_checkpoint.dcp`
`['tool', 'vivado', 'task', 'bitstream', 'output']`	`<design>.bit`
`['tool', 'vivado', 'task', 'bitstream', 'refdir']`	`tools/vivado/scripts`
`['tool', 'vivado', 'task', 'bitstream', 'script']`	`sc_run.tcl`
`['tool', 'vivado', 'task', 'bitstream', 'threads']`	`2`

3.18.2. place#

Performs placement.

Setup file: place.py

Built using target: fpgaflow_demo

3.18.2.1. Configuration#

Keypath	Value
`['tool', 'vivado', 'task', 'place', 'regex', 'errors']`	`^ERROR:`
`['tool', 'vivado', 'task', 'place', 'regex', 'warnings']`	`^(CRITICAL )?WARNING:`
`['tool', 'vivado', 'task', 'place', 'option']`	`-nolog` `-nojournal` `-mode` `batch` `-source`
`['tool', 'vivado', 'task', 'place', 'input']`	`<design>_checkpoint.dcp`
`['tool', 'vivado', 'task', 'place', 'output']`	`<design>_checkpoint.dcp`
`['tool', 'vivado', 'task', 'place', 'refdir']`	`tools/vivado/scripts`
`['tool', 'vivado', 'task', 'place', 'script']`	`sc_run.tcl`
`['tool', 'vivado', 'task', 'place', 'threads']`	`2`

3.18.3. route#

Performs routing.

Setup file: route.py

Built using target: fpgaflow_demo

3.18.3.1. Configuration#

Keypath	Value
`['tool', 'vivado', 'task', 'route', 'regex', 'errors']`	`^ERROR:`
`['tool', 'vivado', 'task', 'route', 'regex', 'warnings']`	`^(CRITICAL )?WARNING:`
`['tool', 'vivado', 'task', 'route', 'option']`	`-nolog` `-nojournal` `-mode` `batch` `-source`
`['tool', 'vivado', 'task', 'route', 'input']`	`<design>_checkpoint.dcp`
`['tool', 'vivado', 'task', 'route', 'output']`	`<design>_checkpoint.dcp`
`['tool', 'vivado', 'task', 'route', 'refdir']`	`tools/vivado/scripts`
`['tool', 'vivado', 'task', 'route', 'script']`	`sc_run.tcl`
`['tool', 'vivado', 'task', 'route', 'threads']`	`2`

3.18.4. syn_fpga#

Performs FPGA synthesis.

Setup file: syn_fpga.py

Built using target: fpgaflow_demo

3.18.4.1. Configuration#

Keypath	Value
`['tool', 'vivado', 'task', 'syn_fpga', 'regex', 'errors']`	`^ERROR:`
`['tool', 'vivado', 'task', 'syn_fpga', 'regex', 'warnings']`	`^(CRITICAL )?WARNING:`
`['tool', 'vivado', 'task', 'syn_fpga', 'option']`	`-nolog` `-nojournal` `-mode` `batch` `-source`
`['tool', 'vivado', 'task', 'syn_fpga', 'input']`	`<design>.v`
`['tool', 'vivado', 'task', 'syn_fpga', 'output']`	`<design>_checkpoint.dcp`
`['tool', 'vivado', 'task', 'syn_fpga', 'refdir']`	`tools/vivado/scripts`
`['tool', 'vivado', 'task', 'syn_fpga', 'script']`	`sc_run.tcl`
`['tool', 'vivado', 'task', 'syn_fpga', 'threads']`	`2`

3.19. vpr#

VPR (Versatile Place and Route) is an open source CAD tool designed for the exploration of new FPGA architectures and CAD algorithms, at the packing, placement and routing phases of the CAD flow. VPR takes, as input, a description of an FPGA architecture along with a technology-mapped user circuit. It then performs packing, placement, and routing to map the circuit onto the FPGA. The output of VPR includes the FPGA configuration needed to implement the circuit and statistics about the final mapped design (eg. critical path delay, area, etc).

Documentation: https://docs.verilogtorouting.org/en/latest

Sources: https://github.com/verilog-to-routing/vtr-verilog-to-routing

Installation: https://github.com/verilog-to-routing/vtr-verilog-to-routing

Setup file: vpr.py

Keypath	Value
`['tool', 'vpr', 'exe']`	`vpr`
`['tool', 'vpr', 'version']`	`0.0`

3.19.1. apr#

Perform automated place and route with VPR

Setup file: apr.py

3.19.1.1. Configuration#

3.20. xyce#

Xyce is a high performance SPICE-compatible circuit simulator capable capable of solving extremely large circuit problems by supporting large-scale parallel computing platforms. It also supports serial execution on all common desktop platforms, and small-scale parallel runs on Unix-like systems.

Documentation: https://xyce.sandia.gov/documentation-tutorials/

Sources: https://github.com/Xyce/Xyce

Installation: https://xyce.sandia.gov/documentation-tutorials/building-guide/

Status: SC integration WIP

Setup file: xyce.py

Keypath	Value
`['tool', 'xyce', 'exe']`	`xyce`
`['tool', 'xyce', 'version']`	`0.0`

3.21. yosys#

Yosys is a framework for RTL synthesis that takes synthesizable Verilog-2005 design and converts it to BLIF, EDIF, BTOR, SMT, Verilog netlist etc. The tool supports logical synthesis and tech mapping to ASIC standard cell libraries, FPGA architectures. In addition it has built in formal methods for property and equivalence checking.

Documentation: https://yosyshq.readthedocs.io/projects/yosys/en/latest/

Sources: https://github.com/YosysHQ/yosys

Installation: https://github.com/YosysHQ/yosys

Setup file: yosys.py

Keypath	Value
`['tool', 'yosys', 'exe']`	`yosys`
`['tool', 'yosys', 'vswitch']`	`--version`
`['tool', 'yosys', 'version']`	`>=0.27`
`['tool', 'yosys', 'format']`	`tcl`

3.21.1. lec#

Perform logical equivalence checks

Setup file: lec.py

Built using target: asap7_demo

3.21.1.1. Configuration#

Keypath	Value
`['tool', 'yosys', 'task', 'lec', 'regex', 'warnings']`	`Warning:`
`['tool', 'yosys', 'task', 'lec', 'regex', 'errors']`	`^ERROR`
`['tool', 'yosys', 'task', 'lec', 'option']`	`-c`
`['tool', 'yosys', 'task', 'lec', 'var', 'flatten']`	`True`
`['tool', 'yosys', 'task', 'lec', 'var', 'autoname']`	`True`
`['tool', 'yosys', 'task', 'lec', 'var', 'add_buffers']`	`True`
`['tool', 'yosys', 'task', 'lec', 'var', 'map_adders']`	`False`
`['tool', 'yosys', 'task', 'lec', 'var', 'synthesis_corner']`	`slow`
`['tool', 'yosys', 'task', 'lec', 'var', 'abc_constraint_driver']`	`BUFx2_ASAP7_75t_R`
`['tool', 'yosys', 'task', 'lec', 'input']`	`<design>.vg`
`['tool', 'yosys', 'task', 'lec', 'require']`	`asic,logiclib` `library,asap7sc7p5t_rvt,output,slow,nldm` `tool,yosys,task,lec,var,flatten` `tool,yosys,task,lec,var,autoname` `tool,yosys,task,lec,var,add_buffers` `tool,yosys,task,lec,var,map_adders` `library,asap7sc7p5t_rvt,option,var,yosys_buffer_input` `library,asap7sc7p5t_rvt,option,var,yosys_buffer_output` `library,asap7sc7p5t_rvt,option,var,yosys_tiehigh_port` `library,asap7sc7p5t_rvt,option,var,yosys_tiehigh_cell` `library,asap7sc7p5t_rvt,option,var,yosys_tiehigh_port` `library,asap7sc7p5t_rvt,option,var,yosys_tiehigh_cell` `tool,yosys,task,lec,var,synthesis_corner`
`['tool', 'yosys', 'task', 'lec', 'refdir']`	`tools/yosys`
`['tool', 'yosys', 'task', 'lec', 'script']`	`sc_lec.tcl`

3.21.1.2. Variables#

Parameters	Help
`[..., 'var', 'flatten']`	True/False, invoke synth with the -flatten option
`[..., 'var', 'autoname']`	True/False, call autoname to rename wires based on registers
`[..., 'var', 'add_buffers']`	True/False, flag to indicate whether to add buffers or not.
`[..., 'var', 'map_adders']`	False/path to map_adders, techmap adders in Yosys
`[..., 'var', 'synthesis_corner']`	Timing corner to use for synthesis
`[..., 'var', 'abc_constraint_driver']`	Buffer that drives the abc techmapping, defaults to first buffer specified
`[..., 'var', 'preserve_modules']`	List of modules in input files to prevent flatten from “flattening”
`[..., 'var', 'abc_constraint_load']`	Capacitive load for the abc techmapping in fF, if not specified it will not be used
`[..., 'var', 'abc_clock_period']`	Clock period to use for synthesis in ps, if more than one clock is specified, the smallest period is used.
`[..., 'var', 'abc_clock_derating']`	Used to derate the clock period to further constrain the clock, values between 0 and 1

3.21.1.3. Files#

Parameters	Help
`[..., 'file', 'dff_liberty']`	Liberty file to use for flip-flop mapping, if not specified the first in the logiclib is used
`[..., 'file', 'abc_constraint_file']`	File used to pass in contraints to abc
`[..., 'file', 'techmap']`	File to use for techmapping in Yosys
`[..., 'file', 'dff_liberty_file']`	File to use for the DFF mapping stage of Yosys

3.21.2. syn_asic#

Perform ASIC synthesis

Setup file: syn_asic.py

Built using target: asap7_demo

3.21.2.1. Configuration#

Keypath	Value
`['tool', 'yosys', 'task', 'syn_asic', 'regex', 'warnings']`	`Warning:`
`['tool', 'yosys', 'task', 'syn_asic', 'regex', 'errors']`	`^ERROR`
`['tool', 'yosys', 'task', 'syn_asic', 'option']`	`-c`
`['tool', 'yosys', 'task', 'syn_asic', 'var', 'flatten']`	`True`
`['tool', 'yosys', 'task', 'syn_asic', 'var', 'autoname']`	`True`
`['tool', 'yosys', 'task', 'syn_asic', 'var', 'add_buffers']`	`True`
`['tool', 'yosys', 'task', 'syn_asic', 'var', 'map_adders']`	`False`
`['tool', 'yosys', 'task', 'syn_asic', 'var', 'synthesis_corner']`	`slow`
`['tool', 'yosys', 'task', 'syn_asic', 'var', 'abc_constraint_driver']`	`BUFx2_ASAP7_75t_R`
`['tool', 'yosys', 'task', 'syn_asic', 'input']`	`<design>.v`
`['tool', 'yosys', 'task', 'syn_asic', 'output']`	`<design>.vg`
`['tool', 'yosys', 'task', 'syn_asic', 'require']`	`asic,logiclib` `library,asap7sc7p5t_rvt,output,slow,nldm` `tool,yosys,task,syn_asic,var,flatten` `tool,yosys,task,syn_asic,var,autoname` `tool,yosys,task,syn_asic,var,add_buffers` `tool,yosys,task,syn_asic,var,map_adders` `library,asap7sc7p5t_rvt,option,var,yosys_buffer_input` `library,asap7sc7p5t_rvt,option,var,yosys_buffer_output` `library,asap7sc7p5t_rvt,option,var,yosys_tiehigh_port` `library,asap7sc7p5t_rvt,option,var,yosys_tiehigh_cell` `library,asap7sc7p5t_rvt,option,var,yosys_tiehigh_port` `library,asap7sc7p5t_rvt,option,var,yosys_tiehigh_cell` `tool,yosys,task,syn_asic,var,synthesis_corner`
`['tool', 'yosys', 'task', 'syn_asic', 'refdir']`	`tools/yosys`
`['tool', 'yosys', 'task', 'syn_asic', 'script']`	`sc_syn.tcl`

3.21.2.2. Variables#

Parameters	Help
`[..., 'var', 'flatten']`	True/False, invoke synth with the -flatten option
`[..., 'var', 'autoname']`	True/False, call autoname to rename wires based on registers
`[..., 'var', 'add_buffers']`	True/False, flag to indicate whether to add buffers or not.
`[..., 'var', 'map_adders']`	False/path to map_adders, techmap adders in Yosys
`[..., 'var', 'synthesis_corner']`	Timing corner to use for synthesis
`[..., 'var', 'abc_constraint_driver']`	Buffer that drives the abc techmapping, defaults to first buffer specified
`[..., 'var', 'preserve_modules']`	List of modules in input files to prevent flatten from “flattening”
`[..., 'var', 'abc_constraint_load']`	Capacitive load for the abc techmapping in fF, if not specified it will not be used
`[..., 'var', 'abc_clock_period']`	Clock period to use for synthesis in ps, if more than one clock is specified, the smallest period is used.
`[..., 'var', 'abc_clock_derating']`	Used to derate the clock period to further constrain the clock, values between 0 and 1

3.21.2.3. Files#

Parameters	Help
`[..., 'file', 'dff_liberty']`	Liberty file to use for flip-flop mapping, if not specified the first in the logiclib is used
`[..., 'file', 'abc_constraint_file']`	File used to pass in contraints to abc
`[..., 'file', 'techmap']`	File to use for techmapping in Yosys
`[..., 'file', 'dff_liberty_file']`	File to use for the DFF mapping stage of Yosys

3.21.3. syn_fpga#

Perform FPGA synthesis

Setup file: syn_fpga.py

Built using target: fpgaflow_demo

3.21.3.1. Configuration#

Keypath	Value
`['tool', 'yosys', 'task', 'syn_fpga', 'regex', 'warnings']`	`Warning:`
`['tool', 'yosys', 'task', 'syn_fpga', 'regex', 'errors']`	`^ERROR`
`['tool', 'yosys', 'task', 'syn_fpga', 'option']`	`-c`
`['tool', 'yosys', 'task', 'syn_fpga', 'input']`	`<design>.v`
`['tool', 'yosys', 'task', 'syn_fpga', 'output']`	`<design>.vg` `<design>_netlist.json` `<design>.blif`
`['tool', 'yosys', 'task', 'syn_fpga', 'require']`	`fpga,partname`
`['tool', 'yosys', 'task', 'syn_fpga', 'refdir']`	`tools/yosys`
`['tool', 'yosys', 'task', 'syn_fpga', 'script']`	`sc_syn.tcl`