2. Pre-Defined Flows

The following are examples are pre-built flows that come with SiliconCompiler which you can use for your own builds.

See the pre-built targets for examples on how these are used in conjunction with pdks, tools and libraries.

2.1. ASIC Flows

Complete ASIC compilation flows that take RTL through synthesis, place-and-route, and finishing. The language argument selects the front-end used to bring the design into Verilog before the shared place-and-route back-end runs; a variant is shown below for each supported source language.

2.1.1. asicflow-verilog / 0

A configurable ASIC compilation flow.

This flow targets ASIC designs, taking RTL through a complete synthesis, place-and-route, and finishing flow.

The flow is divided into the following major steps:

• elaborate: RTL elaboration using Slang.

• synthesis: RTL synthesis using Yosys.

• floorplan: Floorplanning, including macro placement, tapcell/endcap insertion, power grid generation, and pin placement.

• place: Global and detailed placement.

• cts: Clock tree synthesis and post-CTS timing repair.

• route: Global and detailed routing.

• dfm: Design-for-manufacturing steps, primarily metal fill.

• write: Writing out final views of the design (GDSII, etc.).

The synthesis, floorplan, place, cts, and route steps support parallel execution to explore different strategies. This can be configured by setting the corresponding *_np argument to a value greater than 1.

Args:

• name (str, optional): The name of the flow. If not provided, it defaults to ‘asicflow-<language>’.

• language (str): The hardware description language of the design. One of ‘verilog’, ‘systemverilog’, ‘systemverilog-sv2v’, ‘chisel’, ‘vhdl’, or ‘hls’.

• syn_np (int): Number of parallel synthesis jobs to launch.

• floorplan_np (int): Number of parallel floorplan jobs to launch.

• place_np (int): Number of parallel placement jobs to launch.

• cts_np (int): Number of parallel clock tree synthesis jobs to launch.

• route_np (int): Number of parallel routing jobs to launch.

File: asicflow.py

2.1.1.1. Graph

2.1.1.2. Nodes

2.1.1.2.1. elaborate/0

Keypath	Type	Value
[flowgraph,asicflow-verilog,elaborate,0,task]	str	elaborate
[flowgraph,asicflow-verilog,elaborate,0,taskmodule]	str	siliconcompiler.tools.slang.elaborate/Elaborate
[flowgraph,asicflow-verilog,elaborate,0,tool]	str	slang

2.1.1.2.2. synthesis/0

Keypath	Type	Value
[flowgraph,asicflow-verilog,synthesis,0,goal,errors]	float	0.0
[flowgraph,asicflow-verilog,synthesis,0,input]	[(str,str)]	('elaborate', '0')
[flowgraph,asicflow-verilog,synthesis,0,task]	str	syn_asic
[flowgraph,asicflow-verilog,synthesis,0,taskmodule]	str	siliconcompiler.tools.yosys.syn_asic/ASICSynthesis
[flowgraph,asicflow-verilog,synthesis,0,tool]	str	yosys

2.1.1.2.3. synthesis/1

Keypath	Type	Value
[flowgraph,asicflow-verilog,synthesis,1,goal,errors]	float	0.0
[flowgraph,asicflow-verilog,synthesis,1,input]	[(str,str)]	('elaborate', '0')
[flowgraph,asicflow-verilog,synthesis,1,task]	str	syn_asic
[flowgraph,asicflow-verilog,synthesis,1,taskmodule]	str	siliconcompiler.tools.yosys.syn_asic/ASICSynthesis
[flowgraph,asicflow-verilog,synthesis,1,tool]	str	yosys

2.1.1.2.4. synthesis/2

Keypath	Type	Value
[flowgraph,asicflow-verilog,synthesis,2,goal,errors]	float	0.0
[flowgraph,asicflow-verilog,synthesis,2,input]	[(str,str)]	('elaborate', '0')
[flowgraph,asicflow-verilog,synthesis,2,task]	str	syn_asic
[flowgraph,asicflow-verilog,synthesis,2,taskmodule]	str	siliconcompiler.tools.yosys.syn_asic/ASICSynthesis
[flowgraph,asicflow-verilog,synthesis,2,tool]	str	yosys

2.1.1.2.5. synthesis.min/0

Keypath	Type	Value
[flowgraph,asicflow-verilog,synthesis.min,0,input]	[(str,str)]	('synthesis', '0') ('synthesis', '1') ('synthesis', '2')
[flowgraph,asicflow-verilog,synthesis.min,0,task]	str	minimum
[flowgraph,asicflow-verilog,synthesis.min,0,taskmodule]	str	siliconcompiler.tools.builtin.minimum/MinimumTask
[flowgraph,asicflow-verilog,synthesis.min,0,tool]	str	builtin

2.1.1.2.6. cleanup.clean/0

Keypath	Type	Value
[flowgraph,asicflow-verilog,cleanup.clean,0,input]	[(str,str)]	('synthesis.min', '0')
[flowgraph,asicflow-verilog,cleanup.clean,0,task]	str	cleanup_synth
[flowgraph,asicflow-verilog,cleanup.clean,0,taskmodule]	str	siliconcompiler.tools.openroad.synth_cleanup/CleanupSynthTask
[flowgraph,asicflow-verilog,cleanup.clean,0,tool]	str	openroad

2.1.1.2.7. synthesis.timing/0

Keypath	Type	Value
[flowgraph,asicflow-verilog,synthesis.timing,0,input]	[(str,str)]	('synthesis.min', '0')
[flowgraph,asicflow-verilog,synthesis.timing,0,task]	str	timing
[flowgraph,asicflow-verilog,synthesis.timing,0,taskmodule]	str	siliconcompiler.tools.opensta.timing/TimingTask
[flowgraph,asicflow-verilog,synthesis.timing,0,tool]	str	opensta

2.1.1.2.8. floorplan.init/0

Keypath	Type	Value
[flowgraph,asicflow-verilog,floorplan.init,0,input]	[(str,str)]	('cleanup.clean', '0')
[flowgraph,asicflow-verilog,floorplan.init,0,task]	str	init_floorplan
[flowgraph,asicflow-verilog,floorplan.init,0,taskmodule]	str	siliconcompiler.tools.openroad.init_floorplan/InitFloorplanTask
[flowgraph,asicflow-verilog,floorplan.init,0,tool]	str	openroad

2.1.1.2.9. floorplan.init/1

Keypath	Type	Value
[flowgraph,asicflow-verilog,floorplan.init,1,input]	[(str,str)]	('cleanup.clean', '0')
[flowgraph,asicflow-verilog,floorplan.init,1,task]	str	init_floorplan
[flowgraph,asicflow-verilog,floorplan.init,1,taskmodule]	str	siliconcompiler.tools.openroad.init_floorplan/InitFloorplanTask
[flowgraph,asicflow-verilog,floorplan.init,1,tool]	str	openroad

2.1.1.2.10. floorplan.init/2

Keypath	Type	Value
[flowgraph,asicflow-verilog,floorplan.init,2,input]	[(str,str)]	('cleanup.clean', '0')
[flowgraph,asicflow-verilog,floorplan.init,2,task]	str	init_floorplan
[flowgraph,asicflow-verilog,floorplan.init,2,taskmodule]	str	siliconcompiler.tools.openroad.init_floorplan/InitFloorplanTask
[flowgraph,asicflow-verilog,floorplan.init,2,tool]	str	openroad

2.1.1.2.11. floorplan.macro_placement/0

Keypath	Type	Value
[flowgraph,asicflow-verilog,floorplan.macro_placement,0,input]	[(str,str)]	('floorplan.init', '0')
[flowgraph,asicflow-verilog,floorplan.macro_placement,0,task]	str	macro_placement
[flowgraph,asicflow-verilog,floorplan.macro_placement,0,taskmodule]	str	siliconcompiler.tools.openroad.macro_placement/MacroPlacementTask
[flowgraph,asicflow-verilog,floorplan.macro_placement,0,tool]	str	openroad

2.1.1.2.12. floorplan.macro_placement/1

Keypath	Type	Value
[flowgraph,asicflow-verilog,floorplan.macro_placement,1,input]	[(str,str)]	('floorplan.init', '1')
[flowgraph,asicflow-verilog,floorplan.macro_placement,1,task]	str	macro_placement
[flowgraph,asicflow-verilog,floorplan.macro_placement,1,taskmodule]	str	siliconcompiler.tools.openroad.macro_placement/MacroPlacementTask
[flowgraph,asicflow-verilog,floorplan.macro_placement,1,tool]	str	openroad

2.1.1.2.13. floorplan.macro_placement/2

Keypath	Type	Value
[flowgraph,asicflow-verilog,floorplan.macro_placement,2,input]	[(str,str)]	('floorplan.init', '2')
[flowgraph,asicflow-verilog,floorplan.macro_placement,2,task]	str	macro_placement
[flowgraph,asicflow-verilog,floorplan.macro_placement,2,taskmodule]	str	siliconcompiler.tools.openroad.macro_placement/MacroPlacementTask
[flowgraph,asicflow-verilog,floorplan.macro_placement,2,tool]	str	openroad

2.1.1.2.14. floorplan.tapcell/0

Keypath	Type	Value
[flowgraph,asicflow-verilog,floorplan.tapcell,0,input]	[(str,str)]	('floorplan.macro_placement', '0')
[flowgraph,asicflow-verilog,floorplan.tapcell,0,task]	str	endcap_tapcell_insertion
[flowgraph,asicflow-verilog,floorplan.tapcell,0,taskmodule]	str	siliconcompiler.tools.openroad.endcap_tapcell_insertion/EndCapTapCellTask
[flowgraph,asicflow-verilog,floorplan.tapcell,0,tool]	str	openroad

2.1.1.2.15. floorplan.tapcell/1

Keypath	Type	Value
[flowgraph,asicflow-verilog,floorplan.tapcell,1,input]	[(str,str)]	('floorplan.macro_placement', '1')
[flowgraph,asicflow-verilog,floorplan.tapcell,1,task]	str	endcap_tapcell_insertion
[flowgraph,asicflow-verilog,floorplan.tapcell,1,taskmodule]	str	siliconcompiler.tools.openroad.endcap_tapcell_insertion/EndCapTapCellTask
[flowgraph,asicflow-verilog,floorplan.tapcell,1,tool]	str	openroad

2.1.1.2.16. floorplan.tapcell/2

Keypath	Type	Value
[flowgraph,asicflow-verilog,floorplan.tapcell,2,input]	[(str,str)]	('floorplan.macro_placement', '2')
[flowgraph,asicflow-verilog,floorplan.tapcell,2,task]	str	endcap_tapcell_insertion
[flowgraph,asicflow-verilog,floorplan.tapcell,2,taskmodule]	str	siliconcompiler.tools.openroad.endcap_tapcell_insertion/EndCapTapCellTask
[flowgraph,asicflow-verilog,floorplan.tapcell,2,tool]	str	openroad

2.1.1.2.17. floorplan.power_grid/0

Keypath	Type	Value
[flowgraph,asicflow-verilog,floorplan.power_grid,0,input]	[(str,str)]	('floorplan.tapcell', '0')
[flowgraph,asicflow-verilog,floorplan.power_grid,0,task]	str	power_grid
[flowgraph,asicflow-verilog,floorplan.power_grid,0,taskmodule]	str	siliconcompiler.tools.openroad.power_grid/PowerGridTask
[flowgraph,asicflow-verilog,floorplan.power_grid,0,tool]	str	openroad

2.1.1.2.18. floorplan.power_grid/1

Keypath	Type	Value
[flowgraph,asicflow-verilog,floorplan.power_grid,1,input]	[(str,str)]	('floorplan.tapcell', '1')
[flowgraph,asicflow-verilog,floorplan.power_grid,1,task]	str	power_grid
[flowgraph,asicflow-verilog,floorplan.power_grid,1,taskmodule]	str	siliconcompiler.tools.openroad.power_grid/PowerGridTask
[flowgraph,asicflow-verilog,floorplan.power_grid,1,tool]	str	openroad

2.1.1.2.19. floorplan.power_grid/2

Keypath	Type	Value
[flowgraph,asicflow-verilog,floorplan.power_grid,2,input]	[(str,str)]	('floorplan.tapcell', '2')
[flowgraph,asicflow-verilog,floorplan.power_grid,2,task]	str	power_grid
[flowgraph,asicflow-verilog,floorplan.power_grid,2,taskmodule]	str	siliconcompiler.tools.openroad.power_grid/PowerGridTask
[flowgraph,asicflow-verilog,floorplan.power_grid,2,tool]	str	openroad

2.1.1.2.20. floorplan.pin_placement/0

Keypath	Type	Value
[flowgraph,asicflow-verilog,floorplan.pin_placement,0,input]	[(str,str)]	('floorplan.power_grid', '0')
[flowgraph,asicflow-verilog,floorplan.pin_placement,0,task]	str	pin_placement
[flowgraph,asicflow-verilog,floorplan.pin_placement,0,taskmodule]	str	siliconcompiler.tools.openroad.pin_placement/PinPlacementTask
[flowgraph,asicflow-verilog,floorplan.pin_placement,0,tool]	str	openroad

2.1.1.2.21. floorplan.pin_placement/1

Keypath	Type	Value
[flowgraph,asicflow-verilog,floorplan.pin_placement,1,input]	[(str,str)]	('floorplan.power_grid', '1')
[flowgraph,asicflow-verilog,floorplan.pin_placement,1,task]	str	pin_placement
[flowgraph,asicflow-verilog,floorplan.pin_placement,1,taskmodule]	str	siliconcompiler.tools.openroad.pin_placement/PinPlacementTask
[flowgraph,asicflow-verilog,floorplan.pin_placement,1,tool]	str	openroad

2.1.1.2.22. floorplan.pin_placement/2

Keypath	Type	Value
[flowgraph,asicflow-verilog,floorplan.pin_placement,2,input]	[(str,str)]	('floorplan.power_grid', '2')
[flowgraph,asicflow-verilog,floorplan.pin_placement,2,task]	str	pin_placement
[flowgraph,asicflow-verilog,floorplan.pin_placement,2,taskmodule]	str	siliconcompiler.tools.openroad.pin_placement/PinPlacementTask
[flowgraph,asicflow-verilog,floorplan.pin_placement,2,tool]	str	openroad

2.1.1.2.23. floorplan.min/0

Keypath	Type	Value
[flowgraph,asicflow-verilog,floorplan.min,0,input]	[(str,str)]	('floorplan.pin_placement', '0') ('floorplan.pin_placement', '1') ('floorplan.pin_placement', '2')
[flowgraph,asicflow-verilog,floorplan.min,0,task]	str	minimum
[flowgraph,asicflow-verilog,floorplan.min,0,taskmodule]	str	siliconcompiler.tools.builtin.minimum/MinimumTask
[flowgraph,asicflow-verilog,floorplan.min,0,tool]	str	builtin

2.1.1.2.24. place.global/0

Keypath	Type	Value
[flowgraph,asicflow-verilog,place.global,0,input]	[(str,str)]	('floorplan.min', '0')
[flowgraph,asicflow-verilog,place.global,0,task]	str	global_placement
[flowgraph,asicflow-verilog,place.global,0,taskmodule]	str	siliconcompiler.tools.openroad.global_placement/GlobalPlacementTask
[flowgraph,asicflow-verilog,place.global,0,tool]	str	openroad

2.1.1.2.25. place.global/1

Keypath	Type	Value
[flowgraph,asicflow-verilog,place.global,1,input]	[(str,str)]	('floorplan.min', '0')
[flowgraph,asicflow-verilog,place.global,1,task]	str	global_placement
[flowgraph,asicflow-verilog,place.global,1,taskmodule]	str	siliconcompiler.tools.openroad.global_placement/GlobalPlacementTask
[flowgraph,asicflow-verilog,place.global,1,tool]	str	openroad

2.1.1.2.26. place.global/2

Keypath	Type	Value
[flowgraph,asicflow-verilog,place.global,2,input]	[(str,str)]	('floorplan.min', '0')
[flowgraph,asicflow-verilog,place.global,2,task]	str	global_placement
[flowgraph,asicflow-verilog,place.global,2,taskmodule]	str	siliconcompiler.tools.openroad.global_placement/GlobalPlacementTask
[flowgraph,asicflow-verilog,place.global,2,tool]	str	openroad

2.1.1.2.27. place.repair_design/0

Keypath	Type	Value
[flowgraph,asicflow-verilog,place.repair_design,0,input]	[(str,str)]	('place.global', '0')
[flowgraph,asicflow-verilog,place.repair_design,0,task]	str	repair_design
[flowgraph,asicflow-verilog,place.repair_design,0,taskmodule]	str	siliconcompiler.tools.openroad.repair_design/RepairDesignTask
[flowgraph,asicflow-verilog,place.repair_design,0,tool]	str	openroad

2.1.1.2.28. place.repair_design/1

Keypath	Type	Value
[flowgraph,asicflow-verilog,place.repair_design,1,input]	[(str,str)]	('place.global', '1')
[flowgraph,asicflow-verilog,place.repair_design,1,task]	str	repair_design
[flowgraph,asicflow-verilog,place.repair_design,1,taskmodule]	str	siliconcompiler.tools.openroad.repair_design/RepairDesignTask
[flowgraph,asicflow-verilog,place.repair_design,1,tool]	str	openroad

2.1.1.2.29. place.repair_design/2

Keypath	Type	Value
[flowgraph,asicflow-verilog,place.repair_design,2,input]	[(str,str)]	('place.global', '2')
[flowgraph,asicflow-verilog,place.repair_design,2,task]	str	repair_design
[flowgraph,asicflow-verilog,place.repair_design,2,taskmodule]	str	siliconcompiler.tools.openroad.repair_design/RepairDesignTask
[flowgraph,asicflow-verilog,place.repair_design,2,tool]	str	openroad

2.1.1.2.30. place.detailed/0

Keypath	Type	Value
[flowgraph,asicflow-verilog,place.detailed,0,input]	[(str,str)]	('place.repair_design', '0')
[flowgraph,asicflow-verilog,place.detailed,0,task]	str	detailed_placement
[flowgraph,asicflow-verilog,place.detailed,0,taskmodule]	str	siliconcompiler.tools.openroad.detailed_placement/DetailedPlacementTask
[flowgraph,asicflow-verilog,place.detailed,0,tool]	str	openroad

2.1.1.2.31. place.detailed/1

Keypath	Type	Value
[flowgraph,asicflow-verilog,place.detailed,1,input]	[(str,str)]	('place.repair_design', '1')
[flowgraph,asicflow-verilog,place.detailed,1,task]	str	detailed_placement
[flowgraph,asicflow-verilog,place.detailed,1,taskmodule]	str	siliconcompiler.tools.openroad.detailed_placement/DetailedPlacementTask
[flowgraph,asicflow-verilog,place.detailed,1,tool]	str	openroad

2.1.1.2.32. place.detailed/2

Keypath	Type	Value
[flowgraph,asicflow-verilog,place.detailed,2,input]	[(str,str)]	('place.repair_design', '2')
[flowgraph,asicflow-verilog,place.detailed,2,task]	str	detailed_placement
[flowgraph,asicflow-verilog,place.detailed,2,taskmodule]	str	siliconcompiler.tools.openroad.detailed_placement/DetailedPlacementTask
[flowgraph,asicflow-verilog,place.detailed,2,tool]	str	openroad

2.1.1.2.33. place.min/0

Keypath	Type	Value
[flowgraph,asicflow-verilog,place.min,0,input]	[(str,str)]	('place.detailed', '0') ('place.detailed', '1') ('place.detailed', '2')
[flowgraph,asicflow-verilog,place.min,0,task]	str	minimum
[flowgraph,asicflow-verilog,place.min,0,taskmodule]	str	siliconcompiler.tools.builtin.minimum/MinimumTask
[flowgraph,asicflow-verilog,place.min,0,tool]	str	builtin

2.1.1.2.34. cts.clock_tree_synthesis/0

Keypath	Type	Value
[flowgraph,asicflow-verilog,cts.clock_tree_synthesis,0,input]	[(str,str)]	('place.min', '0')
[flowgraph,asicflow-verilog,cts.clock_tree_synthesis,0,task]	str	clock_tree_synthesis
[flowgraph,asicflow-verilog,cts.clock_tree_synthesis,0,taskmodule]	str	siliconcompiler.tools.openroad.clock_tree_synthesis/CTSTask
[flowgraph,asicflow-verilog,cts.clock_tree_synthesis,0,tool]	str	openroad

2.1.1.2.35. cts.clock_tree_synthesis/1

Keypath	Type	Value
[flowgraph,asicflow-verilog,cts.clock_tree_synthesis,1,input]	[(str,str)]	('place.min', '0')
[flowgraph,asicflow-verilog,cts.clock_tree_synthesis,1,task]	str	clock_tree_synthesis
[flowgraph,asicflow-verilog,cts.clock_tree_synthesis,1,taskmodule]	str	siliconcompiler.tools.openroad.clock_tree_synthesis/CTSTask
[flowgraph,asicflow-verilog,cts.clock_tree_synthesis,1,tool]	str	openroad

2.1.1.2.36. cts.clock_tree_synthesis/2

Keypath	Type	Value
[flowgraph,asicflow-verilog,cts.clock_tree_synthesis,2,input]	[(str,str)]	('place.min', '0')
[flowgraph,asicflow-verilog,cts.clock_tree_synthesis,2,task]	str	clock_tree_synthesis
[flowgraph,asicflow-verilog,cts.clock_tree_synthesis,2,taskmodule]	str	siliconcompiler.tools.openroad.clock_tree_synthesis/CTSTask
[flowgraph,asicflow-verilog,cts.clock_tree_synthesis,2,tool]	str	openroad

2.1.1.2.37. cts.repair_timing/0

Keypath	Type	Value
[flowgraph,asicflow-verilog,cts.repair_timing,0,input]	[(str,str)]	('cts.clock_tree_synthesis', '0')
[flowgraph,asicflow-verilog,cts.repair_timing,0,task]	str	repair_timing
[flowgraph,asicflow-verilog,cts.repair_timing,0,taskmodule]	str	siliconcompiler.tools.openroad.repair_timing/RepairTimingTask
[flowgraph,asicflow-verilog,cts.repair_timing,0,tool]	str	openroad

2.1.1.2.38. cts.repair_timing/1

Keypath	Type	Value
[flowgraph,asicflow-verilog,cts.repair_timing,1,input]	[(str,str)]	('cts.clock_tree_synthesis', '1')
[flowgraph,asicflow-verilog,cts.repair_timing,1,task]	str	repair_timing
[flowgraph,asicflow-verilog,cts.repair_timing,1,taskmodule]	str	siliconcompiler.tools.openroad.repair_timing/RepairTimingTask
[flowgraph,asicflow-verilog,cts.repair_timing,1,tool]	str	openroad

2.1.1.2.39. cts.repair_timing/2

Keypath	Type	Value
[flowgraph,asicflow-verilog,cts.repair_timing,2,input]	[(str,str)]	('cts.clock_tree_synthesis', '2')
[flowgraph,asicflow-verilog,cts.repair_timing,2,task]	str	repair_timing
[flowgraph,asicflow-verilog,cts.repair_timing,2,taskmodule]	str	siliconcompiler.tools.openroad.repair_timing/RepairTimingTask
[flowgraph,asicflow-verilog,cts.repair_timing,2,tool]	str	openroad

2.1.1.2.40. cts.min/0

Keypath	Type	Value
[flowgraph,asicflow-verilog,cts.min,0,input]	[(str,str)]	('cts.repair_timing', '0') ('cts.repair_timing', '1') ('cts.repair_timing', '2')
[flowgraph,asicflow-verilog,cts.min,0,task]	str	minimum
[flowgraph,asicflow-verilog,cts.min,0,taskmodule]	str	siliconcompiler.tools.builtin.minimum/MinimumTask
[flowgraph,asicflow-verilog,cts.min,0,tool]	str	builtin

2.1.1.2.41. cts.fillcell/0

Keypath	Type	Value
[flowgraph,asicflow-verilog,cts.fillcell,0,input]	[(str,str)]	('cts.min', '0')
[flowgraph,asicflow-verilog,cts.fillcell,0,task]	str	fillercell_insertion
[flowgraph,asicflow-verilog,cts.fillcell,0,taskmodule]	str	siliconcompiler.tools.openroad.fillercell_insertion/FillCellTask
[flowgraph,asicflow-verilog,cts.fillcell,0,tool]	str	openroad

2.1.1.2.42. route.global/0

Keypath	Type	Value
[flowgraph,asicflow-verilog,route.global,0,input]	[(str,str)]	('cts.fillcell', '0')
[flowgraph,asicflow-verilog,route.global,0,task]	str	global_route
[flowgraph,asicflow-verilog,route.global,0,taskmodule]	str	siliconcompiler.tools.openroad.global_route/GlobalRouteTask
[flowgraph,asicflow-verilog,route.global,0,tool]	str	openroad

2.1.1.2.43. route.global/1

Keypath	Type	Value
[flowgraph,asicflow-verilog,route.global,1,input]	[(str,str)]	('cts.fillcell', '0')
[flowgraph,asicflow-verilog,route.global,1,task]	str	global_route
[flowgraph,asicflow-verilog,route.global,1,taskmodule]	str	siliconcompiler.tools.openroad.global_route/GlobalRouteTask
[flowgraph,asicflow-verilog,route.global,1,tool]	str	openroad

2.1.1.2.44. route.global/2

Keypath	Type	Value
[flowgraph,asicflow-verilog,route.global,2,input]	[(str,str)]	('cts.fillcell', '0')
[flowgraph,asicflow-verilog,route.global,2,task]	str	global_route
[flowgraph,asicflow-verilog,route.global,2,taskmodule]	str	siliconcompiler.tools.openroad.global_route/GlobalRouteTask
[flowgraph,asicflow-verilog,route.global,2,tool]	str	openroad

2.1.1.2.45. route.antenna_repair/0

Keypath	Type	Value
[flowgraph,asicflow-verilog,route.antenna_repair,0,input]	[(str,str)]	('route.global', '0')
[flowgraph,asicflow-verilog,route.antenna_repair,0,task]	str	antenna_repair
[flowgraph,asicflow-verilog,route.antenna_repair,0,taskmodule]	str	siliconcompiler.tools.openroad.antenna_repair/AntennaRepairTask
[flowgraph,asicflow-verilog,route.antenna_repair,0,tool]	str	openroad

2.1.1.2.46. route.antenna_repair/1

Keypath	Type	Value
[flowgraph,asicflow-verilog,route.antenna_repair,1,input]	[(str,str)]	('route.global', '1')
[flowgraph,asicflow-verilog,route.antenna_repair,1,task]	str	antenna_repair
[flowgraph,asicflow-verilog,route.antenna_repair,1,taskmodule]	str	siliconcompiler.tools.openroad.antenna_repair/AntennaRepairTask
[flowgraph,asicflow-verilog,route.antenna_repair,1,tool]	str	openroad

2.1.1.2.47. route.antenna_repair/2

Keypath	Type	Value
[flowgraph,asicflow-verilog,route.antenna_repair,2,input]	[(str,str)]	('route.global', '2')
[flowgraph,asicflow-verilog,route.antenna_repair,2,task]	str	antenna_repair
[flowgraph,asicflow-verilog,route.antenna_repair,2,taskmodule]	str	siliconcompiler.tools.openroad.antenna_repair/AntennaRepairTask
[flowgraph,asicflow-verilog,route.antenna_repair,2,tool]	str	openroad

2.1.1.2.48. route.detailed/0

Keypath	Type	Value
[flowgraph,asicflow-verilog,route.detailed,0,input]	[(str,str)]	('route.antenna_repair', '0')
[flowgraph,asicflow-verilog,route.detailed,0,task]	str	detailed_route
[flowgraph,asicflow-verilog,route.detailed,0,taskmodule]	str	siliconcompiler.tools.openroad.detailed_route/DetailedRouteTask
[flowgraph,asicflow-verilog,route.detailed,0,tool]	str	openroad

2.1.1.2.49. route.detailed/1

Keypath	Type	Value
[flowgraph,asicflow-verilog,route.detailed,1,input]	[(str,str)]	('route.antenna_repair', '1')
[flowgraph,asicflow-verilog,route.detailed,1,task]	str	detailed_route
[flowgraph,asicflow-verilog,route.detailed,1,taskmodule]	str	siliconcompiler.tools.openroad.detailed_route/DetailedRouteTask
[flowgraph,asicflow-verilog,route.detailed,1,tool]	str	openroad

2.1.1.2.50. route.detailed/2

Keypath	Type	Value
[flowgraph,asicflow-verilog,route.detailed,2,input]	[(str,str)]	('route.antenna_repair', '2')
[flowgraph,asicflow-verilog,route.detailed,2,task]	str	detailed_route
[flowgraph,asicflow-verilog,route.detailed,2,taskmodule]	str	siliconcompiler.tools.openroad.detailed_route/DetailedRouteTask
[flowgraph,asicflow-verilog,route.detailed,2,tool]	str	openroad

2.1.1.2.51. route.min/0

Keypath	Type	Value
[flowgraph,asicflow-verilog,route.min,0,input]	[(str,str)]	('route.detailed', '0') ('route.detailed', '1') ('route.detailed', '2')
[flowgraph,asicflow-verilog,route.min,0,task]	str	minimum
[flowgraph,asicflow-verilog,route.min,0,taskmodule]	str	siliconcompiler.tools.builtin.minimum/MinimumTask
[flowgraph,asicflow-verilog,route.min,0,tool]	str	builtin

2.1.1.2.52. dfm.metal_fill/0

Keypath	Type	Value
[flowgraph,asicflow-verilog,dfm.metal_fill,0,input]	[(str,str)]	('route.min', '0')
[flowgraph,asicflow-verilog,dfm.metal_fill,0,task]	str	fillmetal_insertion
[flowgraph,asicflow-verilog,dfm.metal_fill,0,taskmodule]	str	siliconcompiler.tools.openroad.fillmetal_insertion/FillMetalTask
[flowgraph,asicflow-verilog,dfm.metal_fill,0,tool]	str	openroad

2.1.1.2.53. write.gds/0

Keypath	Type	Value
[flowgraph,asicflow-verilog,write.gds,0,input]	[(str,str)]	('dfm.metal_fill', '0')
[flowgraph,asicflow-verilog,write.gds,0,task]	str	export
[flowgraph,asicflow-verilog,write.gds,0,taskmodule]	str	siliconcompiler.tools.klayout.export/ExportTask
[flowgraph,asicflow-verilog,write.gds,0,tool]	str	klayout

2.1.1.2.54. write.views/0

Keypath	Type	Value
[flowgraph,asicflow-verilog,write.views,0,input]	[(str,str)]	('dfm.metal_fill', '0')
[flowgraph,asicflow-verilog,write.views,0,task]	str	write_data
[flowgraph,asicflow-verilog,write.views,0,taskmodule]	str	siliconcompiler.tools.openroad.write_data/WriteViewsTask
[flowgraph,asicflow-verilog,write.views,0,tool]	str	openroad

2.1.2. asicflow-systemverilog-sv2v / 1

A configurable ASIC compilation flow.

This flow targets ASIC designs, taking RTL through a complete synthesis, place-and-route, and finishing flow.

The flow is divided into the following major steps:

• elaborate: RTL elaboration using Slang.

• synthesis: RTL synthesis using Yosys.

• floorplan: Floorplanning, including macro placement, tapcell/endcap insertion, power grid generation, and pin placement.

• place: Global and detailed placement.

• cts: Clock tree synthesis and post-CTS timing repair.

• route: Global and detailed routing.

• dfm: Design-for-manufacturing steps, primarily metal fill.

• write: Writing out final views of the design (GDSII, etc.).

The synthesis, floorplan, place, cts, and route steps support parallel execution to explore different strategies. This can be configured by setting the corresponding *_np argument to a value greater than 1.

Args:

• name (str, optional): The name of the flow. If not provided, it defaults to ‘asicflow-<language>’.

• language (str): The hardware description language of the design. One of ‘verilog’, ‘systemverilog’, ‘systemverilog-sv2v’, ‘chisel’, ‘vhdl’, or ‘hls’.

• syn_np (int): Number of parallel synthesis jobs to launch.

• floorplan_np (int): Number of parallel floorplan jobs to launch.

• place_np (int): Number of parallel placement jobs to launch.

• cts_np (int): Number of parallel clock tree synthesis jobs to launch.

• route_np (int): Number of parallel routing jobs to launch.

File: asicflow.py

2.1.2.1. Graph

2.1.2.2. Nodes

2.1.2.2.1. elaborate/0

Keypath	Type	Value
[flowgraph,asicflow-systemverilog-sv2v,elaborate,0,task]	str	elaborate
[flowgraph,asicflow-systemverilog-sv2v,elaborate,0,taskmodule]	str	siliconcompiler.tools.slang.elaborate/Elaborate
[flowgraph,asicflow-systemverilog-sv2v,elaborate,0,tool]	str	slang

2.1.2.2.2. convert/0

Keypath	Type	Value
[flowgraph,asicflow-systemverilog-sv2v,convert,0,input]	[(str,str)]	('elaborate', '0')
[flowgraph,asicflow-systemverilog-sv2v,convert,0,task]	str	convert
[flowgraph,asicflow-systemverilog-sv2v,convert,0,taskmodule]	str	siliconcompiler.tools.sv2v.convert/ConvertTask
[flowgraph,asicflow-systemverilog-sv2v,convert,0,tool]	str	sv2v

2.1.2.2.3. synthesis/0

Keypath	Type	Value
[flowgraph,asicflow-systemverilog-sv2v,synthesis,0,goal,errors]	float	0.0
[flowgraph,asicflow-systemverilog-sv2v,synthesis,0,input]	[(str,str)]	('convert', '0')
[flowgraph,asicflow-systemverilog-sv2v,synthesis,0,task]	str	syn_asic
[flowgraph,asicflow-systemverilog-sv2v,synthesis,0,taskmodule]	str	siliconcompiler.tools.yosys.syn_asic/ASICSynthesis
[flowgraph,asicflow-systemverilog-sv2v,synthesis,0,tool]	str	yosys

2.1.2.2.4. synthesis/1

Keypath	Type	Value
[flowgraph,asicflow-systemverilog-sv2v,synthesis,1,goal,errors]	float	0.0
[flowgraph,asicflow-systemverilog-sv2v,synthesis,1,input]	[(str,str)]	('convert', '0')
[flowgraph,asicflow-systemverilog-sv2v,synthesis,1,task]	str	syn_asic
[flowgraph,asicflow-systemverilog-sv2v,synthesis,1,taskmodule]	str	siliconcompiler.tools.yosys.syn_asic/ASICSynthesis
[flowgraph,asicflow-systemverilog-sv2v,synthesis,1,tool]	str	yosys

2.1.2.2.5. synthesis/2

Keypath	Type	Value
[flowgraph,asicflow-systemverilog-sv2v,synthesis,2,goal,errors]	float	0.0
[flowgraph,asicflow-systemverilog-sv2v,synthesis,2,input]	[(str,str)]	('convert', '0')
[flowgraph,asicflow-systemverilog-sv2v,synthesis,2,task]	str	syn_asic
[flowgraph,asicflow-systemverilog-sv2v,synthesis,2,taskmodule]	str	siliconcompiler.tools.yosys.syn_asic/ASICSynthesis
[flowgraph,asicflow-systemverilog-sv2v,synthesis,2,tool]	str	yosys

2.1.2.2.6. synthesis.min/0

Keypath	Type	Value
[flowgraph,asicflow-systemverilog-sv2v,synthesis.min,0,input]	[(str,str)]	('synthesis', '0') ('synthesis', '1') ('synthesis', '2')
[flowgraph,asicflow-systemverilog-sv2v,synthesis.min,0,task]	str	minimum
[flowgraph,asicflow-systemverilog-sv2v,synthesis.min,0,taskmodule]	str	siliconcompiler.tools.builtin.minimum/MinimumTask
[flowgraph,asicflow-systemverilog-sv2v,synthesis.min,0,tool]	str	builtin

2.1.2.2.7. cleanup.clean/0

Keypath	Type	Value
[flowgraph,asicflow-systemverilog-sv2v,cleanup.clean,0,input]	[(str,str)]	('synthesis.min', '0')
[flowgraph,asicflow-systemverilog-sv2v,cleanup.clean,0,task]	str	cleanup_synth
[flowgraph,asicflow-systemverilog-sv2v,cleanup.clean,0,taskmodule]	str	siliconcompiler.tools.openroad.synth_cleanup/CleanupSynthTask
[flowgraph,asicflow-systemverilog-sv2v,cleanup.clean,0,tool]	str	openroad

2.1.2.2.8. synthesis.timing/0

Keypath	Type	Value
[flowgraph,asicflow-systemverilog-sv2v,synthesis.timing,0,input]	[(str,str)]	('synthesis.min', '0')
[flowgraph,asicflow-systemverilog-sv2v,synthesis.timing,0,task]	str	timing
[flowgraph,asicflow-systemverilog-sv2v,synthesis.timing,0,taskmodule]	str	siliconcompiler.tools.opensta.timing/TimingTask
[flowgraph,asicflow-systemverilog-sv2v,synthesis.timing,0,tool]	str	opensta

2.1.2.2.9. floorplan.init/0

Keypath	Type	Value
[flowgraph,asicflow-systemverilog-sv2v,floorplan.init,0,input]	[(str,str)]	('cleanup.clean', '0')
[flowgraph,asicflow-systemverilog-sv2v,floorplan.init,0,task]	str	init_floorplan
[flowgraph,asicflow-systemverilog-sv2v,floorplan.init,0,taskmodule]	str	siliconcompiler.tools.openroad.init_floorplan/InitFloorplanTask
[flowgraph,asicflow-systemverilog-sv2v,floorplan.init,0,tool]	str	openroad

2.1.2.2.10. floorplan.init/1

Keypath	Type	Value
[flowgraph,asicflow-systemverilog-sv2v,floorplan.init,1,input]	[(str,str)]	('cleanup.clean', '0')
[flowgraph,asicflow-systemverilog-sv2v,floorplan.init,1,task]	str	init_floorplan
[flowgraph,asicflow-systemverilog-sv2v,floorplan.init,1,taskmodule]	str	siliconcompiler.tools.openroad.init_floorplan/InitFloorplanTask
[flowgraph,asicflow-systemverilog-sv2v,floorplan.init,1,tool]	str	openroad

2.1.2.2.11. floorplan.init/2

Keypath	Type	Value
[flowgraph,asicflow-systemverilog-sv2v,floorplan.init,2,input]	[(str,str)]	('cleanup.clean', '0')
[flowgraph,asicflow-systemverilog-sv2v,floorplan.init,2,task]	str	init_floorplan
[flowgraph,asicflow-systemverilog-sv2v,floorplan.init,2,taskmodule]	str	siliconcompiler.tools.openroad.init_floorplan/InitFloorplanTask
[flowgraph,asicflow-systemverilog-sv2v,floorplan.init,2,tool]	str	openroad

2.1.2.2.12. floorplan.macro_placement/0

Keypath	Type	Value
[flowgraph,asicflow-systemverilog-sv2v,floorplan.macro_placement,0,input]	[(str,str)]	('floorplan.init', '0')
[flowgraph,asicflow-systemverilog-sv2v,floorplan.macro_placement,0,task]	str	macro_placement
[flowgraph,asicflow-systemverilog-sv2v,floorplan.macro_placement,0,taskmodule]	str	siliconcompiler.tools.openroad.macro_placement/MacroPlacementTask
[flowgraph,asicflow-systemverilog-sv2v,floorplan.macro_placement,0,tool]	str	openroad

2.1.2.2.13. floorplan.macro_placement/1

Keypath	Type	Value
[flowgraph,asicflow-systemverilog-sv2v,floorplan.macro_placement,1,input]	[(str,str)]	('floorplan.init', '1')
[flowgraph,asicflow-systemverilog-sv2v,floorplan.macro_placement,1,task]	str	macro_placement
[flowgraph,asicflow-systemverilog-sv2v,floorplan.macro_placement,1,taskmodule]	str	siliconcompiler.tools.openroad.macro_placement/MacroPlacementTask
[flowgraph,asicflow-systemverilog-sv2v,floorplan.macro_placement,1,tool]	str	openroad

2.1.2.2.14. floorplan.macro_placement/2

Keypath	Type	Value
[flowgraph,asicflow-systemverilog-sv2v,floorplan.macro_placement,2,input]	[(str,str)]	('floorplan.init', '2')
[flowgraph,asicflow-systemverilog-sv2v,floorplan.macro_placement,2,task]	str	macro_placement
[flowgraph,asicflow-systemverilog-sv2v,floorplan.macro_placement,2,taskmodule]	str	siliconcompiler.tools.openroad.macro_placement/MacroPlacementTask
[flowgraph,asicflow-systemverilog-sv2v,floorplan.macro_placement,2,tool]	str	openroad

2.1.2.2.15. floorplan.tapcell/0

Keypath	Type	Value
[flowgraph,asicflow-systemverilog-sv2v,floorplan.tapcell,0,input]	[(str,str)]	('floorplan.macro_placement', '0')
[flowgraph,asicflow-systemverilog-sv2v,floorplan.tapcell,0,task]	str	endcap_tapcell_insertion
[flowgraph,asicflow-systemverilog-sv2v,floorplan.tapcell,0,taskmodule]	str	siliconcompiler.tools.openroad.endcap_tapcell_insertion/EndCapTapCellTask
[flowgraph,asicflow-systemverilog-sv2v,floorplan.tapcell,0,tool]	str	openroad

2.1.2.2.16. floorplan.tapcell/1

Keypath	Type	Value
[flowgraph,asicflow-systemverilog-sv2v,floorplan.tapcell,1,input]	[(str,str)]	('floorplan.macro_placement', '1')
[flowgraph,asicflow-systemverilog-sv2v,floorplan.tapcell,1,task]	str	endcap_tapcell_insertion
[flowgraph,asicflow-systemverilog-sv2v,floorplan.tapcell,1,taskmodule]	str	siliconcompiler.tools.openroad.endcap_tapcell_insertion/EndCapTapCellTask
[flowgraph,asicflow-systemverilog-sv2v,floorplan.tapcell,1,tool]	str	openroad

2.1.2.2.17. floorplan.tapcell/2

Keypath	Type	Value
[flowgraph,asicflow-systemverilog-sv2v,floorplan.tapcell,2,input]	[(str,str)]	('floorplan.macro_placement', '2')
[flowgraph,asicflow-systemverilog-sv2v,floorplan.tapcell,2,task]	str	endcap_tapcell_insertion
[flowgraph,asicflow-systemverilog-sv2v,floorplan.tapcell,2,taskmodule]	str	siliconcompiler.tools.openroad.endcap_tapcell_insertion/EndCapTapCellTask
[flowgraph,asicflow-systemverilog-sv2v,floorplan.tapcell,2,tool]	str	openroad

2.1.2.2.18. floorplan.power_grid/0

Keypath	Type	Value
[flowgraph,asicflow-systemverilog-sv2v,floorplan.power_grid,0,input]	[(str,str)]	('floorplan.tapcell', '0')
[flowgraph,asicflow-systemverilog-sv2v,floorplan.power_grid,0,task]	str	power_grid
[flowgraph,asicflow-systemverilog-sv2v,floorplan.power_grid,0,taskmodule]	str	siliconcompiler.tools.openroad.power_grid/PowerGridTask
[flowgraph,asicflow-systemverilog-sv2v,floorplan.power_grid,0,tool]	str	openroad

2.1.2.2.19. floorplan.power_grid/1

Keypath	Type	Value
[flowgraph,asicflow-systemverilog-sv2v,floorplan.power_grid,1,input]	[(str,str)]	('floorplan.tapcell', '1')
[flowgraph,asicflow-systemverilog-sv2v,floorplan.power_grid,1,task]	str	power_grid
[flowgraph,asicflow-systemverilog-sv2v,floorplan.power_grid,1,taskmodule]	str	siliconcompiler.tools.openroad.power_grid/PowerGridTask
[flowgraph,asicflow-systemverilog-sv2v,floorplan.power_grid,1,tool]	str	openroad

2.1.2.2.20. floorplan.power_grid/2

Keypath	Type	Value
[flowgraph,asicflow-systemverilog-sv2v,floorplan.power_grid,2,input]	[(str,str)]	('floorplan.tapcell', '2')
[flowgraph,asicflow-systemverilog-sv2v,floorplan.power_grid,2,task]	str	power_grid
[flowgraph,asicflow-systemverilog-sv2v,floorplan.power_grid,2,taskmodule]	str	siliconcompiler.tools.openroad.power_grid/PowerGridTask
[flowgraph,asicflow-systemverilog-sv2v,floorplan.power_grid,2,tool]	str	openroad

2.1.2.2.21. floorplan.pin_placement/0

Keypath	Type	Value
[flowgraph,asicflow-systemverilog-sv2v,floorplan.pin_placement,0,input]	[(str,str)]	('floorplan.power_grid', '0')
[flowgraph,asicflow-systemverilog-sv2v,floorplan.pin_placement,0,task]	str	pin_placement
[flowgraph,asicflow-systemverilog-sv2v,floorplan.pin_placement,0,taskmodule]	str	siliconcompiler.tools.openroad.pin_placement/PinPlacementTask
[flowgraph,asicflow-systemverilog-sv2v,floorplan.pin_placement,0,tool]	str	openroad

2.1.2.2.22. floorplan.pin_placement/1

Keypath	Type	Value
[flowgraph,asicflow-systemverilog-sv2v,floorplan.pin_placement,1,input]	[(str,str)]	('floorplan.power_grid', '1')
[flowgraph,asicflow-systemverilog-sv2v,floorplan.pin_placement,1,task]	str	pin_placement
[flowgraph,asicflow-systemverilog-sv2v,floorplan.pin_placement,1,taskmodule]	str	siliconcompiler.tools.openroad.pin_placement/PinPlacementTask
[flowgraph,asicflow-systemverilog-sv2v,floorplan.pin_placement,1,tool]	str	openroad

2.1.2.2.23. floorplan.pin_placement/2

Keypath	Type	Value
[flowgraph,asicflow-systemverilog-sv2v,floorplan.pin_placement,2,input]	[(str,str)]	('floorplan.power_grid', '2')
[flowgraph,asicflow-systemverilog-sv2v,floorplan.pin_placement,2,task]	str	pin_placement
[flowgraph,asicflow-systemverilog-sv2v,floorplan.pin_placement,2,taskmodule]	str	siliconcompiler.tools.openroad.pin_placement/PinPlacementTask
[flowgraph,asicflow-systemverilog-sv2v,floorplan.pin_placement,2,tool]	str	openroad

2.1.2.2.24. floorplan.min/0

Keypath	Type	Value
[flowgraph,asicflow-systemverilog-sv2v,floorplan.min,0,input]	[(str,str)]	('floorplan.pin_placement', '0') ('floorplan.pin_placement', '1') ('floorplan.pin_placement', '2')
[flowgraph,asicflow-systemverilog-sv2v,floorplan.min,0,task]	str	minimum
[flowgraph,asicflow-systemverilog-sv2v,floorplan.min,0,taskmodule]	str	siliconcompiler.tools.builtin.minimum/MinimumTask
[flowgraph,asicflow-systemverilog-sv2v,floorplan.min,0,tool]	str	builtin

2.1.2.2.25. place.global/0

Keypath	Type	Value
[flowgraph,asicflow-systemverilog-sv2v,place.global,0,input]	[(str,str)]	('floorplan.min', '0')
[flowgraph,asicflow-systemverilog-sv2v,place.global,0,task]	str	global_placement
[flowgraph,asicflow-systemverilog-sv2v,place.global,0,taskmodule]	str	siliconcompiler.tools.openroad.global_placement/GlobalPlacementTask
[flowgraph,asicflow-systemverilog-sv2v,place.global,0,tool]	str	openroad

2.1.2.2.26. place.global/1

Keypath	Type	Value
[flowgraph,asicflow-systemverilog-sv2v,place.global,1,input]	[(str,str)]	('floorplan.min', '0')
[flowgraph,asicflow-systemverilog-sv2v,place.global,1,task]	str	global_placement
[flowgraph,asicflow-systemverilog-sv2v,place.global,1,taskmodule]	str	siliconcompiler.tools.openroad.global_placement/GlobalPlacementTask
[flowgraph,asicflow-systemverilog-sv2v,place.global,1,tool]	str	openroad

2.1.2.2.27. place.global/2

Keypath	Type	Value
[flowgraph,asicflow-systemverilog-sv2v,place.global,2,input]	[(str,str)]	('floorplan.min', '0')
[flowgraph,asicflow-systemverilog-sv2v,place.global,2,task]	str	global_placement
[flowgraph,asicflow-systemverilog-sv2v,place.global,2,taskmodule]	str	siliconcompiler.tools.openroad.global_placement/GlobalPlacementTask
[flowgraph,asicflow-systemverilog-sv2v,place.global,2,tool]	str	openroad

2.1.2.2.28. place.repair_design/0

Keypath	Type	Value
[flowgraph,asicflow-systemverilog-sv2v,place.repair_design,0,input]	[(str,str)]	('place.global', '0')
[flowgraph,asicflow-systemverilog-sv2v,place.repair_design,0,task]	str	repair_design
[flowgraph,asicflow-systemverilog-sv2v,place.repair_design,0,taskmodule]	str	siliconcompiler.tools.openroad.repair_design/RepairDesignTask
[flowgraph,asicflow-systemverilog-sv2v,place.repair_design,0,tool]	str	openroad

2.1.2.2.29. place.repair_design/1

Keypath	Type	Value
[flowgraph,asicflow-systemverilog-sv2v,place.repair_design,1,input]	[(str,str)]	('place.global', '1')
[flowgraph,asicflow-systemverilog-sv2v,place.repair_design,1,task]	str	repair_design
[flowgraph,asicflow-systemverilog-sv2v,place.repair_design,1,taskmodule]	str	siliconcompiler.tools.openroad.repair_design/RepairDesignTask
[flowgraph,asicflow-systemverilog-sv2v,place.repair_design,1,tool]	str	openroad

2.1.2.2.30. place.repair_design/2

Keypath	Type	Value
[flowgraph,asicflow-systemverilog-sv2v,place.repair_design,2,input]	[(str,str)]	('place.global', '2')
[flowgraph,asicflow-systemverilog-sv2v,place.repair_design,2,task]	str	repair_design
[flowgraph,asicflow-systemverilog-sv2v,place.repair_design,2,taskmodule]	str	siliconcompiler.tools.openroad.repair_design/RepairDesignTask
[flowgraph,asicflow-systemverilog-sv2v,place.repair_design,2,tool]	str	openroad

2.1.2.2.31. place.detailed/0

Keypath	Type	Value
[flowgraph,asicflow-systemverilog-sv2v,place.detailed,0,input]	[(str,str)]	('place.repair_design', '0')
[flowgraph,asicflow-systemverilog-sv2v,place.detailed,0,task]	str	detailed_placement
[flowgraph,asicflow-systemverilog-sv2v,place.detailed,0,taskmodule]	str	siliconcompiler.tools.openroad.detailed_placement/DetailedPlacementTask
[flowgraph,asicflow-systemverilog-sv2v,place.detailed,0,tool]	str	openroad

2.1.2.2.32. place.detailed/1

Keypath	Type	Value
[flowgraph,asicflow-systemverilog-sv2v,place.detailed,1,input]	[(str,str)]	('place.repair_design', '1')
[flowgraph,asicflow-systemverilog-sv2v,place.detailed,1,task]	str	detailed_placement
[flowgraph,asicflow-systemverilog-sv2v,place.detailed,1,taskmodule]	str	siliconcompiler.tools.openroad.detailed_placement/DetailedPlacementTask
[flowgraph,asicflow-systemverilog-sv2v,place.detailed,1,tool]	str	openroad

2.1.2.2.33. place.detailed/2

Keypath	Type	Value
[flowgraph,asicflow-systemverilog-sv2v,place.detailed,2,input]	[(str,str)]	('place.repair_design', '2')
[flowgraph,asicflow-systemverilog-sv2v,place.detailed,2,task]	str	detailed_placement
[flowgraph,asicflow-systemverilog-sv2v,place.detailed,2,taskmodule]	str	siliconcompiler.tools.openroad.detailed_placement/DetailedPlacementTask
[flowgraph,asicflow-systemverilog-sv2v,place.detailed,2,tool]	str	openroad

2.1.2.2.34. place.min/0

Keypath	Type	Value
[flowgraph,asicflow-systemverilog-sv2v,place.min,0,input]	[(str,str)]	('place.detailed', '0') ('place.detailed', '1') ('place.detailed', '2')
[flowgraph,asicflow-systemverilog-sv2v,place.min,0,task]	str	minimum
[flowgraph,asicflow-systemverilog-sv2v,place.min,0,taskmodule]	str	siliconcompiler.tools.builtin.minimum/MinimumTask
[flowgraph,asicflow-systemverilog-sv2v,place.min,0,tool]	str	builtin

2.1.2.2.35. cts.clock_tree_synthesis/0

Keypath	Type	Value
[flowgraph,asicflow-systemverilog-sv2v,cts.clock_tree_synthesis,0,input]	[(str,str)]	('place.min', '0')
[flowgraph,asicflow-systemverilog-sv2v,cts.clock_tree_synthesis,0,task]	str	clock_tree_synthesis
[flowgraph,asicflow-systemverilog-sv2v,cts.clock_tree_synthesis,0,taskmodule]	str	siliconcompiler.tools.openroad.clock_tree_synthesis/CTSTask
[flowgraph,asicflow-systemverilog-sv2v,cts.clock_tree_synthesis,0,tool]	str	openroad

2.1.2.2.36. cts.clock_tree_synthesis/1

Keypath	Type	Value
[flowgraph,asicflow-systemverilog-sv2v,cts.clock_tree_synthesis,1,input]	[(str,str)]	('place.min', '0')
[flowgraph,asicflow-systemverilog-sv2v,cts.clock_tree_synthesis,1,task]	str	clock_tree_synthesis
[flowgraph,asicflow-systemverilog-sv2v,cts.clock_tree_synthesis,1,taskmodule]	str	siliconcompiler.tools.openroad.clock_tree_synthesis/CTSTask
[flowgraph,asicflow-systemverilog-sv2v,cts.clock_tree_synthesis,1,tool]	str	openroad

2.1.2.2.37. cts.clock_tree_synthesis/2

Keypath	Type	Value
[flowgraph,asicflow-systemverilog-sv2v,cts.clock_tree_synthesis,2,input]	[(str,str)]	('place.min', '0')
[flowgraph,asicflow-systemverilog-sv2v,cts.clock_tree_synthesis,2,task]	str	clock_tree_synthesis
[flowgraph,asicflow-systemverilog-sv2v,cts.clock_tree_synthesis,2,taskmodule]	str	siliconcompiler.tools.openroad.clock_tree_synthesis/CTSTask
[flowgraph,asicflow-systemverilog-sv2v,cts.clock_tree_synthesis,2,tool]	str	openroad

2.1.2.2.38. cts.repair_timing/0

Keypath	Type	Value
[flowgraph,asicflow-systemverilog-sv2v,cts.repair_timing,0,input]	[(str,str)]	('cts.clock_tree_synthesis', '0')
[flowgraph,asicflow-systemverilog-sv2v,cts.repair_timing,0,task]	str	repair_timing
[flowgraph,asicflow-systemverilog-sv2v,cts.repair_timing,0,taskmodule]	str	siliconcompiler.tools.openroad.repair_timing/RepairTimingTask
[flowgraph,asicflow-systemverilog-sv2v,cts.repair_timing,0,tool]	str	openroad

2.1.2.2.39. cts.repair_timing/1

Keypath	Type	Value
[flowgraph,asicflow-systemverilog-sv2v,cts.repair_timing,1,input]	[(str,str)]	('cts.clock_tree_synthesis', '1')
[flowgraph,asicflow-systemverilog-sv2v,cts.repair_timing,1,task]	str	repair_timing
[flowgraph,asicflow-systemverilog-sv2v,cts.repair_timing,1,taskmodule]	str	siliconcompiler.tools.openroad.repair_timing/RepairTimingTask
[flowgraph,asicflow-systemverilog-sv2v,cts.repair_timing,1,tool]	str	openroad

2.1.2.2.40. cts.repair_timing/2

Keypath	Type	Value
[flowgraph,asicflow-systemverilog-sv2v,cts.repair_timing,2,input]	[(str,str)]	('cts.clock_tree_synthesis', '2')
[flowgraph,asicflow-systemverilog-sv2v,cts.repair_timing,2,task]	str	repair_timing
[flowgraph,asicflow-systemverilog-sv2v,cts.repair_timing,2,taskmodule]	str	siliconcompiler.tools.openroad.repair_timing/RepairTimingTask
[flowgraph,asicflow-systemverilog-sv2v,cts.repair_timing,2,tool]	str	openroad

2.1.2.2.41. cts.min/0

Keypath	Type	Value
[flowgraph,asicflow-systemverilog-sv2v,cts.min,0,input]	[(str,str)]	('cts.repair_timing', '0') ('cts.repair_timing', '1') ('cts.repair_timing', '2')
[flowgraph,asicflow-systemverilog-sv2v,cts.min,0,task]	str	minimum
[flowgraph,asicflow-systemverilog-sv2v,cts.min,0,taskmodule]	str	siliconcompiler.tools.builtin.minimum/MinimumTask
[flowgraph,asicflow-systemverilog-sv2v,cts.min,0,tool]	str	builtin

2.1.2.2.42. cts.fillcell/0

Keypath	Type	Value
[flowgraph,asicflow-systemverilog-sv2v,cts.fillcell,0,input]	[(str,str)]	('cts.min', '0')
[flowgraph,asicflow-systemverilog-sv2v,cts.fillcell,0,task]	str	fillercell_insertion
[flowgraph,asicflow-systemverilog-sv2v,cts.fillcell,0,taskmodule]	str	siliconcompiler.tools.openroad.fillercell_insertion/FillCellTask
[flowgraph,asicflow-systemverilog-sv2v,cts.fillcell,0,tool]	str	openroad

2.1.2.2.43. route.global/0

Keypath	Type	Value
[flowgraph,asicflow-systemverilog-sv2v,route.global,0,input]	[(str,str)]	('cts.fillcell', '0')
[flowgraph,asicflow-systemverilog-sv2v,route.global,0,task]	str	global_route
[flowgraph,asicflow-systemverilog-sv2v,route.global,0,taskmodule]	str	siliconcompiler.tools.openroad.global_route/GlobalRouteTask
[flowgraph,asicflow-systemverilog-sv2v,route.global,0,tool]	str	openroad

2.1.2.2.44. route.global/1

Keypath	Type	Value
[flowgraph,asicflow-systemverilog-sv2v,route.global,1,input]	[(str,str)]	('cts.fillcell', '0')
[flowgraph,asicflow-systemverilog-sv2v,route.global,1,task]	str	global_route
[flowgraph,asicflow-systemverilog-sv2v,route.global,1,taskmodule]	str	siliconcompiler.tools.openroad.global_route/GlobalRouteTask
[flowgraph,asicflow-systemverilog-sv2v,route.global,1,tool]	str	openroad

2.1.2.2.45. route.global/2

Keypath	Type	Value
[flowgraph,asicflow-systemverilog-sv2v,route.global,2,input]	[(str,str)]	('cts.fillcell', '0')
[flowgraph,asicflow-systemverilog-sv2v,route.global,2,task]	str	global_route
[flowgraph,asicflow-systemverilog-sv2v,route.global,2,taskmodule]	str	siliconcompiler.tools.openroad.global_route/GlobalRouteTask
[flowgraph,asicflow-systemverilog-sv2v,route.global,2,tool]	str	openroad

2.1.2.2.46. route.antenna_repair/0

Keypath	Type	Value
[flowgraph,asicflow-systemverilog-sv2v,route.antenna_repair,0,input]	[(str,str)]	('route.global', '0')
[flowgraph,asicflow-systemverilog-sv2v,route.antenna_repair,0,task]	str	antenna_repair
[flowgraph,asicflow-systemverilog-sv2v,route.antenna_repair,0,taskmodule]	str	siliconcompiler.tools.openroad.antenna_repair/AntennaRepairTask
[flowgraph,asicflow-systemverilog-sv2v,route.antenna_repair,0,tool]	str	openroad

2.1.2.2.47. route.antenna_repair/1

Keypath	Type	Value
[flowgraph,asicflow-systemverilog-sv2v,route.antenna_repair,1,input]	[(str,str)]	('route.global', '1')
[flowgraph,asicflow-systemverilog-sv2v,route.antenna_repair,1,task]	str	antenna_repair
[flowgraph,asicflow-systemverilog-sv2v,route.antenna_repair,1,taskmodule]	str	siliconcompiler.tools.openroad.antenna_repair/AntennaRepairTask
[flowgraph,asicflow-systemverilog-sv2v,route.antenna_repair,1,tool]	str	openroad

2.1.2.2.48. route.antenna_repair/2

Keypath	Type	Value
[flowgraph,asicflow-systemverilog-sv2v,route.antenna_repair,2,input]	[(str,str)]	('route.global', '2')
[flowgraph,asicflow-systemverilog-sv2v,route.antenna_repair,2,task]	str	antenna_repair
[flowgraph,asicflow-systemverilog-sv2v,route.antenna_repair,2,taskmodule]	str	siliconcompiler.tools.openroad.antenna_repair/AntennaRepairTask
[flowgraph,asicflow-systemverilog-sv2v,route.antenna_repair,2,tool]	str	openroad

2.1.2.2.49. route.detailed/0

Keypath	Type	Value
[flowgraph,asicflow-systemverilog-sv2v,route.detailed,0,input]	[(str,str)]	('route.antenna_repair', '0')
[flowgraph,asicflow-systemverilog-sv2v,route.detailed,0,task]	str	detailed_route
[flowgraph,asicflow-systemverilog-sv2v,route.detailed,0,taskmodule]	str	siliconcompiler.tools.openroad.detailed_route/DetailedRouteTask
[flowgraph,asicflow-systemverilog-sv2v,route.detailed,0,tool]	str	openroad

2.1.2.2.50. route.detailed/1

Keypath	Type	Value
[flowgraph,asicflow-systemverilog-sv2v,route.detailed,1,input]	[(str,str)]	('route.antenna_repair', '1')
[flowgraph,asicflow-systemverilog-sv2v,route.detailed,1,task]	str	detailed_route
[flowgraph,asicflow-systemverilog-sv2v,route.detailed,1,taskmodule]	str	siliconcompiler.tools.openroad.detailed_route/DetailedRouteTask
[flowgraph,asicflow-systemverilog-sv2v,route.detailed,1,tool]	str	openroad

2.1.2.2.51. route.detailed/2

Keypath	Type	Value
[flowgraph,asicflow-systemverilog-sv2v,route.detailed,2,input]	[(str,str)]	('route.antenna_repair', '2')
[flowgraph,asicflow-systemverilog-sv2v,route.detailed,2,task]	str	detailed_route
[flowgraph,asicflow-systemverilog-sv2v,route.detailed,2,taskmodule]	str	siliconcompiler.tools.openroad.detailed_route/DetailedRouteTask
[flowgraph,asicflow-systemverilog-sv2v,route.detailed,2,tool]	str	openroad

2.1.2.2.52. route.min/0

Keypath	Type	Value
[flowgraph,asicflow-systemverilog-sv2v,route.min,0,input]	[(str,str)]	('route.detailed', '0') ('route.detailed', '1') ('route.detailed', '2')
[flowgraph,asicflow-systemverilog-sv2v,route.min,0,task]	str	minimum
[flowgraph,asicflow-systemverilog-sv2v,route.min,0,taskmodule]	str	siliconcompiler.tools.builtin.minimum/MinimumTask
[flowgraph,asicflow-systemverilog-sv2v,route.min,0,tool]	str	builtin

2.1.2.2.53. dfm.metal_fill/0

Keypath	Type	Value
[flowgraph,asicflow-systemverilog-sv2v,dfm.metal_fill,0,input]	[(str,str)]	('route.min', '0')
[flowgraph,asicflow-systemverilog-sv2v,dfm.metal_fill,0,task]	str	fillmetal_insertion
[flowgraph,asicflow-systemverilog-sv2v,dfm.metal_fill,0,taskmodule]	str	siliconcompiler.tools.openroad.fillmetal_insertion/FillMetalTask
[flowgraph,asicflow-systemverilog-sv2v,dfm.metal_fill,0,tool]	str	openroad

2.1.2.2.54. write.gds/0

Keypath	Type	Value
[flowgraph,asicflow-systemverilog-sv2v,write.gds,0,input]	[(str,str)]	('dfm.metal_fill', '0')
[flowgraph,asicflow-systemverilog-sv2v,write.gds,0,task]	str	export
[flowgraph,asicflow-systemverilog-sv2v,write.gds,0,taskmodule]	str	siliconcompiler.tools.klayout.export/ExportTask
[flowgraph,asicflow-systemverilog-sv2v,write.gds,0,tool]	str	klayout

2.1.2.2.55. write.views/0

Keypath	Type	Value
[flowgraph,asicflow-systemverilog-sv2v,write.views,0,input]	[(str,str)]	('dfm.metal_fill', '0')
[flowgraph,asicflow-systemverilog-sv2v,write.views,0,task]	str	write_data
[flowgraph,asicflow-systemverilog-sv2v,write.views,0,taskmodule]	str	siliconcompiler.tools.openroad.write_data/WriteViewsTask
[flowgraph,asicflow-systemverilog-sv2v,write.views,0,tool]	str	openroad

2.1.3. asicflow-chisel / 2

A configurable ASIC compilation flow.

This flow targets ASIC designs, taking RTL through a complete synthesis, place-and-route, and finishing flow.

The flow is divided into the following major steps:

• elaborate: RTL elaboration using Slang.

• synthesis: RTL synthesis using Yosys.

• floorplan: Floorplanning, including macro placement, tapcell/endcap insertion, power grid generation, and pin placement.

• place: Global and detailed placement.

• cts: Clock tree synthesis and post-CTS timing repair.

• route: Global and detailed routing.

• dfm: Design-for-manufacturing steps, primarily metal fill.

• write: Writing out final views of the design (GDSII, etc.).

The synthesis, floorplan, place, cts, and route steps support parallel execution to explore different strategies. This can be configured by setting the corresponding *_np argument to a value greater than 1.

Args:

• name (str, optional): The name of the flow. If not provided, it defaults to ‘asicflow-<language>’.

• language (str): The hardware description language of the design. One of ‘verilog’, ‘systemverilog’, ‘systemverilog-sv2v’, ‘chisel’, ‘vhdl’, or ‘hls’.

• syn_np (int): Number of parallel synthesis jobs to launch.

• floorplan_np (int): Number of parallel floorplan jobs to launch.

• place_np (int): Number of parallel placement jobs to launch.

• cts_np (int): Number of parallel clock tree synthesis jobs to launch.

• route_np (int): Number of parallel routing jobs to launch.

File: asicflow.py

2.1.3.1. Graph

2.1.3.2. Nodes

2.1.3.2.1. convert/0

Keypath	Type	Value
[flowgraph,asicflow-chisel,convert,0,task]	str	convert
[flowgraph,asicflow-chisel,convert,0,taskmodule]	str	siliconcompiler.tools.chisel.convert/ConvertTask
[flowgraph,asicflow-chisel,convert,0,tool]	str	chisel

2.1.3.2.2. synthesis/0

Keypath	Type	Value
[flowgraph,asicflow-chisel,synthesis,0,goal,errors]	float	0.0
[flowgraph,asicflow-chisel,synthesis,0,input]	[(str,str)]	('convert', '0')
[flowgraph,asicflow-chisel,synthesis,0,task]	str	syn_asic
[flowgraph,asicflow-chisel,synthesis,0,taskmodule]	str	siliconcompiler.tools.yosys.syn_asic/ASICSynthesis
[flowgraph,asicflow-chisel,synthesis,0,tool]	str	yosys

2.1.3.2.3. synthesis/1

Keypath	Type	Value
[flowgraph,asicflow-chisel,synthesis,1,goal,errors]	float	0.0
[flowgraph,asicflow-chisel,synthesis,1,input]	[(str,str)]	('convert', '0')
[flowgraph,asicflow-chisel,synthesis,1,task]	str	syn_asic
[flowgraph,asicflow-chisel,synthesis,1,taskmodule]	str	siliconcompiler.tools.yosys.syn_asic/ASICSynthesis
[flowgraph,asicflow-chisel,synthesis,1,tool]	str	yosys

2.1.3.2.4. synthesis/2

Keypath	Type	Value
[flowgraph,asicflow-chisel,synthesis,2,goal,errors]	float	0.0
[flowgraph,asicflow-chisel,synthesis,2,input]	[(str,str)]	('convert', '0')
[flowgraph,asicflow-chisel,synthesis,2,task]	str	syn_asic
[flowgraph,asicflow-chisel,synthesis,2,taskmodule]	str	siliconcompiler.tools.yosys.syn_asic/ASICSynthesis
[flowgraph,asicflow-chisel,synthesis,2,tool]	str	yosys

2.1.3.2.5. synthesis.min/0

Keypath	Type	Value
[flowgraph,asicflow-chisel,synthesis.min,0,input]	[(str,str)]	('synthesis', '0') ('synthesis', '1') ('synthesis', '2')
[flowgraph,asicflow-chisel,synthesis.min,0,task]	str	minimum
[flowgraph,asicflow-chisel,synthesis.min,0,taskmodule]	str	siliconcompiler.tools.builtin.minimum/MinimumTask
[flowgraph,asicflow-chisel,synthesis.min,0,tool]	str	builtin

2.1.3.2.6. cleanup.clean/0

Keypath	Type	Value
[flowgraph,asicflow-chisel,cleanup.clean,0,input]	[(str,str)]	('synthesis.min', '0')
[flowgraph,asicflow-chisel,cleanup.clean,0,task]	str	cleanup_synth
[flowgraph,asicflow-chisel,cleanup.clean,0,taskmodule]	str	siliconcompiler.tools.openroad.synth_cleanup/CleanupSynthTask
[flowgraph,asicflow-chisel,cleanup.clean,0,tool]	str	openroad

2.1.3.2.7. synthesis.timing/0

Keypath	Type	Value
[flowgraph,asicflow-chisel,synthesis.timing,0,input]	[(str,str)]	('synthesis.min', '0')
[flowgraph,asicflow-chisel,synthesis.timing,0,task]	str	timing
[flowgraph,asicflow-chisel,synthesis.timing,0,taskmodule]	str	siliconcompiler.tools.opensta.timing/TimingTask
[flowgraph,asicflow-chisel,synthesis.timing,0,tool]	str	opensta

2.1.3.2.8. floorplan.init/0

Keypath	Type	Value
[flowgraph,asicflow-chisel,floorplan.init,0,input]	[(str,str)]	('cleanup.clean', '0')
[flowgraph,asicflow-chisel,floorplan.init,0,task]	str	init_floorplan
[flowgraph,asicflow-chisel,floorplan.init,0,taskmodule]	str	siliconcompiler.tools.openroad.init_floorplan/InitFloorplanTask
[flowgraph,asicflow-chisel,floorplan.init,0,tool]	str	openroad

2.1.3.2.9. floorplan.init/1

Keypath	Type	Value
[flowgraph,asicflow-chisel,floorplan.init,1,input]	[(str,str)]	('cleanup.clean', '0')
[flowgraph,asicflow-chisel,floorplan.init,1,task]	str	init_floorplan
[flowgraph,asicflow-chisel,floorplan.init,1,taskmodule]	str	siliconcompiler.tools.openroad.init_floorplan/InitFloorplanTask
[flowgraph,asicflow-chisel,floorplan.init,1,tool]	str	openroad

2.1.3.2.10. floorplan.init/2

Keypath	Type	Value
[flowgraph,asicflow-chisel,floorplan.init,2,input]	[(str,str)]	('cleanup.clean', '0')
[flowgraph,asicflow-chisel,floorplan.init,2,task]	str	init_floorplan
[flowgraph,asicflow-chisel,floorplan.init,2,taskmodule]	str	siliconcompiler.tools.openroad.init_floorplan/InitFloorplanTask
[flowgraph,asicflow-chisel,floorplan.init,2,tool]	str	openroad

2.1.3.2.11. floorplan.macro_placement/0

Keypath	Type	Value
[flowgraph,asicflow-chisel,floorplan.macro_placement,0,input]	[(str,str)]	('floorplan.init', '0')
[flowgraph,asicflow-chisel,floorplan.macro_placement,0,task]	str	macro_placement
[flowgraph,asicflow-chisel,floorplan.macro_placement,0,taskmodule]	str	siliconcompiler.tools.openroad.macro_placement/MacroPlacementTask
[flowgraph,asicflow-chisel,floorplan.macro_placement,0,tool]	str	openroad

2.1.3.2.12. floorplan.macro_placement/1

Keypath	Type	Value
[flowgraph,asicflow-chisel,floorplan.macro_placement,1,input]	[(str,str)]	('floorplan.init', '1')
[flowgraph,asicflow-chisel,floorplan.macro_placement,1,task]	str	macro_placement
[flowgraph,asicflow-chisel,floorplan.macro_placement,1,taskmodule]	str	siliconcompiler.tools.openroad.macro_placement/MacroPlacementTask
[flowgraph,asicflow-chisel,floorplan.macro_placement,1,tool]	str	openroad

2.1.3.2.13. floorplan.macro_placement/2

Keypath	Type	Value
[flowgraph,asicflow-chisel,floorplan.macro_placement,2,input]	[(str,str)]	('floorplan.init', '2')
[flowgraph,asicflow-chisel,floorplan.macro_placement,2,task]	str	macro_placement
[flowgraph,asicflow-chisel,floorplan.macro_placement,2,taskmodule]	str	siliconcompiler.tools.openroad.macro_placement/MacroPlacementTask
[flowgraph,asicflow-chisel,floorplan.macro_placement,2,tool]	str	openroad

2.1.3.2.14. floorplan.tapcell/0

Keypath	Type	Value
[flowgraph,asicflow-chisel,floorplan.tapcell,0,input]	[(str,str)]	('floorplan.macro_placement', '0')
[flowgraph,asicflow-chisel,floorplan.tapcell,0,task]	str	endcap_tapcell_insertion
[flowgraph,asicflow-chisel,floorplan.tapcell,0,taskmodule]	str	siliconcompiler.tools.openroad.endcap_tapcell_insertion/EndCapTapCellTask
[flowgraph,asicflow-chisel,floorplan.tapcell,0,tool]	str	openroad

2.1.3.2.15. floorplan.tapcell/1

Keypath	Type	Value
[flowgraph,asicflow-chisel,floorplan.tapcell,1,input]	[(str,str)]	('floorplan.macro_placement', '1')
[flowgraph,asicflow-chisel,floorplan.tapcell,1,task]	str	endcap_tapcell_insertion
[flowgraph,asicflow-chisel,floorplan.tapcell,1,taskmodule]	str	siliconcompiler.tools.openroad.endcap_tapcell_insertion/EndCapTapCellTask
[flowgraph,asicflow-chisel,floorplan.tapcell,1,tool]	str	openroad

2.1.3.2.16. floorplan.tapcell/2

Keypath	Type	Value
[flowgraph,asicflow-chisel,floorplan.tapcell,2,input]	[(str,str)]	('floorplan.macro_placement', '2')
[flowgraph,asicflow-chisel,floorplan.tapcell,2,task]	str	endcap_tapcell_insertion
[flowgraph,asicflow-chisel,floorplan.tapcell,2,taskmodule]	str	siliconcompiler.tools.openroad.endcap_tapcell_insertion/EndCapTapCellTask
[flowgraph,asicflow-chisel,floorplan.tapcell,2,tool]	str	openroad

2.1.3.2.17. floorplan.power_grid/0

Keypath	Type	Value
[flowgraph,asicflow-chisel,floorplan.power_grid,0,input]	[(str,str)]	('floorplan.tapcell', '0')
[flowgraph,asicflow-chisel,floorplan.power_grid,0,task]	str	power_grid
[flowgraph,asicflow-chisel,floorplan.power_grid,0,taskmodule]	str	siliconcompiler.tools.openroad.power_grid/PowerGridTask
[flowgraph,asicflow-chisel,floorplan.power_grid,0,tool]	str	openroad

2.1.3.2.18. floorplan.power_grid/1

Keypath	Type	Value
[flowgraph,asicflow-chisel,floorplan.power_grid,1,input]	[(str,str)]	('floorplan.tapcell', '1')
[flowgraph,asicflow-chisel,floorplan.power_grid,1,task]	str	power_grid
[flowgraph,asicflow-chisel,floorplan.power_grid,1,taskmodule]	str	siliconcompiler.tools.openroad.power_grid/PowerGridTask
[flowgraph,asicflow-chisel,floorplan.power_grid,1,tool]	str	openroad

2.1.3.2.19. floorplan.power_grid/2

Keypath	Type	Value
[flowgraph,asicflow-chisel,floorplan.power_grid,2,input]	[(str,str)]	('floorplan.tapcell', '2')
[flowgraph,asicflow-chisel,floorplan.power_grid,2,task]	str	power_grid
[flowgraph,asicflow-chisel,floorplan.power_grid,2,taskmodule]	str	siliconcompiler.tools.openroad.power_grid/PowerGridTask
[flowgraph,asicflow-chisel,floorplan.power_grid,2,tool]	str	openroad

2.1.3.2.20. floorplan.pin_placement/0

Keypath	Type	Value
[flowgraph,asicflow-chisel,floorplan.pin_placement,0,input]	[(str,str)]	('floorplan.power_grid', '0')
[flowgraph,asicflow-chisel,floorplan.pin_placement,0,task]	str	pin_placement
[flowgraph,asicflow-chisel,floorplan.pin_placement,0,taskmodule]	str	siliconcompiler.tools.openroad.pin_placement/PinPlacementTask
[flowgraph,asicflow-chisel,floorplan.pin_placement,0,tool]	str	openroad

2.1.3.2.21. floorplan.pin_placement/1

Keypath	Type	Value
[flowgraph,asicflow-chisel,floorplan.pin_placement,1,input]	[(str,str)]	('floorplan.power_grid', '1')
[flowgraph,asicflow-chisel,floorplan.pin_placement,1,task]	str	pin_placement
[flowgraph,asicflow-chisel,floorplan.pin_placement,1,taskmodule]	str	siliconcompiler.tools.openroad.pin_placement/PinPlacementTask
[flowgraph,asicflow-chisel,floorplan.pin_placement,1,tool]	str	openroad

2.1.3.2.22. floorplan.pin_placement/2

Keypath	Type	Value
[flowgraph,asicflow-chisel,floorplan.pin_placement,2,input]	[(str,str)]	('floorplan.power_grid', '2')
[flowgraph,asicflow-chisel,floorplan.pin_placement,2,task]	str	pin_placement
[flowgraph,asicflow-chisel,floorplan.pin_placement,2,taskmodule]	str	siliconcompiler.tools.openroad.pin_placement/PinPlacementTask
[flowgraph,asicflow-chisel,floorplan.pin_placement,2,tool]	str	openroad

2.1.3.2.23. floorplan.min/0

Keypath	Type	Value
[flowgraph,asicflow-chisel,floorplan.min,0,input]	[(str,str)]	('floorplan.pin_placement', '0') ('floorplan.pin_placement', '1') ('floorplan.pin_placement', '2')
[flowgraph,asicflow-chisel,floorplan.min,0,task]	str	minimum
[flowgraph,asicflow-chisel,floorplan.min,0,taskmodule]	str	siliconcompiler.tools.builtin.minimum/MinimumTask
[flowgraph,asicflow-chisel,floorplan.min,0,tool]	str	builtin

2.1.3.2.24. place.global/0

Keypath	Type	Value
[flowgraph,asicflow-chisel,place.global,0,input]	[(str,str)]	('floorplan.min', '0')
[flowgraph,asicflow-chisel,place.global,0,task]	str	global_placement
[flowgraph,asicflow-chisel,place.global,0,taskmodule]	str	siliconcompiler.tools.openroad.global_placement/GlobalPlacementTask
[flowgraph,asicflow-chisel,place.global,0,tool]	str	openroad

2.1.3.2.25. place.global/1

Keypath	Type	Value
[flowgraph,asicflow-chisel,place.global,1,input]	[(str,str)]	('floorplan.min', '0')
[flowgraph,asicflow-chisel,place.global,1,task]	str	global_placement
[flowgraph,asicflow-chisel,place.global,1,taskmodule]	str	siliconcompiler.tools.openroad.global_placement/GlobalPlacementTask
[flowgraph,asicflow-chisel,place.global,1,tool]	str	openroad

2.1.3.2.26. place.global/2

Keypath	Type	Value
[flowgraph,asicflow-chisel,place.global,2,input]	[(str,str)]	('floorplan.min', '0')
[flowgraph,asicflow-chisel,place.global,2,task]	str	global_placement
[flowgraph,asicflow-chisel,place.global,2,taskmodule]	str	siliconcompiler.tools.openroad.global_placement/GlobalPlacementTask
[flowgraph,asicflow-chisel,place.global,2,tool]	str	openroad

2.1.3.2.27. place.repair_design/0

Keypath	Type	Value
[flowgraph,asicflow-chisel,place.repair_design,0,input]	[(str,str)]	('place.global', '0')
[flowgraph,asicflow-chisel,place.repair_design,0,task]	str	repair_design
[flowgraph,asicflow-chisel,place.repair_design,0,taskmodule]	str	siliconcompiler.tools.openroad.repair_design/RepairDesignTask
[flowgraph,asicflow-chisel,place.repair_design,0,tool]	str	openroad

2.1.3.2.28. place.repair_design/1

Keypath	Type	Value
[flowgraph,asicflow-chisel,place.repair_design,1,input]	[(str,str)]	('place.global', '1')
[flowgraph,asicflow-chisel,place.repair_design,1,task]	str	repair_design
[flowgraph,asicflow-chisel,place.repair_design,1,taskmodule]	str	siliconcompiler.tools.openroad.repair_design/RepairDesignTask
[flowgraph,asicflow-chisel,place.repair_design,1,tool]	str	openroad

2.1.3.2.29. place.repair_design/2

Keypath	Type	Value
[flowgraph,asicflow-chisel,place.repair_design,2,input]	[(str,str)]	('place.global', '2')
[flowgraph,asicflow-chisel,place.repair_design,2,task]	str	repair_design
[flowgraph,asicflow-chisel,place.repair_design,2,taskmodule]	str	siliconcompiler.tools.openroad.repair_design/RepairDesignTask
[flowgraph,asicflow-chisel,place.repair_design,2,tool]	str	openroad

2.1.3.2.30. place.detailed/0

Keypath	Type	Value
[flowgraph,asicflow-chisel,place.detailed,0,input]	[(str,str)]	('place.repair_design', '0')
[flowgraph,asicflow-chisel,place.detailed,0,task]	str	detailed_placement
[flowgraph,asicflow-chisel,place.detailed,0,taskmodule]	str	siliconcompiler.tools.openroad.detailed_placement/DetailedPlacementTask
[flowgraph,asicflow-chisel,place.detailed,0,tool]	str	openroad

2.1.3.2.31. place.detailed/1

Keypath	Type	Value
[flowgraph,asicflow-chisel,place.detailed,1,input]	[(str,str)]	('place.repair_design', '1')
[flowgraph,asicflow-chisel,place.detailed,1,task]	str	detailed_placement
[flowgraph,asicflow-chisel,place.detailed,1,taskmodule]	str	siliconcompiler.tools.openroad.detailed_placement/DetailedPlacementTask
[flowgraph,asicflow-chisel,place.detailed,1,tool]	str	openroad

2.1.3.2.32. place.detailed/2

Keypath	Type	Value
[flowgraph,asicflow-chisel,place.detailed,2,input]	[(str,str)]	('place.repair_design', '2')
[flowgraph,asicflow-chisel,place.detailed,2,task]	str	detailed_placement
[flowgraph,asicflow-chisel,place.detailed,2,taskmodule]	str	siliconcompiler.tools.openroad.detailed_placement/DetailedPlacementTask
[flowgraph,asicflow-chisel,place.detailed,2,tool]	str	openroad

2.1.3.2.33. place.min/0

Keypath	Type	Value
[flowgraph,asicflow-chisel,place.min,0,input]	[(str,str)]	('place.detailed', '0') ('place.detailed', '1') ('place.detailed', '2')
[flowgraph,asicflow-chisel,place.min,0,task]	str	minimum
[flowgraph,asicflow-chisel,place.min,0,taskmodule]	str	siliconcompiler.tools.builtin.minimum/MinimumTask
[flowgraph,asicflow-chisel,place.min,0,tool]	str	builtin

2.1.3.2.34. cts.clock_tree_synthesis/0

Keypath	Type	Value
[flowgraph,asicflow-chisel,cts.clock_tree_synthesis,0,input]	[(str,str)]	('place.min', '0')
[flowgraph,asicflow-chisel,cts.clock_tree_synthesis,0,task]	str	clock_tree_synthesis
[flowgraph,asicflow-chisel,cts.clock_tree_synthesis,0,taskmodule]	str	siliconcompiler.tools.openroad.clock_tree_synthesis/CTSTask
[flowgraph,asicflow-chisel,cts.clock_tree_synthesis,0,tool]	str	openroad

2.1.3.2.35. cts.clock_tree_synthesis/1

Keypath	Type	Value
[flowgraph,asicflow-chisel,cts.clock_tree_synthesis,1,input]	[(str,str)]	('place.min', '0')
[flowgraph,asicflow-chisel,cts.clock_tree_synthesis,1,task]	str	clock_tree_synthesis
[flowgraph,asicflow-chisel,cts.clock_tree_synthesis,1,taskmodule]	str	siliconcompiler.tools.openroad.clock_tree_synthesis/CTSTask
[flowgraph,asicflow-chisel,cts.clock_tree_synthesis,1,tool]	str	openroad

2.1.3.2.36. cts.clock_tree_synthesis/2

Keypath	Type	Value
[flowgraph,asicflow-chisel,cts.clock_tree_synthesis,2,input]	[(str,str)]	('place.min', '0')
[flowgraph,asicflow-chisel,cts.clock_tree_synthesis,2,task]	str	clock_tree_synthesis
[flowgraph,asicflow-chisel,cts.clock_tree_synthesis,2,taskmodule]	str	siliconcompiler.tools.openroad.clock_tree_synthesis/CTSTask
[flowgraph,asicflow-chisel,cts.clock_tree_synthesis,2,tool]	str	openroad

2.1.3.2.37. cts.repair_timing/0

Keypath	Type	Value
[flowgraph,asicflow-chisel,cts.repair_timing,0,input]	[(str,str)]	('cts.clock_tree_synthesis', '0')
[flowgraph,asicflow-chisel,cts.repair_timing,0,task]	str	repair_timing
[flowgraph,asicflow-chisel,cts.repair_timing,0,taskmodule]	str	siliconcompiler.tools.openroad.repair_timing/RepairTimingTask
[flowgraph,asicflow-chisel,cts.repair_timing,0,tool]	str	openroad

2.1.3.2.38. cts.repair_timing/1

Keypath	Type	Value
[flowgraph,asicflow-chisel,cts.repair_timing,1,input]	[(str,str)]	('cts.clock_tree_synthesis', '1')
[flowgraph,asicflow-chisel,cts.repair_timing,1,task]	str	repair_timing
[flowgraph,asicflow-chisel,cts.repair_timing,1,taskmodule]	str	siliconcompiler.tools.openroad.repair_timing/RepairTimingTask
[flowgraph,asicflow-chisel,cts.repair_timing,1,tool]	str	openroad

2.1.3.2.39. cts.repair_timing/2

Keypath	Type	Value
[flowgraph,asicflow-chisel,cts.repair_timing,2,input]	[(str,str)]	('cts.clock_tree_synthesis', '2')
[flowgraph,asicflow-chisel,cts.repair_timing,2,task]	str	repair_timing
[flowgraph,asicflow-chisel,cts.repair_timing,2,taskmodule]	str	siliconcompiler.tools.openroad.repair_timing/RepairTimingTask
[flowgraph,asicflow-chisel,cts.repair_timing,2,tool]	str	openroad

2.1.3.2.40. cts.min/0

Keypath	Type	Value
[flowgraph,asicflow-chisel,cts.min,0,input]	[(str,str)]	('cts.repair_timing', '0') ('cts.repair_timing', '1') ('cts.repair_timing', '2')
[flowgraph,asicflow-chisel,cts.min,0,task]	str	minimum
[flowgraph,asicflow-chisel,cts.min,0,taskmodule]	str	siliconcompiler.tools.builtin.minimum/MinimumTask
[flowgraph,asicflow-chisel,cts.min,0,tool]	str	builtin

2.1.3.2.41. cts.fillcell/0

Keypath	Type	Value
[flowgraph,asicflow-chisel,cts.fillcell,0,input]	[(str,str)]	('cts.min', '0')
[flowgraph,asicflow-chisel,cts.fillcell,0,task]	str	fillercell_insertion
[flowgraph,asicflow-chisel,cts.fillcell,0,taskmodule]	str	siliconcompiler.tools.openroad.fillercell_insertion/FillCellTask
[flowgraph,asicflow-chisel,cts.fillcell,0,tool]	str	openroad

2.1.3.2.42. route.global/0

Keypath	Type	Value
[flowgraph,asicflow-chisel,route.global,0,input]	[(str,str)]	('cts.fillcell', '0')
[flowgraph,asicflow-chisel,route.global,0,task]	str	global_route
[flowgraph,asicflow-chisel,route.global,0,taskmodule]	str	siliconcompiler.tools.openroad.global_route/GlobalRouteTask
[flowgraph,asicflow-chisel,route.global,0,tool]	str	openroad

2.1.3.2.43. route.global/1

Keypath	Type	Value
[flowgraph,asicflow-chisel,route.global,1,input]	[(str,str)]	('cts.fillcell', '0')
[flowgraph,asicflow-chisel,route.global,1,task]	str	global_route
[flowgraph,asicflow-chisel,route.global,1,taskmodule]	str	siliconcompiler.tools.openroad.global_route/GlobalRouteTask
[flowgraph,asicflow-chisel,route.global,1,tool]	str	openroad

2.1.3.2.44. route.global/2

Keypath	Type	Value
[flowgraph,asicflow-chisel,route.global,2,input]	[(str,str)]	('cts.fillcell', '0')
[flowgraph,asicflow-chisel,route.global,2,task]	str	global_route
[flowgraph,asicflow-chisel,route.global,2,taskmodule]	str	siliconcompiler.tools.openroad.global_route/GlobalRouteTask
[flowgraph,asicflow-chisel,route.global,2,tool]	str	openroad

2.1.3.2.45. route.antenna_repair/0

Keypath	Type	Value
[flowgraph,asicflow-chisel,route.antenna_repair,0,input]	[(str,str)]	('route.global', '0')
[flowgraph,asicflow-chisel,route.antenna_repair,0,task]	str	antenna_repair
[flowgraph,asicflow-chisel,route.antenna_repair,0,taskmodule]	str	siliconcompiler.tools.openroad.antenna_repair/AntennaRepairTask
[flowgraph,asicflow-chisel,route.antenna_repair,0,tool]	str	openroad

2.1.3.2.46. route.antenna_repair/1

Keypath	Type	Value
[flowgraph,asicflow-chisel,route.antenna_repair,1,input]	[(str,str)]	('route.global', '1')
[flowgraph,asicflow-chisel,route.antenna_repair,1,task]	str	antenna_repair
[flowgraph,asicflow-chisel,route.antenna_repair,1,taskmodule]	str	siliconcompiler.tools.openroad.antenna_repair/AntennaRepairTask
[flowgraph,asicflow-chisel,route.antenna_repair,1,tool]	str	openroad

2.1.3.2.47. route.antenna_repair/2

Keypath	Type	Value
[flowgraph,asicflow-chisel,route.antenna_repair,2,input]	[(str,str)]	('route.global', '2')
[flowgraph,asicflow-chisel,route.antenna_repair,2,task]	str	antenna_repair
[flowgraph,asicflow-chisel,route.antenna_repair,2,taskmodule]	str	siliconcompiler.tools.openroad.antenna_repair/AntennaRepairTask
[flowgraph,asicflow-chisel,route.antenna_repair,2,tool]	str	openroad

2.1.3.2.48. route.detailed/0

Keypath	Type	Value
[flowgraph,asicflow-chisel,route.detailed,0,input]	[(str,str)]	('route.antenna_repair', '0')
[flowgraph,asicflow-chisel,route.detailed,0,task]	str	detailed_route
[flowgraph,asicflow-chisel,route.detailed,0,taskmodule]	str	siliconcompiler.tools.openroad.detailed_route/DetailedRouteTask
[flowgraph,asicflow-chisel,route.detailed,0,tool]	str	openroad

2.1.3.2.49. route.detailed/1

Keypath	Type	Value
[flowgraph,asicflow-chisel,route.detailed,1,input]	[(str,str)]	('route.antenna_repair', '1')
[flowgraph,asicflow-chisel,route.detailed,1,task]	str	detailed_route
[flowgraph,asicflow-chisel,route.detailed,1,taskmodule]	str	siliconcompiler.tools.openroad.detailed_route/DetailedRouteTask
[flowgraph,asicflow-chisel,route.detailed,1,tool]	str	openroad

2.1.3.2.50. route.detailed/2

Keypath	Type	Value
[flowgraph,asicflow-chisel,route.detailed,2,input]	[(str,str)]	('route.antenna_repair', '2')
[flowgraph,asicflow-chisel,route.detailed,2,task]	str	detailed_route
[flowgraph,asicflow-chisel,route.detailed,2,taskmodule]	str	siliconcompiler.tools.openroad.detailed_route/DetailedRouteTask
[flowgraph,asicflow-chisel,route.detailed,2,tool]	str	openroad

2.1.3.2.51. route.min/0

Keypath	Type	Value
[flowgraph,asicflow-chisel,route.min,0,input]	[(str,str)]	('route.detailed', '0') ('route.detailed', '1') ('route.detailed', '2')
[flowgraph,asicflow-chisel,route.min,0,task]	str	minimum
[flowgraph,asicflow-chisel,route.min,0,taskmodule]	str	siliconcompiler.tools.builtin.minimum/MinimumTask
[flowgraph,asicflow-chisel,route.min,0,tool]	str	builtin

2.1.3.2.52. dfm.metal_fill/0

Keypath	Type	Value
[flowgraph,asicflow-chisel,dfm.metal_fill,0,input]	[(str,str)]	('route.min', '0')
[flowgraph,asicflow-chisel,dfm.metal_fill,0,task]	str	fillmetal_insertion
[flowgraph,asicflow-chisel,dfm.metal_fill,0,taskmodule]	str	siliconcompiler.tools.openroad.fillmetal_insertion/FillMetalTask
[flowgraph,asicflow-chisel,dfm.metal_fill,0,tool]	str	openroad

2.1.3.2.53. write.gds/0

Keypath	Type	Value
[flowgraph,asicflow-chisel,write.gds,0,input]	[(str,str)]	('dfm.metal_fill', '0')
[flowgraph,asicflow-chisel,write.gds,0,task]	str	export
[flowgraph,asicflow-chisel,write.gds,0,taskmodule]	str	siliconcompiler.tools.klayout.export/ExportTask
[flowgraph,asicflow-chisel,write.gds,0,tool]	str	klayout

2.1.3.2.54. write.views/0

Keypath	Type	Value
[flowgraph,asicflow-chisel,write.views,0,input]	[(str,str)]	('dfm.metal_fill', '0')
[flowgraph,asicflow-chisel,write.views,0,task]	str	write_data
[flowgraph,asicflow-chisel,write.views,0,taskmodule]	str	siliconcompiler.tools.openroad.write_data/WriteViewsTask
[flowgraph,asicflow-chisel,write.views,0,tool]	str	openroad

2.1.4. asicflow-vhdl / 3

A configurable ASIC compilation flow.

This flow targets ASIC designs, taking RTL through a complete synthesis, place-and-route, and finishing flow.

The flow is divided into the following major steps:

• elaborate: RTL elaboration using Slang.

• synthesis: RTL synthesis using Yosys.

• floorplan: Floorplanning, including macro placement, tapcell/endcap insertion, power grid generation, and pin placement.

• place: Global and detailed placement.

• cts: Clock tree synthesis and post-CTS timing repair.

• route: Global and detailed routing.

• dfm: Design-for-manufacturing steps, primarily metal fill.

• write: Writing out final views of the design (GDSII, etc.).

The synthesis, floorplan, place, cts, and route steps support parallel execution to explore different strategies. This can be configured by setting the corresponding *_np argument to a value greater than 1.

Args:

• name (str, optional): The name of the flow. If not provided, it defaults to ‘asicflow-<language>’.

• language (str): The hardware description language of the design. One of ‘verilog’, ‘systemverilog’, ‘systemverilog-sv2v’, ‘chisel’, ‘vhdl’, or ‘hls’.

• syn_np (int): Number of parallel synthesis jobs to launch.

• floorplan_np (int): Number of parallel floorplan jobs to launch.

• place_np (int): Number of parallel placement jobs to launch.

• cts_np (int): Number of parallel clock tree synthesis jobs to launch.

• route_np (int): Number of parallel routing jobs to launch.

File: asicflow.py

2.1.4.1. Graph

2.1.4.2. Nodes

2.1.4.2.1. convert/0

Keypath	Type	Value
[flowgraph,asicflow-vhdl,convert,0,task]	str	convert
[flowgraph,asicflow-vhdl,convert,0,taskmodule]	str	siliconcompiler.tools.ghdl.convert/ConvertTask
[flowgraph,asicflow-vhdl,convert,0,tool]	str	ghdl

2.1.4.2.2. synthesis/0

Keypath	Type	Value
[flowgraph,asicflow-vhdl,synthesis,0,goal,errors]	float	0.0
[flowgraph,asicflow-vhdl,synthesis,0,input]	[(str,str)]	('convert', '0')
[flowgraph,asicflow-vhdl,synthesis,0,task]	str	syn_asic
[flowgraph,asicflow-vhdl,synthesis,0,taskmodule]	str	siliconcompiler.tools.yosys.syn_asic/ASICSynthesis
[flowgraph,asicflow-vhdl,synthesis,0,tool]	str	yosys

2.1.4.2.3. synthesis/1

Keypath	Type	Value
[flowgraph,asicflow-vhdl,synthesis,1,goal,errors]	float	0.0
[flowgraph,asicflow-vhdl,synthesis,1,input]	[(str,str)]	('convert', '0')
[flowgraph,asicflow-vhdl,synthesis,1,task]	str	syn_asic
[flowgraph,asicflow-vhdl,synthesis,1,taskmodule]	str	siliconcompiler.tools.yosys.syn_asic/ASICSynthesis
[flowgraph,asicflow-vhdl,synthesis,1,tool]	str	yosys

2.1.4.2.4. synthesis/2

Keypath	Type	Value
[flowgraph,asicflow-vhdl,synthesis,2,goal,errors]	float	0.0
[flowgraph,asicflow-vhdl,synthesis,2,input]	[(str,str)]	('convert', '0')
[flowgraph,asicflow-vhdl,synthesis,2,task]	str	syn_asic
[flowgraph,asicflow-vhdl,synthesis,2,taskmodule]	str	siliconcompiler.tools.yosys.syn_asic/ASICSynthesis
[flowgraph,asicflow-vhdl,synthesis,2,tool]	str	yosys

2.1.4.2.5. synthesis.min/0

Keypath	Type	Value
[flowgraph,asicflow-vhdl,synthesis.min,0,input]	[(str,str)]	('synthesis', '0') ('synthesis', '1') ('synthesis', '2')
[flowgraph,asicflow-vhdl,synthesis.min,0,task]	str	minimum
[flowgraph,asicflow-vhdl,synthesis.min,0,taskmodule]	str	siliconcompiler.tools.builtin.minimum/MinimumTask
[flowgraph,asicflow-vhdl,synthesis.min,0,tool]	str	builtin

2.1.4.2.6. cleanup.clean/0

Keypath	Type	Value
[flowgraph,asicflow-vhdl,cleanup.clean,0,input]	[(str,str)]	('synthesis.min', '0')
[flowgraph,asicflow-vhdl,cleanup.clean,0,task]	str	cleanup_synth
[flowgraph,asicflow-vhdl,cleanup.clean,0,taskmodule]	str	siliconcompiler.tools.openroad.synth_cleanup/CleanupSynthTask
[flowgraph,asicflow-vhdl,cleanup.clean,0,tool]	str	openroad

2.1.4.2.7. synthesis.timing/0

Keypath	Type	Value
[flowgraph,asicflow-vhdl,synthesis.timing,0,input]	[(str,str)]	('synthesis.min', '0')
[flowgraph,asicflow-vhdl,synthesis.timing,0,task]	str	timing
[flowgraph,asicflow-vhdl,synthesis.timing,0,taskmodule]	str	siliconcompiler.tools.opensta.timing/TimingTask
[flowgraph,asicflow-vhdl,synthesis.timing,0,tool]	str	opensta

2.1.4.2.8. floorplan.init/0

Keypath	Type	Value
[flowgraph,asicflow-vhdl,floorplan.init,0,input]	[(str,str)]	('cleanup.clean', '0')
[flowgraph,asicflow-vhdl,floorplan.init,0,task]	str	init_floorplan
[flowgraph,asicflow-vhdl,floorplan.init,0,taskmodule]	str	siliconcompiler.tools.openroad.init_floorplan/InitFloorplanTask
[flowgraph,asicflow-vhdl,floorplan.init,0,tool]	str	openroad

2.1.4.2.9. floorplan.init/1

Keypath	Type	Value
[flowgraph,asicflow-vhdl,floorplan.init,1,input]	[(str,str)]	('cleanup.clean', '0')
[flowgraph,asicflow-vhdl,floorplan.init,1,task]	str	init_floorplan
[flowgraph,asicflow-vhdl,floorplan.init,1,taskmodule]	str	siliconcompiler.tools.openroad.init_floorplan/InitFloorplanTask
[flowgraph,asicflow-vhdl,floorplan.init,1,tool]	str	openroad

2.1.4.2.10. floorplan.init/2

Keypath	Type	Value
[flowgraph,asicflow-vhdl,floorplan.init,2,input]	[(str,str)]	('cleanup.clean', '0')
[flowgraph,asicflow-vhdl,floorplan.init,2,task]	str	init_floorplan
[flowgraph,asicflow-vhdl,floorplan.init,2,taskmodule]	str	siliconcompiler.tools.openroad.init_floorplan/InitFloorplanTask
[flowgraph,asicflow-vhdl,floorplan.init,2,tool]	str	openroad

2.1.4.2.11. floorplan.macro_placement/0

Keypath	Type	Value
[flowgraph,asicflow-vhdl,floorplan.macro_placement,0,input]	[(str,str)]	('floorplan.init', '0')
[flowgraph,asicflow-vhdl,floorplan.macro_placement,0,task]	str	macro_placement
[flowgraph,asicflow-vhdl,floorplan.macro_placement,0,taskmodule]	str	siliconcompiler.tools.openroad.macro_placement/MacroPlacementTask
[flowgraph,asicflow-vhdl,floorplan.macro_placement,0,tool]	str	openroad

2.1.4.2.12. floorplan.macro_placement/1

Keypath	Type	Value
[flowgraph,asicflow-vhdl,floorplan.macro_placement,1,input]	[(str,str)]	('floorplan.init', '1')
[flowgraph,asicflow-vhdl,floorplan.macro_placement,1,task]	str	macro_placement
[flowgraph,asicflow-vhdl,floorplan.macro_placement,1,taskmodule]	str	siliconcompiler.tools.openroad.macro_placement/MacroPlacementTask
[flowgraph,asicflow-vhdl,floorplan.macro_placement,1,tool]	str	openroad

2.1.4.2.13. floorplan.macro_placement/2

Keypath	Type	Value
[flowgraph,asicflow-vhdl,floorplan.macro_placement,2,input]	[(str,str)]	('floorplan.init', '2')
[flowgraph,asicflow-vhdl,floorplan.macro_placement,2,task]	str	macro_placement
[flowgraph,asicflow-vhdl,floorplan.macro_placement,2,taskmodule]	str	siliconcompiler.tools.openroad.macro_placement/MacroPlacementTask
[flowgraph,asicflow-vhdl,floorplan.macro_placement,2,tool]	str	openroad

2.1.4.2.14. floorplan.tapcell/0

Keypath	Type	Value
[flowgraph,asicflow-vhdl,floorplan.tapcell,0,input]	[(str,str)]	('floorplan.macro_placement', '0')
[flowgraph,asicflow-vhdl,floorplan.tapcell,0,task]	str	endcap_tapcell_insertion
[flowgraph,asicflow-vhdl,floorplan.tapcell,0,taskmodule]	str	siliconcompiler.tools.openroad.endcap_tapcell_insertion/EndCapTapCellTask
[flowgraph,asicflow-vhdl,floorplan.tapcell,0,tool]	str	openroad

2.1.4.2.15. floorplan.tapcell/1

Keypath	Type	Value
[flowgraph,asicflow-vhdl,floorplan.tapcell,1,input]	[(str,str)]	('floorplan.macro_placement', '1')
[flowgraph,asicflow-vhdl,floorplan.tapcell,1,task]	str	endcap_tapcell_insertion
[flowgraph,asicflow-vhdl,floorplan.tapcell,1,taskmodule]	str	siliconcompiler.tools.openroad.endcap_tapcell_insertion/EndCapTapCellTask
[flowgraph,asicflow-vhdl,floorplan.tapcell,1,tool]	str	openroad

2.1.4.2.16. floorplan.tapcell/2

Keypath	Type	Value
[flowgraph,asicflow-vhdl,floorplan.tapcell,2,input]	[(str,str)]	('floorplan.macro_placement', '2')
[flowgraph,asicflow-vhdl,floorplan.tapcell,2,task]	str	endcap_tapcell_insertion
[flowgraph,asicflow-vhdl,floorplan.tapcell,2,taskmodule]	str	siliconcompiler.tools.openroad.endcap_tapcell_insertion/EndCapTapCellTask
[flowgraph,asicflow-vhdl,floorplan.tapcell,2,tool]	str	openroad

2.1.4.2.17. floorplan.power_grid/0

Keypath	Type	Value
[flowgraph,asicflow-vhdl,floorplan.power_grid,0,input]	[(str,str)]	('floorplan.tapcell', '0')
[flowgraph,asicflow-vhdl,floorplan.power_grid,0,task]	str	power_grid
[flowgraph,asicflow-vhdl,floorplan.power_grid,0,taskmodule]	str	siliconcompiler.tools.openroad.power_grid/PowerGridTask
[flowgraph,asicflow-vhdl,floorplan.power_grid,0,tool]	str	openroad

2.1.4.2.18. floorplan.power_grid/1

Keypath	Type	Value
[flowgraph,asicflow-vhdl,floorplan.power_grid,1,input]	[(str,str)]	('floorplan.tapcell', '1')
[flowgraph,asicflow-vhdl,floorplan.power_grid,1,task]	str	power_grid
[flowgraph,asicflow-vhdl,floorplan.power_grid,1,taskmodule]	str	siliconcompiler.tools.openroad.power_grid/PowerGridTask
[flowgraph,asicflow-vhdl,floorplan.power_grid,1,tool]	str	openroad

2.1.4.2.19. floorplan.power_grid/2

Keypath	Type	Value
[flowgraph,asicflow-vhdl,floorplan.power_grid,2,input]	[(str,str)]	('floorplan.tapcell', '2')
[flowgraph,asicflow-vhdl,floorplan.power_grid,2,task]	str	power_grid
[flowgraph,asicflow-vhdl,floorplan.power_grid,2,taskmodule]	str	siliconcompiler.tools.openroad.power_grid/PowerGridTask
[flowgraph,asicflow-vhdl,floorplan.power_grid,2,tool]	str	openroad

2.1.4.2.20. floorplan.pin_placement/0

Keypath	Type	Value
[flowgraph,asicflow-vhdl,floorplan.pin_placement,0,input]	[(str,str)]	('floorplan.power_grid', '0')
[flowgraph,asicflow-vhdl,floorplan.pin_placement,0,task]	str	pin_placement
[flowgraph,asicflow-vhdl,floorplan.pin_placement,0,taskmodule]	str	siliconcompiler.tools.openroad.pin_placement/PinPlacementTask
[flowgraph,asicflow-vhdl,floorplan.pin_placement,0,tool]	str	openroad

2.1.4.2.21. floorplan.pin_placement/1

Keypath	Type	Value
[flowgraph,asicflow-vhdl,floorplan.pin_placement,1,input]	[(str,str)]	('floorplan.power_grid', '1')
[flowgraph,asicflow-vhdl,floorplan.pin_placement,1,task]	str	pin_placement
[flowgraph,asicflow-vhdl,floorplan.pin_placement,1,taskmodule]	str	siliconcompiler.tools.openroad.pin_placement/PinPlacementTask
[flowgraph,asicflow-vhdl,floorplan.pin_placement,1,tool]	str	openroad

2.1.4.2.22. floorplan.pin_placement/2

Keypath	Type	Value
[flowgraph,asicflow-vhdl,floorplan.pin_placement,2,input]	[(str,str)]	('floorplan.power_grid', '2')
[flowgraph,asicflow-vhdl,floorplan.pin_placement,2,task]	str	pin_placement
[flowgraph,asicflow-vhdl,floorplan.pin_placement,2,taskmodule]	str	siliconcompiler.tools.openroad.pin_placement/PinPlacementTask
[flowgraph,asicflow-vhdl,floorplan.pin_placement,2,tool]	str	openroad

2.1.4.2.23. floorplan.min/0

Keypath	Type	Value
[flowgraph,asicflow-vhdl,floorplan.min,0,input]	[(str,str)]	('floorplan.pin_placement', '0') ('floorplan.pin_placement', '1') ('floorplan.pin_placement', '2')
[flowgraph,asicflow-vhdl,floorplan.min,0,task]	str	minimum
[flowgraph,asicflow-vhdl,floorplan.min,0,taskmodule]	str	siliconcompiler.tools.builtin.minimum/MinimumTask
[flowgraph,asicflow-vhdl,floorplan.min,0,tool]	str	builtin

2.1.4.2.24. place.global/0

Keypath	Type	Value
[flowgraph,asicflow-vhdl,place.global,0,input]	[(str,str)]	('floorplan.min', '0')
[flowgraph,asicflow-vhdl,place.global,0,task]	str	global_placement
[flowgraph,asicflow-vhdl,place.global,0,taskmodule]	str	siliconcompiler.tools.openroad.global_placement/GlobalPlacementTask
[flowgraph,asicflow-vhdl,place.global,0,tool]	str	openroad

2.1.4.2.25. place.global/1

Keypath	Type	Value
[flowgraph,asicflow-vhdl,place.global,1,input]	[(str,str)]	('floorplan.min', '0')
[flowgraph,asicflow-vhdl,place.global,1,task]	str	global_placement
[flowgraph,asicflow-vhdl,place.global,1,taskmodule]	str	siliconcompiler.tools.openroad.global_placement/GlobalPlacementTask
[flowgraph,asicflow-vhdl,place.global,1,tool]	str	openroad

2.1.4.2.26. place.global/2

Keypath	Type	Value
[flowgraph,asicflow-vhdl,place.global,2,input]	[(str,str)]	('floorplan.min', '0')
[flowgraph,asicflow-vhdl,place.global,2,task]	str	global_placement
[flowgraph,asicflow-vhdl,place.global,2,taskmodule]	str	siliconcompiler.tools.openroad.global_placement/GlobalPlacementTask
[flowgraph,asicflow-vhdl,place.global,2,tool]	str	openroad

2.1.4.2.27. place.repair_design/0

Keypath	Type	Value
[flowgraph,asicflow-vhdl,place.repair_design,0,input]	[(str,str)]	('place.global', '0')
[flowgraph,asicflow-vhdl,place.repair_design,0,task]	str	repair_design
[flowgraph,asicflow-vhdl,place.repair_design,0,taskmodule]	str	siliconcompiler.tools.openroad.repair_design/RepairDesignTask
[flowgraph,asicflow-vhdl,place.repair_design,0,tool]	str	openroad

2.1.4.2.28. place.repair_design/1

Keypath	Type	Value
[flowgraph,asicflow-vhdl,place.repair_design,1,input]	[(str,str)]	('place.global', '1')
[flowgraph,asicflow-vhdl,place.repair_design,1,task]	str	repair_design
[flowgraph,asicflow-vhdl,place.repair_design,1,taskmodule]	str	siliconcompiler.tools.openroad.repair_design/RepairDesignTask
[flowgraph,asicflow-vhdl,place.repair_design,1,tool]	str	openroad

2.1.4.2.29. place.repair_design/2

Keypath	Type	Value
[flowgraph,asicflow-vhdl,place.repair_design,2,input]	[(str,str)]	('place.global', '2')
[flowgraph,asicflow-vhdl,place.repair_design,2,task]	str	repair_design
[flowgraph,asicflow-vhdl,place.repair_design,2,taskmodule]	str	siliconcompiler.tools.openroad.repair_design/RepairDesignTask
[flowgraph,asicflow-vhdl,place.repair_design,2,tool]	str	openroad

2.1.4.2.30. place.detailed/0

Keypath	Type	Value
[flowgraph,asicflow-vhdl,place.detailed,0,input]	[(str,str)]	('place.repair_design', '0')
[flowgraph,asicflow-vhdl,place.detailed,0,task]	str	detailed_placement
[flowgraph,asicflow-vhdl,place.detailed,0,taskmodule]	str	siliconcompiler.tools.openroad.detailed_placement/DetailedPlacementTask
[flowgraph,asicflow-vhdl,place.detailed,0,tool]	str	openroad

2.1.4.2.31. place.detailed/1

Keypath	Type	Value
[flowgraph,asicflow-vhdl,place.detailed,1,input]	[(str,str)]	('place.repair_design', '1')
[flowgraph,asicflow-vhdl,place.detailed,1,task]	str	detailed_placement
[flowgraph,asicflow-vhdl,place.detailed,1,taskmodule]	str	siliconcompiler.tools.openroad.detailed_placement/DetailedPlacementTask
[flowgraph,asicflow-vhdl,place.detailed,1,tool]	str	openroad

2.1.4.2.32. place.detailed/2

Keypath	Type	Value
[flowgraph,asicflow-vhdl,place.detailed,2,input]	[(str,str)]	('place.repair_design', '2')
[flowgraph,asicflow-vhdl,place.detailed,2,task]	str	detailed_placement
[flowgraph,asicflow-vhdl,place.detailed,2,taskmodule]	str	siliconcompiler.tools.openroad.detailed_placement/DetailedPlacementTask
[flowgraph,asicflow-vhdl,place.detailed,2,tool]	str	openroad

2.1.4.2.33. place.min/0

Keypath	Type	Value
[flowgraph,asicflow-vhdl,place.min,0,input]	[(str,str)]	('place.detailed', '0') ('place.detailed', '1') ('place.detailed', '2')
[flowgraph,asicflow-vhdl,place.min,0,task]	str	minimum
[flowgraph,asicflow-vhdl,place.min,0,taskmodule]	str	siliconcompiler.tools.builtin.minimum/MinimumTask
[flowgraph,asicflow-vhdl,place.min,0,tool]	str	builtin

2.1.4.2.34. cts.clock_tree_synthesis/0

Keypath	Type	Value
[flowgraph,asicflow-vhdl,cts.clock_tree_synthesis,0,input]	[(str,str)]	('place.min', '0')
[flowgraph,asicflow-vhdl,cts.clock_tree_synthesis,0,task]	str	clock_tree_synthesis
[flowgraph,asicflow-vhdl,cts.clock_tree_synthesis,0,taskmodule]	str	siliconcompiler.tools.openroad.clock_tree_synthesis/CTSTask
[flowgraph,asicflow-vhdl,cts.clock_tree_synthesis,0,tool]	str	openroad

2.1.4.2.35. cts.clock_tree_synthesis/1

Keypath	Type	Value
[flowgraph,asicflow-vhdl,cts.clock_tree_synthesis,1,input]	[(str,str)]	('place.min', '0')
[flowgraph,asicflow-vhdl,cts.clock_tree_synthesis,1,task]	str	clock_tree_synthesis
[flowgraph,asicflow-vhdl,cts.clock_tree_synthesis,1,taskmodule]	str	siliconcompiler.tools.openroad.clock_tree_synthesis/CTSTask
[flowgraph,asicflow-vhdl,cts.clock_tree_synthesis,1,tool]	str	openroad

2.1.4.2.36. cts.clock_tree_synthesis/2

Keypath	Type	Value
[flowgraph,asicflow-vhdl,cts.clock_tree_synthesis,2,input]	[(str,str)]	('place.min', '0')
[flowgraph,asicflow-vhdl,cts.clock_tree_synthesis,2,task]	str	clock_tree_synthesis
[flowgraph,asicflow-vhdl,cts.clock_tree_synthesis,2,taskmodule]	str	siliconcompiler.tools.openroad.clock_tree_synthesis/CTSTask
[flowgraph,asicflow-vhdl,cts.clock_tree_synthesis,2,tool]	str	openroad

2.1.4.2.37. cts.repair_timing/0

Keypath	Type	Value
[flowgraph,asicflow-vhdl,cts.repair_timing,0,input]	[(str,str)]	('cts.clock_tree_synthesis', '0')
[flowgraph,asicflow-vhdl,cts.repair_timing,0,task]	str	repair_timing
[flowgraph,asicflow-vhdl,cts.repair_timing,0,taskmodule]	str	siliconcompiler.tools.openroad.repair_timing/RepairTimingTask
[flowgraph,asicflow-vhdl,cts.repair_timing,0,tool]	str	openroad

2.1.4.2.38. cts.repair_timing/1

Keypath	Type	Value
[flowgraph,asicflow-vhdl,cts.repair_timing,1,input]	[(str,str)]	('cts.clock_tree_synthesis', '1')
[flowgraph,asicflow-vhdl,cts.repair_timing,1,task]	str	repair_timing
[flowgraph,asicflow-vhdl,cts.repair_timing,1,taskmodule]	str	siliconcompiler.tools.openroad.repair_timing/RepairTimingTask
[flowgraph,asicflow-vhdl,cts.repair_timing,1,tool]	str	openroad

2.1.4.2.39. cts.repair_timing/2

Keypath	Type	Value
[flowgraph,asicflow-vhdl,cts.repair_timing,2,input]	[(str,str)]	('cts.clock_tree_synthesis', '2')
[flowgraph,asicflow-vhdl,cts.repair_timing,2,task]	str	repair_timing
[flowgraph,asicflow-vhdl,cts.repair_timing,2,taskmodule]	str	siliconcompiler.tools.openroad.repair_timing/RepairTimingTask
[flowgraph,asicflow-vhdl,cts.repair_timing,2,tool]	str	openroad

2.1.4.2.40. cts.min/0

Keypath	Type	Value
[flowgraph,asicflow-vhdl,cts.min,0,input]	[(str,str)]	('cts.repair_timing', '0') ('cts.repair_timing', '1') ('cts.repair_timing', '2')
[flowgraph,asicflow-vhdl,cts.min,0,task]	str	minimum
[flowgraph,asicflow-vhdl,cts.min,0,taskmodule]	str	siliconcompiler.tools.builtin.minimum/MinimumTask
[flowgraph,asicflow-vhdl,cts.min,0,tool]	str	builtin

2.1.4.2.41. cts.fillcell/0

Keypath	Type	Value
[flowgraph,asicflow-vhdl,cts.fillcell,0,input]	[(str,str)]	('cts.min', '0')
[flowgraph,asicflow-vhdl,cts.fillcell,0,task]	str	fillercell_insertion
[flowgraph,asicflow-vhdl,cts.fillcell,0,taskmodule]	str	siliconcompiler.tools.openroad.fillercell_insertion/FillCellTask
[flowgraph,asicflow-vhdl,cts.fillcell,0,tool]	str	openroad

2.1.4.2.42. route.global/0

Keypath	Type	Value
[flowgraph,asicflow-vhdl,route.global,0,input]	[(str,str)]	('cts.fillcell', '0')
[flowgraph,asicflow-vhdl,route.global,0,task]	str	global_route
[flowgraph,asicflow-vhdl,route.global,0,taskmodule]	str	siliconcompiler.tools.openroad.global_route/GlobalRouteTask
[flowgraph,asicflow-vhdl,route.global,0,tool]	str	openroad

2.1.4.2.43. route.global/1

Keypath	Type	Value
[flowgraph,asicflow-vhdl,route.global,1,input]	[(str,str)]	('cts.fillcell', '0')
[flowgraph,asicflow-vhdl,route.global,1,task]	str	global_route
[flowgraph,asicflow-vhdl,route.global,1,taskmodule]	str	siliconcompiler.tools.openroad.global_route/GlobalRouteTask
[flowgraph,asicflow-vhdl,route.global,1,tool]	str	openroad

2.1.4.2.44. route.global/2

Keypath	Type	Value
[flowgraph,asicflow-vhdl,route.global,2,input]	[(str,str)]	('cts.fillcell', '0')
[flowgraph,asicflow-vhdl,route.global,2,task]	str	global_route
[flowgraph,asicflow-vhdl,route.global,2,taskmodule]	str	siliconcompiler.tools.openroad.global_route/GlobalRouteTask
[flowgraph,asicflow-vhdl,route.global,2,tool]	str	openroad

2.1.4.2.45. route.antenna_repair/0

Keypath	Type	Value
[flowgraph,asicflow-vhdl,route.antenna_repair,0,input]	[(str,str)]	('route.global', '0')
[flowgraph,asicflow-vhdl,route.antenna_repair,0,task]	str	antenna_repair
[flowgraph,asicflow-vhdl,route.antenna_repair,0,taskmodule]	str	siliconcompiler.tools.openroad.antenna_repair/AntennaRepairTask
[flowgraph,asicflow-vhdl,route.antenna_repair,0,tool]	str	openroad

2.1.4.2.46. route.antenna_repair/1

Keypath	Type	Value
[flowgraph,asicflow-vhdl,route.antenna_repair,1,input]	[(str,str)]	('route.global', '1')
[flowgraph,asicflow-vhdl,route.antenna_repair,1,task]	str	antenna_repair
[flowgraph,asicflow-vhdl,route.antenna_repair,1,taskmodule]	str	siliconcompiler.tools.openroad.antenna_repair/AntennaRepairTask
[flowgraph,asicflow-vhdl,route.antenna_repair,1,tool]	str	openroad

2.1.4.2.47. route.antenna_repair/2

Keypath	Type	Value
[flowgraph,asicflow-vhdl,route.antenna_repair,2,input]	[(str,str)]	('route.global', '2')
[flowgraph,asicflow-vhdl,route.antenna_repair,2,task]	str	antenna_repair
[flowgraph,asicflow-vhdl,route.antenna_repair,2,taskmodule]	str	siliconcompiler.tools.openroad.antenna_repair/AntennaRepairTask
[flowgraph,asicflow-vhdl,route.antenna_repair,2,tool]	str	openroad

2.1.4.2.48. route.detailed/0

Keypath	Type	Value
[flowgraph,asicflow-vhdl,route.detailed,0,input]	[(str,str)]	('route.antenna_repair', '0')
[flowgraph,asicflow-vhdl,route.detailed,0,task]	str	detailed_route
[flowgraph,asicflow-vhdl,route.detailed,0,taskmodule]	str	siliconcompiler.tools.openroad.detailed_route/DetailedRouteTask
[flowgraph,asicflow-vhdl,route.detailed,0,tool]	str	openroad

2.1.4.2.49. route.detailed/1

Keypath	Type	Value
[flowgraph,asicflow-vhdl,route.detailed,1,input]	[(str,str)]	('route.antenna_repair', '1')
[flowgraph,asicflow-vhdl,route.detailed,1,task]	str	detailed_route
[flowgraph,asicflow-vhdl,route.detailed,1,taskmodule]	str	siliconcompiler.tools.openroad.detailed_route/DetailedRouteTask
[flowgraph,asicflow-vhdl,route.detailed,1,tool]	str	openroad

2.1.4.2.50. route.detailed/2

Keypath	Type	Value
[flowgraph,asicflow-vhdl,route.detailed,2,input]	[(str,str)]	('route.antenna_repair', '2')
[flowgraph,asicflow-vhdl,route.detailed,2,task]	str	detailed_route
[flowgraph,asicflow-vhdl,route.detailed,2,taskmodule]	str	siliconcompiler.tools.openroad.detailed_route/DetailedRouteTask
[flowgraph,asicflow-vhdl,route.detailed,2,tool]	str	openroad

2.1.4.2.51. route.min/0

Keypath	Type	Value
[flowgraph,asicflow-vhdl,route.min,0,input]	[(str,str)]	('route.detailed', '0') ('route.detailed', '1') ('route.detailed', '2')
[flowgraph,asicflow-vhdl,route.min,0,task]	str	minimum
[flowgraph,asicflow-vhdl,route.min,0,taskmodule]	str	siliconcompiler.tools.builtin.minimum/MinimumTask
[flowgraph,asicflow-vhdl,route.min,0,tool]	str	builtin

2.1.4.2.52. dfm.metal_fill/0

Keypath	Type	Value
[flowgraph,asicflow-vhdl,dfm.metal_fill,0,input]	[(str,str)]	('route.min', '0')
[flowgraph,asicflow-vhdl,dfm.metal_fill,0,task]	str	fillmetal_insertion
[flowgraph,asicflow-vhdl,dfm.metal_fill,0,taskmodule]	str	siliconcompiler.tools.openroad.fillmetal_insertion/FillMetalTask
[flowgraph,asicflow-vhdl,dfm.metal_fill,0,tool]	str	openroad

2.1.4.2.53. write.gds/0

Keypath	Type	Value
[flowgraph,asicflow-vhdl,write.gds,0,input]	[(str,str)]	('dfm.metal_fill', '0')
[flowgraph,asicflow-vhdl,write.gds,0,task]	str	export
[flowgraph,asicflow-vhdl,write.gds,0,taskmodule]	str	siliconcompiler.tools.klayout.export/ExportTask
[flowgraph,asicflow-vhdl,write.gds,0,tool]	str	klayout

2.1.4.2.54. write.views/0

Keypath	Type	Value
[flowgraph,asicflow-vhdl,write.views,0,input]	[(str,str)]	('dfm.metal_fill', '0')
[flowgraph,asicflow-vhdl,write.views,0,task]	str	write_data
[flowgraph,asicflow-vhdl,write.views,0,taskmodule]	str	siliconcompiler.tools.openroad.write_data/WriteViewsTask
[flowgraph,asicflow-vhdl,write.views,0,tool]	str	openroad

2.1.5. asicflow-hls / 4

A configurable ASIC compilation flow.

This flow targets ASIC designs, taking RTL through a complete synthesis, place-and-route, and finishing flow.

The flow is divided into the following major steps:

• elaborate: RTL elaboration using Slang.

• synthesis: RTL synthesis using Yosys.

• floorplan: Floorplanning, including macro placement, tapcell/endcap insertion, power grid generation, and pin placement.

• place: Global and detailed placement.

• cts: Clock tree synthesis and post-CTS timing repair.

• route: Global and detailed routing.

• dfm: Design-for-manufacturing steps, primarily metal fill.

• write: Writing out final views of the design (GDSII, etc.).

The synthesis, floorplan, place, cts, and route steps support parallel execution to explore different strategies. This can be configured by setting the corresponding *_np argument to a value greater than 1.

Args:

• name (str, optional): The name of the flow. If not provided, it defaults to ‘asicflow-<language>’.

• language (str): The hardware description language of the design. One of ‘verilog’, ‘systemverilog’, ‘systemverilog-sv2v’, ‘chisel’, ‘vhdl’, or ‘hls’.

• syn_np (int): Number of parallel synthesis jobs to launch.

• floorplan_np (int): Number of parallel floorplan jobs to launch.

• place_np (int): Number of parallel placement jobs to launch.

• cts_np (int): Number of parallel clock tree synthesis jobs to launch.

• route_np (int): Number of parallel routing jobs to launch.

File: asicflow.py

2.1.5.1. Graph

2.1.5.2. Nodes

2.1.5.2.1. convert/0

Keypath	Type	Value
[flowgraph,asicflow-hls,convert,0,task]	str	convert
[flowgraph,asicflow-hls,convert,0,taskmodule]	str	siliconcompiler.tools.bambu.convert/ConvertTask
[flowgraph,asicflow-hls,convert,0,tool]	str	bambu

2.1.5.2.2. synthesis/0

Keypath	Type	Value
[flowgraph,asicflow-hls,synthesis,0,goal,errors]	float	0.0
[flowgraph,asicflow-hls,synthesis,0,input]	[(str,str)]	('convert', '0')
[flowgraph,asicflow-hls,synthesis,0,task]	str	syn_asic
[flowgraph,asicflow-hls,synthesis,0,taskmodule]	str	siliconcompiler.tools.yosys.syn_asic/ASICSynthesis
[flowgraph,asicflow-hls,synthesis,0,tool]	str	yosys

2.1.5.2.3. synthesis/1

Keypath	Type	Value
[flowgraph,asicflow-hls,synthesis,1,goal,errors]	float	0.0
[flowgraph,asicflow-hls,synthesis,1,input]	[(str,str)]	('convert', '0')
[flowgraph,asicflow-hls,synthesis,1,task]	str	syn_asic
[flowgraph,asicflow-hls,synthesis,1,taskmodule]	str	siliconcompiler.tools.yosys.syn_asic/ASICSynthesis
[flowgraph,asicflow-hls,synthesis,1,tool]	str	yosys

2.1.5.2.4. synthesis/2

Keypath	Type	Value
[flowgraph,asicflow-hls,synthesis,2,goal,errors]	float	0.0
[flowgraph,asicflow-hls,synthesis,2,input]	[(str,str)]	('convert', '0')
[flowgraph,asicflow-hls,synthesis,2,task]	str	syn_asic
[flowgraph,asicflow-hls,synthesis,2,taskmodule]	str	siliconcompiler.tools.yosys.syn_asic/ASICSynthesis
[flowgraph,asicflow-hls,synthesis,2,tool]	str	yosys

2.1.5.2.5. synthesis.min/0

Keypath	Type	Value
[flowgraph,asicflow-hls,synthesis.min,0,input]	[(str,str)]	('synthesis', '0') ('synthesis', '1') ('synthesis', '2')
[flowgraph,asicflow-hls,synthesis.min,0,task]	str	minimum
[flowgraph,asicflow-hls,synthesis.min,0,taskmodule]	str	siliconcompiler.tools.builtin.minimum/MinimumTask
[flowgraph,asicflow-hls,synthesis.min,0,tool]	str	builtin

2.1.5.2.6. cleanup.clean/0

Keypath	Type	Value
[flowgraph,asicflow-hls,cleanup.clean,0,input]	[(str,str)]	('synthesis.min', '0')
[flowgraph,asicflow-hls,cleanup.clean,0,task]	str	cleanup_synth
[flowgraph,asicflow-hls,cleanup.clean,0,taskmodule]	str	siliconcompiler.tools.openroad.synth_cleanup/CleanupSynthTask
[flowgraph,asicflow-hls,cleanup.clean,0,tool]	str	openroad

2.1.5.2.7. synthesis.timing/0

Keypath	Type	Value
[flowgraph,asicflow-hls,synthesis.timing,0,input]	[(str,str)]	('synthesis.min', '0')
[flowgraph,asicflow-hls,synthesis.timing,0,task]	str	timing
[flowgraph,asicflow-hls,synthesis.timing,0,taskmodule]	str	siliconcompiler.tools.opensta.timing/TimingTask
[flowgraph,asicflow-hls,synthesis.timing,0,tool]	str	opensta

2.1.5.2.8. floorplan.init/0

Keypath	Type	Value
[flowgraph,asicflow-hls,floorplan.init,0,input]	[(str,str)]	('cleanup.clean', '0')
[flowgraph,asicflow-hls,floorplan.init,0,task]	str	init_floorplan
[flowgraph,asicflow-hls,floorplan.init,0,taskmodule]	str	siliconcompiler.tools.openroad.init_floorplan/InitFloorplanTask
[flowgraph,asicflow-hls,floorplan.init,0,tool]	str	openroad

2.1.5.2.9. floorplan.init/1

Keypath	Type	Value
[flowgraph,asicflow-hls,floorplan.init,1,input]	[(str,str)]	('cleanup.clean', '0')
[flowgraph,asicflow-hls,floorplan.init,1,task]	str	init_floorplan
[flowgraph,asicflow-hls,floorplan.init,1,taskmodule]	str	siliconcompiler.tools.openroad.init_floorplan/InitFloorplanTask
[flowgraph,asicflow-hls,floorplan.init,1,tool]	str	openroad

2.1.5.2.10. floorplan.init/2

Keypath	Type	Value
[flowgraph,asicflow-hls,floorplan.init,2,input]	[(str,str)]	('cleanup.clean', '0')
[flowgraph,asicflow-hls,floorplan.init,2,task]	str	init_floorplan
[flowgraph,asicflow-hls,floorplan.init,2,taskmodule]	str	siliconcompiler.tools.openroad.init_floorplan/InitFloorplanTask
[flowgraph,asicflow-hls,floorplan.init,2,tool]	str	openroad

2.1.5.2.11. floorplan.macro_placement/0

Keypath	Type	Value
[flowgraph,asicflow-hls,floorplan.macro_placement,0,input]	[(str,str)]	('floorplan.init', '0')
[flowgraph,asicflow-hls,floorplan.macro_placement,0,task]	str	macro_placement
[flowgraph,asicflow-hls,floorplan.macro_placement,0,taskmodule]	str	siliconcompiler.tools.openroad.macro_placement/MacroPlacementTask
[flowgraph,asicflow-hls,floorplan.macro_placement,0,tool]	str	openroad

2.1.5.2.12. floorplan.macro_placement/1

Keypath	Type	Value
[flowgraph,asicflow-hls,floorplan.macro_placement,1,input]	[(str,str)]	('floorplan.init', '1')
[flowgraph,asicflow-hls,floorplan.macro_placement,1,task]	str	macro_placement
[flowgraph,asicflow-hls,floorplan.macro_placement,1,taskmodule]	str	siliconcompiler.tools.openroad.macro_placement/MacroPlacementTask
[flowgraph,asicflow-hls,floorplan.macro_placement,1,tool]	str	openroad

2.1.5.2.13. floorplan.macro_placement/2

Keypath	Type	Value
[flowgraph,asicflow-hls,floorplan.macro_placement,2,input]	[(str,str)]	('floorplan.init', '2')
[flowgraph,asicflow-hls,floorplan.macro_placement,2,task]	str	macro_placement
[flowgraph,asicflow-hls,floorplan.macro_placement,2,taskmodule]	str	siliconcompiler.tools.openroad.macro_placement/MacroPlacementTask
[flowgraph,asicflow-hls,floorplan.macro_placement,2,tool]	str	openroad

2.1.5.2.14. floorplan.tapcell/0

Keypath	Type	Value
[flowgraph,asicflow-hls,floorplan.tapcell,0,input]	[(str,str)]	('floorplan.macro_placement', '0')
[flowgraph,asicflow-hls,floorplan.tapcell,0,task]	str	endcap_tapcell_insertion
[flowgraph,asicflow-hls,floorplan.tapcell,0,taskmodule]	str	siliconcompiler.tools.openroad.endcap_tapcell_insertion/EndCapTapCellTask
[flowgraph,asicflow-hls,floorplan.tapcell,0,tool]	str	openroad

2.1.5.2.15. floorplan.tapcell/1

Keypath	Type	Value
[flowgraph,asicflow-hls,floorplan.tapcell,1,input]	[(str,str)]	('floorplan.macro_placement', '1')
[flowgraph,asicflow-hls,floorplan.tapcell,1,task]	str	endcap_tapcell_insertion
[flowgraph,asicflow-hls,floorplan.tapcell,1,taskmodule]	str	siliconcompiler.tools.openroad.endcap_tapcell_insertion/EndCapTapCellTask
[flowgraph,asicflow-hls,floorplan.tapcell,1,tool]	str	openroad

2.1.5.2.16. floorplan.tapcell/2

Keypath	Type	Value
[flowgraph,asicflow-hls,floorplan.tapcell,2,input]	[(str,str)]	('floorplan.macro_placement', '2')
[flowgraph,asicflow-hls,floorplan.tapcell,2,task]	str	endcap_tapcell_insertion
[flowgraph,asicflow-hls,floorplan.tapcell,2,taskmodule]	str	siliconcompiler.tools.openroad.endcap_tapcell_insertion/EndCapTapCellTask
[flowgraph,asicflow-hls,floorplan.tapcell,2,tool]	str	openroad

2.1.5.2.17. floorplan.power_grid/0

Keypath	Type	Value
[flowgraph,asicflow-hls,floorplan.power_grid,0,input]	[(str,str)]	('floorplan.tapcell', '0')
[flowgraph,asicflow-hls,floorplan.power_grid,0,task]	str	power_grid
[flowgraph,asicflow-hls,floorplan.power_grid,0,taskmodule]	str	siliconcompiler.tools.openroad.power_grid/PowerGridTask
[flowgraph,asicflow-hls,floorplan.power_grid,0,tool]	str	openroad

2.1.5.2.18. floorplan.power_grid/1

Keypath	Type	Value
[flowgraph,asicflow-hls,floorplan.power_grid,1,input]	[(str,str)]	('floorplan.tapcell', '1')
[flowgraph,asicflow-hls,floorplan.power_grid,1,task]	str	power_grid
[flowgraph,asicflow-hls,floorplan.power_grid,1,taskmodule]	str	siliconcompiler.tools.openroad.power_grid/PowerGridTask
[flowgraph,asicflow-hls,floorplan.power_grid,1,tool]	str	openroad

2.1.5.2.19. floorplan.power_grid/2

Keypath	Type	Value
[flowgraph,asicflow-hls,floorplan.power_grid,2,input]	[(str,str)]	('floorplan.tapcell', '2')
[flowgraph,asicflow-hls,floorplan.power_grid,2,task]	str	power_grid
[flowgraph,asicflow-hls,floorplan.power_grid,2,taskmodule]	str	siliconcompiler.tools.openroad.power_grid/PowerGridTask
[flowgraph,asicflow-hls,floorplan.power_grid,2,tool]	str	openroad

2.1.5.2.20. floorplan.pin_placement/0

Keypath	Type	Value
[flowgraph,asicflow-hls,floorplan.pin_placement,0,input]	[(str,str)]	('floorplan.power_grid', '0')
[flowgraph,asicflow-hls,floorplan.pin_placement,0,task]	str	pin_placement
[flowgraph,asicflow-hls,floorplan.pin_placement,0,taskmodule]	str	siliconcompiler.tools.openroad.pin_placement/PinPlacementTask
[flowgraph,asicflow-hls,floorplan.pin_placement,0,tool]	str	openroad

2.1.5.2.21. floorplan.pin_placement/1

Keypath	Type	Value
[flowgraph,asicflow-hls,floorplan.pin_placement,1,input]	[(str,str)]	('floorplan.power_grid', '1')
[flowgraph,asicflow-hls,floorplan.pin_placement,1,task]	str	pin_placement
[flowgraph,asicflow-hls,floorplan.pin_placement,1,taskmodule]	str	siliconcompiler.tools.openroad.pin_placement/PinPlacementTask
[flowgraph,asicflow-hls,floorplan.pin_placement,1,tool]	str	openroad

2.1.5.2.22. floorplan.pin_placement/2

Keypath	Type	Value
[flowgraph,asicflow-hls,floorplan.pin_placement,2,input]	[(str,str)]	('floorplan.power_grid', '2')
[flowgraph,asicflow-hls,floorplan.pin_placement,2,task]	str	pin_placement
[flowgraph,asicflow-hls,floorplan.pin_placement,2,taskmodule]	str	siliconcompiler.tools.openroad.pin_placement/PinPlacementTask
[flowgraph,asicflow-hls,floorplan.pin_placement,2,tool]	str	openroad

2.1.5.2.23. floorplan.min/0

Keypath	Type	Value
[flowgraph,asicflow-hls,floorplan.min,0,input]	[(str,str)]	('floorplan.pin_placement', '0') ('floorplan.pin_placement', '1') ('floorplan.pin_placement', '2')
[flowgraph,asicflow-hls,floorplan.min,0,task]	str	minimum
[flowgraph,asicflow-hls,floorplan.min,0,taskmodule]	str	siliconcompiler.tools.builtin.minimum/MinimumTask
[flowgraph,asicflow-hls,floorplan.min,0,tool]	str	builtin

2.1.5.2.24. place.global/0

Keypath	Type	Value
[flowgraph,asicflow-hls,place.global,0,input]	[(str,str)]	('floorplan.min', '0')
[flowgraph,asicflow-hls,place.global,0,task]	str	global_placement
[flowgraph,asicflow-hls,place.global,0,taskmodule]	str	siliconcompiler.tools.openroad.global_placement/GlobalPlacementTask
[flowgraph,asicflow-hls,place.global,0,tool]	str	openroad

2.1.5.2.25. place.global/1

Keypath	Type	Value
[flowgraph,asicflow-hls,place.global,1,input]	[(str,str)]	('floorplan.min', '0')
[flowgraph,asicflow-hls,place.global,1,task]	str	global_placement
[flowgraph,asicflow-hls,place.global,1,taskmodule]	str	siliconcompiler.tools.openroad.global_placement/GlobalPlacementTask
[flowgraph,asicflow-hls,place.global,1,tool]	str	openroad

2.1.5.2.26. place.global/2

Keypath	Type	Value
[flowgraph,asicflow-hls,place.global,2,input]	[(str,str)]	('floorplan.min', '0')
[flowgraph,asicflow-hls,place.global,2,task]	str	global_placement
[flowgraph,asicflow-hls,place.global,2,taskmodule]	str	siliconcompiler.tools.openroad.global_placement/GlobalPlacementTask
[flowgraph,asicflow-hls,place.global,2,tool]	str	openroad

2.1.5.2.27. place.repair_design/0

Keypath	Type	Value
[flowgraph,asicflow-hls,place.repair_design,0,input]	[(str,str)]	('place.global', '0')
[flowgraph,asicflow-hls,place.repair_design,0,task]	str	repair_design
[flowgraph,asicflow-hls,place.repair_design,0,taskmodule]	str	siliconcompiler.tools.openroad.repair_design/RepairDesignTask
[flowgraph,asicflow-hls,place.repair_design,0,tool]	str	openroad

2.1.5.2.28. place.repair_design/1

Keypath	Type	Value
[flowgraph,asicflow-hls,place.repair_design,1,input]	[(str,str)]	('place.global', '1')
[flowgraph,asicflow-hls,place.repair_design,1,task]	str	repair_design
[flowgraph,asicflow-hls,place.repair_design,1,taskmodule]	str	siliconcompiler.tools.openroad.repair_design/RepairDesignTask
[flowgraph,asicflow-hls,place.repair_design,1,tool]	str	openroad

2.1.5.2.29. place.repair_design/2

Keypath	Type	Value
[flowgraph,asicflow-hls,place.repair_design,2,input]	[(str,str)]	('place.global', '2')
[flowgraph,asicflow-hls,place.repair_design,2,task]	str	repair_design
[flowgraph,asicflow-hls,place.repair_design,2,taskmodule]	str	siliconcompiler.tools.openroad.repair_design/RepairDesignTask
[flowgraph,asicflow-hls,place.repair_design,2,tool]	str	openroad

2.1.5.2.30. place.detailed/0

Keypath	Type	Value
[flowgraph,asicflow-hls,place.detailed,0,input]	[(str,str)]	('place.repair_design', '0')
[flowgraph,asicflow-hls,place.detailed,0,task]	str	detailed_placement
[flowgraph,asicflow-hls,place.detailed,0,taskmodule]	str	siliconcompiler.tools.openroad.detailed_placement/DetailedPlacementTask
[flowgraph,asicflow-hls,place.detailed,0,tool]	str	openroad

2.1.5.2.31. place.detailed/1

Keypath	Type	Value
[flowgraph,asicflow-hls,place.detailed,1,input]	[(str,str)]	('place.repair_design', '1')
[flowgraph,asicflow-hls,place.detailed,1,task]	str	detailed_placement
[flowgraph,asicflow-hls,place.detailed,1,taskmodule]	str	siliconcompiler.tools.openroad.detailed_placement/DetailedPlacementTask
[flowgraph,asicflow-hls,place.detailed,1,tool]	str	openroad

2.1.5.2.32. place.detailed/2

Keypath	Type	Value
[flowgraph,asicflow-hls,place.detailed,2,input]	[(str,str)]	('place.repair_design', '2')
[flowgraph,asicflow-hls,place.detailed,2,task]	str	detailed_placement
[flowgraph,asicflow-hls,place.detailed,2,taskmodule]	str	siliconcompiler.tools.openroad.detailed_placement/DetailedPlacementTask
[flowgraph,asicflow-hls,place.detailed,2,tool]	str	openroad

2.1.5.2.33. place.min/0

Keypath	Type	Value
[flowgraph,asicflow-hls,place.min,0,input]	[(str,str)]	('place.detailed', '0') ('place.detailed', '1') ('place.detailed', '2')
[flowgraph,asicflow-hls,place.min,0,task]	str	minimum
[flowgraph,asicflow-hls,place.min,0,taskmodule]	str	siliconcompiler.tools.builtin.minimum/MinimumTask
[flowgraph,asicflow-hls,place.min,0,tool]	str	builtin

2.1.5.2.34. cts.clock_tree_synthesis/0

Keypath	Type	Value
[flowgraph,asicflow-hls,cts.clock_tree_synthesis,0,input]	[(str,str)]	('place.min', '0')
[flowgraph,asicflow-hls,cts.clock_tree_synthesis,0,task]	str	clock_tree_synthesis
[flowgraph,asicflow-hls,cts.clock_tree_synthesis,0,taskmodule]	str	siliconcompiler.tools.openroad.clock_tree_synthesis/CTSTask
[flowgraph,asicflow-hls,cts.clock_tree_synthesis,0,tool]	str	openroad

2.1.5.2.35. cts.clock_tree_synthesis/1

Keypath	Type	Value
[flowgraph,asicflow-hls,cts.clock_tree_synthesis,1,input]	[(str,str)]	('place.min', '0')
[flowgraph,asicflow-hls,cts.clock_tree_synthesis,1,task]	str	clock_tree_synthesis
[flowgraph,asicflow-hls,cts.clock_tree_synthesis,1,taskmodule]	str	siliconcompiler.tools.openroad.clock_tree_synthesis/CTSTask
[flowgraph,asicflow-hls,cts.clock_tree_synthesis,1,tool]	str	openroad

2.1.5.2.36. cts.clock_tree_synthesis/2

Keypath	Type	Value
[flowgraph,asicflow-hls,cts.clock_tree_synthesis,2,input]	[(str,str)]	('place.min', '0')
[flowgraph,asicflow-hls,cts.clock_tree_synthesis,2,task]	str	clock_tree_synthesis
[flowgraph,asicflow-hls,cts.clock_tree_synthesis,2,taskmodule]	str	siliconcompiler.tools.openroad.clock_tree_synthesis/CTSTask
[flowgraph,asicflow-hls,cts.clock_tree_synthesis,2,tool]	str	openroad

2.1.5.2.37. cts.repair_timing/0

Keypath	Type	Value
[flowgraph,asicflow-hls,cts.repair_timing,0,input]	[(str,str)]	('cts.clock_tree_synthesis', '0')
[flowgraph,asicflow-hls,cts.repair_timing,0,task]	str	repair_timing
[flowgraph,asicflow-hls,cts.repair_timing,0,taskmodule]	str	siliconcompiler.tools.openroad.repair_timing/RepairTimingTask
[flowgraph,asicflow-hls,cts.repair_timing,0,tool]	str	openroad

2.1.5.2.38. cts.repair_timing/1

Keypath	Type	Value
[flowgraph,asicflow-hls,cts.repair_timing,1,input]	[(str,str)]	('cts.clock_tree_synthesis', '1')
[flowgraph,asicflow-hls,cts.repair_timing,1,task]	str	repair_timing
[flowgraph,asicflow-hls,cts.repair_timing,1,taskmodule]	str	siliconcompiler.tools.openroad.repair_timing/RepairTimingTask
[flowgraph,asicflow-hls,cts.repair_timing,1,tool]	str	openroad

2.1.5.2.39. cts.repair_timing/2

Keypath	Type	Value
[flowgraph,asicflow-hls,cts.repair_timing,2,input]	[(str,str)]	('cts.clock_tree_synthesis', '2')
[flowgraph,asicflow-hls,cts.repair_timing,2,task]	str	repair_timing
[flowgraph,asicflow-hls,cts.repair_timing,2,taskmodule]	str	siliconcompiler.tools.openroad.repair_timing/RepairTimingTask
[flowgraph,asicflow-hls,cts.repair_timing,2,tool]	str	openroad

2.1.5.2.40. cts.min/0

Keypath	Type	Value
[flowgraph,asicflow-hls,cts.min,0,input]	[(str,str)]	('cts.repair_timing', '0') ('cts.repair_timing', '1') ('cts.repair_timing', '2')
[flowgraph,asicflow-hls,cts.min,0,task]	str	minimum
[flowgraph,asicflow-hls,cts.min,0,taskmodule]	str	siliconcompiler.tools.builtin.minimum/MinimumTask
[flowgraph,asicflow-hls,cts.min,0,tool]	str	builtin

2.1.5.2.41. cts.fillcell/0

Keypath	Type	Value
[flowgraph,asicflow-hls,cts.fillcell,0,input]	[(str,str)]	('cts.min', '0')
[flowgraph,asicflow-hls,cts.fillcell,0,task]	str	fillercell_insertion
[flowgraph,asicflow-hls,cts.fillcell,0,taskmodule]	str	siliconcompiler.tools.openroad.fillercell_insertion/FillCellTask
[flowgraph,asicflow-hls,cts.fillcell,0,tool]	str	openroad

2.1.5.2.42. route.global/0

Keypath	Type	Value
[flowgraph,asicflow-hls,route.global,0,input]	[(str,str)]	('cts.fillcell', '0')
[flowgraph,asicflow-hls,route.global,0,task]	str	global_route
[flowgraph,asicflow-hls,route.global,0,taskmodule]	str	siliconcompiler.tools.openroad.global_route/GlobalRouteTask
[flowgraph,asicflow-hls,route.global,0,tool]	str	openroad

2.1.5.2.43. route.global/1

Keypath	Type	Value
[flowgraph,asicflow-hls,route.global,1,input]	[(str,str)]	('cts.fillcell', '0')
[flowgraph,asicflow-hls,route.global,1,task]	str	global_route
[flowgraph,asicflow-hls,route.global,1,taskmodule]	str	siliconcompiler.tools.openroad.global_route/GlobalRouteTask
[flowgraph,asicflow-hls,route.global,1,tool]	str	openroad

2.1.5.2.44. route.global/2

Keypath	Type	Value
[flowgraph,asicflow-hls,route.global,2,input]	[(str,str)]	('cts.fillcell', '0')
[flowgraph,asicflow-hls,route.global,2,task]	str	global_route
[flowgraph,asicflow-hls,route.global,2,taskmodule]	str	siliconcompiler.tools.openroad.global_route/GlobalRouteTask
[flowgraph,asicflow-hls,route.global,2,tool]	str	openroad

2.1.5.2.45. route.antenna_repair/0

Keypath	Type	Value
[flowgraph,asicflow-hls,route.antenna_repair,0,input]	[(str,str)]	('route.global', '0')
[flowgraph,asicflow-hls,route.antenna_repair,0,task]	str	antenna_repair
[flowgraph,asicflow-hls,route.antenna_repair,0,taskmodule]	str	siliconcompiler.tools.openroad.antenna_repair/AntennaRepairTask
[flowgraph,asicflow-hls,route.antenna_repair,0,tool]	str	openroad

2.1.5.2.46. route.antenna_repair/1

Keypath	Type	Value
[flowgraph,asicflow-hls,route.antenna_repair,1,input]	[(str,str)]	('route.global', '1')
[flowgraph,asicflow-hls,route.antenna_repair,1,task]	str	antenna_repair
[flowgraph,asicflow-hls,route.antenna_repair,1,taskmodule]	str	siliconcompiler.tools.openroad.antenna_repair/AntennaRepairTask
[flowgraph,asicflow-hls,route.antenna_repair,1,tool]	str	openroad

2.1.5.2.47. route.antenna_repair/2

Keypath	Type	Value
[flowgraph,asicflow-hls,route.antenna_repair,2,input]	[(str,str)]	('route.global', '2')
[flowgraph,asicflow-hls,route.antenna_repair,2,task]	str	antenna_repair
[flowgraph,asicflow-hls,route.antenna_repair,2,taskmodule]	str	siliconcompiler.tools.openroad.antenna_repair/AntennaRepairTask
[flowgraph,asicflow-hls,route.antenna_repair,2,tool]	str	openroad

2.1.5.2.48. route.detailed/0

Keypath	Type	Value
[flowgraph,asicflow-hls,route.detailed,0,input]	[(str,str)]	('route.antenna_repair', '0')
[flowgraph,asicflow-hls,route.detailed,0,task]	str	detailed_route
[flowgraph,asicflow-hls,route.detailed,0,taskmodule]	str	siliconcompiler.tools.openroad.detailed_route/DetailedRouteTask
[flowgraph,asicflow-hls,route.detailed,0,tool]	str	openroad

2.1.5.2.49. route.detailed/1

Keypath	Type	Value
[flowgraph,asicflow-hls,route.detailed,1,input]	[(str,str)]	('route.antenna_repair', '1')
[flowgraph,asicflow-hls,route.detailed,1,task]	str	detailed_route
[flowgraph,asicflow-hls,route.detailed,1,taskmodule]	str	siliconcompiler.tools.openroad.detailed_route/DetailedRouteTask
[flowgraph,asicflow-hls,route.detailed,1,tool]	str	openroad

2.1.5.2.50. route.detailed/2

Keypath	Type	Value
[flowgraph,asicflow-hls,route.detailed,2,input]	[(str,str)]	('route.antenna_repair', '2')
[flowgraph,asicflow-hls,route.detailed,2,task]	str	detailed_route
[flowgraph,asicflow-hls,route.detailed,2,taskmodule]	str	siliconcompiler.tools.openroad.detailed_route/DetailedRouteTask
[flowgraph,asicflow-hls,route.detailed,2,tool]	str	openroad

2.1.5.2.51. route.min/0

Keypath	Type	Value
[flowgraph,asicflow-hls,route.min,0,input]	[(str,str)]	('route.detailed', '0') ('route.detailed', '1') ('route.detailed', '2')
[flowgraph,asicflow-hls,route.min,0,task]	str	minimum
[flowgraph,asicflow-hls,route.min,0,taskmodule]	str	siliconcompiler.tools.builtin.minimum/MinimumTask
[flowgraph,asicflow-hls,route.min,0,tool]	str	builtin

2.1.5.2.52. dfm.metal_fill/0

Keypath	Type	Value
[flowgraph,asicflow-hls,dfm.metal_fill,0,input]	[(str,str)]	('route.min', '0')
[flowgraph,asicflow-hls,dfm.metal_fill,0,task]	str	fillmetal_insertion
[flowgraph,asicflow-hls,dfm.metal_fill,0,taskmodule]	str	siliconcompiler.tools.openroad.fillmetal_insertion/FillMetalTask
[flowgraph,asicflow-hls,dfm.metal_fill,0,tool]	str	openroad

2.1.5.2.53. write.gds/0

Keypath	Type	Value
[flowgraph,asicflow-hls,write.gds,0,input]	[(str,str)]	('dfm.metal_fill', '0')
[flowgraph,asicflow-hls,write.gds,0,task]	str	export
[flowgraph,asicflow-hls,write.gds,0,taskmodule]	str	siliconcompiler.tools.klayout.export/ExportTask
[flowgraph,asicflow-hls,write.gds,0,tool]	str	klayout

2.1.5.2.54. write.views/0

Keypath	Type	Value
[flowgraph,asicflow-hls,write.views,0,input]	[(str,str)]	('dfm.metal_fill', '0')
[flowgraph,asicflow-hls,write.views,0,task]	str	write_data
[flowgraph,asicflow-hls,write.views,0,taskmodule]	str	siliconcompiler.tools.openroad.write_data/WriteViewsTask
[flowgraph,asicflow-hls,write.views,0,tool]	str	openroad

2.1.6. asicflow-bluespec / 5

A configurable ASIC compilation flow.

This flow targets ASIC designs, taking RTL through a complete synthesis, place-and-route, and finishing flow.

The flow is divided into the following major steps:

• elaborate: RTL elaboration using Slang.

• synthesis: RTL synthesis using Yosys.

• floorplan: Floorplanning, including macro placement, tapcell/endcap insertion, power grid generation, and pin placement.

• place: Global and detailed placement.

• cts: Clock tree synthesis and post-CTS timing repair.

• route: Global and detailed routing.

• dfm: Design-for-manufacturing steps, primarily metal fill.

• write: Writing out final views of the design (GDSII, etc.).

The synthesis, floorplan, place, cts, and route steps support parallel execution to explore different strategies. This can be configured by setting the corresponding *_np argument to a value greater than 1.

Args:

• name (str, optional): The name of the flow. If not provided, it defaults to ‘asicflow-<language>’.

• language (str): The hardware description language of the design. One of ‘verilog’, ‘systemverilog’, ‘systemverilog-sv2v’, ‘chisel’, ‘vhdl’, or ‘hls’.

• syn_np (int): Number of parallel synthesis jobs to launch.

• floorplan_np (int): Number of parallel floorplan jobs to launch.

• place_np (int): Number of parallel placement jobs to launch.

• cts_np (int): Number of parallel clock tree synthesis jobs to launch.

• route_np (int): Number of parallel routing jobs to launch.

File: asicflow.py

2.1.6.1. Graph

2.1.6.2. Nodes

2.1.6.2.1. convert/0

Keypath	Type	Value
[flowgraph,asicflow-bluespec,convert,0,task]	str	convert
[flowgraph,asicflow-bluespec,convert,0,taskmodule]	str	siliconcompiler.tools.bluespec.convert/ConvertTask
[flowgraph,asicflow-bluespec,convert,0,tool]	str	bluespec

2.1.6.2.2. synthesis/0

Keypath	Type	Value
[flowgraph,asicflow-bluespec,synthesis,0,goal,errors]	float	0.0
[flowgraph,asicflow-bluespec,synthesis,0,input]	[(str,str)]	('convert', '0')
[flowgraph,asicflow-bluespec,synthesis,0,task]	str	syn_asic
[flowgraph,asicflow-bluespec,synthesis,0,taskmodule]	str	siliconcompiler.tools.yosys.syn_asic/ASICSynthesis
[flowgraph,asicflow-bluespec,synthesis,0,tool]	str	yosys

2.1.6.2.3. synthesis/1

Keypath	Type	Value
[flowgraph,asicflow-bluespec,synthesis,1,goal,errors]	float	0.0
[flowgraph,asicflow-bluespec,synthesis,1,input]	[(str,str)]	('convert', '0')
[flowgraph,asicflow-bluespec,synthesis,1,task]	str	syn_asic
[flowgraph,asicflow-bluespec,synthesis,1,taskmodule]	str	siliconcompiler.tools.yosys.syn_asic/ASICSynthesis
[flowgraph,asicflow-bluespec,synthesis,1,tool]	str	yosys

2.1.6.2.4. synthesis/2

Keypath	Type	Value
[flowgraph,asicflow-bluespec,synthesis,2,goal,errors]	float	0.0
[flowgraph,asicflow-bluespec,synthesis,2,input]	[(str,str)]	('convert', '0')
[flowgraph,asicflow-bluespec,synthesis,2,task]	str	syn_asic
[flowgraph,asicflow-bluespec,synthesis,2,taskmodule]	str	siliconcompiler.tools.yosys.syn_asic/ASICSynthesis
[flowgraph,asicflow-bluespec,synthesis,2,tool]	str	yosys

2.1.6.2.5. synthesis.min/0

Keypath	Type	Value
[flowgraph,asicflow-bluespec,synthesis.min,0,input]	[(str,str)]	('synthesis', '0') ('synthesis', '1') ('synthesis', '2')
[flowgraph,asicflow-bluespec,synthesis.min,0,task]	str	minimum
[flowgraph,asicflow-bluespec,synthesis.min,0,taskmodule]	str	siliconcompiler.tools.builtin.minimum/MinimumTask
[flowgraph,asicflow-bluespec,synthesis.min,0,tool]	str	builtin

2.1.6.2.6. cleanup.clean/0

Keypath	Type	Value
[flowgraph,asicflow-bluespec,cleanup.clean,0,input]	[(str,str)]	('synthesis.min', '0')
[flowgraph,asicflow-bluespec,cleanup.clean,0,task]	str	cleanup_synth
[flowgraph,asicflow-bluespec,cleanup.clean,0,taskmodule]	str	siliconcompiler.tools.openroad.synth_cleanup/CleanupSynthTask
[flowgraph,asicflow-bluespec,cleanup.clean,0,tool]	str	openroad

2.1.6.2.7. synthesis.timing/0

Keypath	Type	Value
[flowgraph,asicflow-bluespec,synthesis.timing,0,input]	[(str,str)]	('synthesis.min', '0')
[flowgraph,asicflow-bluespec,synthesis.timing,0,task]	str	timing
[flowgraph,asicflow-bluespec,synthesis.timing,0,taskmodule]	str	siliconcompiler.tools.opensta.timing/TimingTask
[flowgraph,asicflow-bluespec,synthesis.timing,0,tool]	str	opensta

2.1.6.2.8. floorplan.init/0

Keypath	Type	Value
[flowgraph,asicflow-bluespec,floorplan.init,0,input]	[(str,str)]	('cleanup.clean', '0')
[flowgraph,asicflow-bluespec,floorplan.init,0,task]	str	init_floorplan
[flowgraph,asicflow-bluespec,floorplan.init,0,taskmodule]	str	siliconcompiler.tools.openroad.init_floorplan/InitFloorplanTask
[flowgraph,asicflow-bluespec,floorplan.init,0,tool]	str	openroad

2.1.6.2.9. floorplan.init/1

Keypath	Type	Value
[flowgraph,asicflow-bluespec,floorplan.init,1,input]	[(str,str)]	('cleanup.clean', '0')
[flowgraph,asicflow-bluespec,floorplan.init,1,task]	str	init_floorplan
[flowgraph,asicflow-bluespec,floorplan.init,1,taskmodule]	str	siliconcompiler.tools.openroad.init_floorplan/InitFloorplanTask
[flowgraph,asicflow-bluespec,floorplan.init,1,tool]	str	openroad

2.1.6.2.10. floorplan.init/2

Keypath	Type	Value
[flowgraph,asicflow-bluespec,floorplan.init,2,input]	[(str,str)]	('cleanup.clean', '0')
[flowgraph,asicflow-bluespec,floorplan.init,2,task]	str	init_floorplan
[flowgraph,asicflow-bluespec,floorplan.init,2,taskmodule]	str	siliconcompiler.tools.openroad.init_floorplan/InitFloorplanTask
[flowgraph,asicflow-bluespec,floorplan.init,2,tool]	str	openroad

2.1.6.2.11. floorplan.macro_placement/0

Keypath	Type	Value
[flowgraph,asicflow-bluespec,floorplan.macro_placement,0,input]	[(str,str)]	('floorplan.init', '0')
[flowgraph,asicflow-bluespec,floorplan.macro_placement,0,task]	str	macro_placement
[flowgraph,asicflow-bluespec,floorplan.macro_placement,0,taskmodule]	str	siliconcompiler.tools.openroad.macro_placement/MacroPlacementTask
[flowgraph,asicflow-bluespec,floorplan.macro_placement,0,tool]	str	openroad

2.1.6.2.12. floorplan.macro_placement/1

Keypath	Type	Value
[flowgraph,asicflow-bluespec,floorplan.macro_placement,1,input]	[(str,str)]	('floorplan.init', '1')
[flowgraph,asicflow-bluespec,floorplan.macro_placement,1,task]	str	macro_placement
[flowgraph,asicflow-bluespec,floorplan.macro_placement,1,taskmodule]	str	siliconcompiler.tools.openroad.macro_placement/MacroPlacementTask
[flowgraph,asicflow-bluespec,floorplan.macro_placement,1,tool]	str	openroad

2.1.6.2.13. floorplan.macro_placement/2

Keypath	Type	Value
[flowgraph,asicflow-bluespec,floorplan.macro_placement,2,input]	[(str,str)]	('floorplan.init', '2')
[flowgraph,asicflow-bluespec,floorplan.macro_placement,2,task]	str	macro_placement
[flowgraph,asicflow-bluespec,floorplan.macro_placement,2,taskmodule]	str	siliconcompiler.tools.openroad.macro_placement/MacroPlacementTask
[flowgraph,asicflow-bluespec,floorplan.macro_placement,2,tool]	str	openroad

2.1.6.2.14. floorplan.tapcell/0

Keypath	Type	Value
[flowgraph,asicflow-bluespec,floorplan.tapcell,0,input]	[(str,str)]	('floorplan.macro_placement', '0')
[flowgraph,asicflow-bluespec,floorplan.tapcell,0,task]	str	endcap_tapcell_insertion
[flowgraph,asicflow-bluespec,floorplan.tapcell,0,taskmodule]	str	siliconcompiler.tools.openroad.endcap_tapcell_insertion/EndCapTapCellTask
[flowgraph,asicflow-bluespec,floorplan.tapcell,0,tool]	str	openroad

2.1.6.2.15. floorplan.tapcell/1

Keypath	Type	Value
[flowgraph,asicflow-bluespec,floorplan.tapcell,1,input]	[(str,str)]	('floorplan.macro_placement', '1')
[flowgraph,asicflow-bluespec,floorplan.tapcell,1,task]	str	endcap_tapcell_insertion
[flowgraph,asicflow-bluespec,floorplan.tapcell,1,taskmodule]	str	siliconcompiler.tools.openroad.endcap_tapcell_insertion/EndCapTapCellTask
[flowgraph,asicflow-bluespec,floorplan.tapcell,1,tool]	str	openroad

2.1.6.2.16. floorplan.tapcell/2

Keypath	Type	Value
[flowgraph,asicflow-bluespec,floorplan.tapcell,2,input]	[(str,str)]	('floorplan.macro_placement', '2')
[flowgraph,asicflow-bluespec,floorplan.tapcell,2,task]	str	endcap_tapcell_insertion
[flowgraph,asicflow-bluespec,floorplan.tapcell,2,taskmodule]	str	siliconcompiler.tools.openroad.endcap_tapcell_insertion/EndCapTapCellTask
[flowgraph,asicflow-bluespec,floorplan.tapcell,2,tool]	str	openroad

2.1.6.2.17. floorplan.power_grid/0

Keypath	Type	Value
[flowgraph,asicflow-bluespec,floorplan.power_grid,0,input]	[(str,str)]	('floorplan.tapcell', '0')
[flowgraph,asicflow-bluespec,floorplan.power_grid,0,task]	str	power_grid
[flowgraph,asicflow-bluespec,floorplan.power_grid,0,taskmodule]	str	siliconcompiler.tools.openroad.power_grid/PowerGridTask
[flowgraph,asicflow-bluespec,floorplan.power_grid,0,tool]	str	openroad

2.1.6.2.18. floorplan.power_grid/1

Keypath	Type	Value
[flowgraph,asicflow-bluespec,floorplan.power_grid,1,input]	[(str,str)]	('floorplan.tapcell', '1')
[flowgraph,asicflow-bluespec,floorplan.power_grid,1,task]	str	power_grid
[flowgraph,asicflow-bluespec,floorplan.power_grid,1,taskmodule]	str	siliconcompiler.tools.openroad.power_grid/PowerGridTask
[flowgraph,asicflow-bluespec,floorplan.power_grid,1,tool]	str	openroad

2.1.6.2.19. floorplan.power_grid/2

Keypath	Type	Value
[flowgraph,asicflow-bluespec,floorplan.power_grid,2,input]	[(str,str)]	('floorplan.tapcell', '2')
[flowgraph,asicflow-bluespec,floorplan.power_grid,2,task]	str	power_grid
[flowgraph,asicflow-bluespec,floorplan.power_grid,2,taskmodule]	str	siliconcompiler.tools.openroad.power_grid/PowerGridTask
[flowgraph,asicflow-bluespec,floorplan.power_grid,2,tool]	str	openroad

2.1.6.2.20. floorplan.pin_placement/0

Keypath	Type	Value
[flowgraph,asicflow-bluespec,floorplan.pin_placement,0,input]	[(str,str)]	('floorplan.power_grid', '0')
[flowgraph,asicflow-bluespec,floorplan.pin_placement,0,task]	str	pin_placement
[flowgraph,asicflow-bluespec,floorplan.pin_placement,0,taskmodule]	str	siliconcompiler.tools.openroad.pin_placement/PinPlacementTask
[flowgraph,asicflow-bluespec,floorplan.pin_placement,0,tool]	str	openroad

2.1.6.2.21. floorplan.pin_placement/1

Keypath	Type	Value
[flowgraph,asicflow-bluespec,floorplan.pin_placement,1,input]	[(str,str)]	('floorplan.power_grid', '1')
[flowgraph,asicflow-bluespec,floorplan.pin_placement,1,task]	str	pin_placement
[flowgraph,asicflow-bluespec,floorplan.pin_placement,1,taskmodule]	str	siliconcompiler.tools.openroad.pin_placement/PinPlacementTask
[flowgraph,asicflow-bluespec,floorplan.pin_placement,1,tool]	str	openroad

2.1.6.2.22. floorplan.pin_placement/2

Keypath	Type	Value
[flowgraph,asicflow-bluespec,floorplan.pin_placement,2,input]	[(str,str)]	('floorplan.power_grid', '2')
[flowgraph,asicflow-bluespec,floorplan.pin_placement,2,task]	str	pin_placement
[flowgraph,asicflow-bluespec,floorplan.pin_placement,2,taskmodule]	str	siliconcompiler.tools.openroad.pin_placement/PinPlacementTask
[flowgraph,asicflow-bluespec,floorplan.pin_placement,2,tool]	str	openroad

2.1.6.2.23. floorplan.min/0

Keypath	Type	Value
[flowgraph,asicflow-bluespec,floorplan.min,0,input]	[(str,str)]	('floorplan.pin_placement', '0') ('floorplan.pin_placement', '1') ('floorplan.pin_placement', '2')
[flowgraph,asicflow-bluespec,floorplan.min,0,task]	str	minimum
[flowgraph,asicflow-bluespec,floorplan.min,0,taskmodule]	str	siliconcompiler.tools.builtin.minimum/MinimumTask
[flowgraph,asicflow-bluespec,floorplan.min,0,tool]	str	builtin

2.1.6.2.24. place.global/0

Keypath	Type	Value
[flowgraph,asicflow-bluespec,place.global,0,input]	[(str,str)]	('floorplan.min', '0')
[flowgraph,asicflow-bluespec,place.global,0,task]	str	global_placement
[flowgraph,asicflow-bluespec,place.global,0,taskmodule]	str	siliconcompiler.tools.openroad.global_placement/GlobalPlacementTask
[flowgraph,asicflow-bluespec,place.global,0,tool]	str	openroad

2.1.6.2.25. place.global/1

Keypath	Type	Value
[flowgraph,asicflow-bluespec,place.global,1,input]	[(str,str)]	('floorplan.min', '0')
[flowgraph,asicflow-bluespec,place.global,1,task]	str	global_placement
[flowgraph,asicflow-bluespec,place.global,1,taskmodule]	str	siliconcompiler.tools.openroad.global_placement/GlobalPlacementTask
[flowgraph,asicflow-bluespec,place.global,1,tool]	str	openroad

2.1.6.2.26. place.global/2

Keypath	Type	Value
[flowgraph,asicflow-bluespec,place.global,2,input]	[(str,str)]	('floorplan.min', '0')
[flowgraph,asicflow-bluespec,place.global,2,task]	str	global_placement
[flowgraph,asicflow-bluespec,place.global,2,taskmodule]	str	siliconcompiler.tools.openroad.global_placement/GlobalPlacementTask
[flowgraph,asicflow-bluespec,place.global,2,tool]	str	openroad

2.1.6.2.27. place.repair_design/0

Keypath	Type	Value
[flowgraph,asicflow-bluespec,place.repair_design,0,input]	[(str,str)]	('place.global', '0')
[flowgraph,asicflow-bluespec,place.repair_design,0,task]	str	repair_design
[flowgraph,asicflow-bluespec,place.repair_design,0,taskmodule]	str	siliconcompiler.tools.openroad.repair_design/RepairDesignTask
[flowgraph,asicflow-bluespec,place.repair_design,0,tool]	str	openroad

2.1.6.2.28. place.repair_design/1

Keypath	Type	Value
[flowgraph,asicflow-bluespec,place.repair_design,1,input]	[(str,str)]	('place.global', '1')
[flowgraph,asicflow-bluespec,place.repair_design,1,task]	str	repair_design
[flowgraph,asicflow-bluespec,place.repair_design,1,taskmodule]	str	siliconcompiler.tools.openroad.repair_design/RepairDesignTask
[flowgraph,asicflow-bluespec,place.repair_design,1,tool]	str	openroad

2.1.6.2.29. place.repair_design/2

Keypath	Type	Value
[flowgraph,asicflow-bluespec,place.repair_design,2,input]	[(str,str)]	('place.global', '2')
[flowgraph,asicflow-bluespec,place.repair_design,2,task]	str	repair_design
[flowgraph,asicflow-bluespec,place.repair_design,2,taskmodule]	str	siliconcompiler.tools.openroad.repair_design/RepairDesignTask
[flowgraph,asicflow-bluespec,place.repair_design,2,tool]	str	openroad

2.1.6.2.30. place.detailed/0

Keypath	Type	Value
[flowgraph,asicflow-bluespec,place.detailed,0,input]	[(str,str)]	('place.repair_design', '0')
[flowgraph,asicflow-bluespec,place.detailed,0,task]	str	detailed_placement
[flowgraph,asicflow-bluespec,place.detailed,0,taskmodule]	str	siliconcompiler.tools.openroad.detailed_placement/DetailedPlacementTask
[flowgraph,asicflow-bluespec,place.detailed,0,tool]	str	openroad

2.1.6.2.31. place.detailed/1

Keypath	Type	Value
[flowgraph,asicflow-bluespec,place.detailed,1,input]	[(str,str)]	('place.repair_design', '1')
[flowgraph,asicflow-bluespec,place.detailed,1,task]	str	detailed_placement
[flowgraph,asicflow-bluespec,place.detailed,1,taskmodule]	str	siliconcompiler.tools.openroad.detailed_placement/DetailedPlacementTask
[flowgraph,asicflow-bluespec,place.detailed,1,tool]	str	openroad

2.1.6.2.32. place.detailed/2

Keypath	Type	Value
[flowgraph,asicflow-bluespec,place.detailed,2,input]	[(str,str)]	('place.repair_design', '2')
[flowgraph,asicflow-bluespec,place.detailed,2,task]	str	detailed_placement
[flowgraph,asicflow-bluespec,place.detailed,2,taskmodule]	str	siliconcompiler.tools.openroad.detailed_placement/DetailedPlacementTask
[flowgraph,asicflow-bluespec,place.detailed,2,tool]	str	openroad

2.1.6.2.33. place.min/0

Keypath	Type	Value
[flowgraph,asicflow-bluespec,place.min,0,input]	[(str,str)]	('place.detailed', '0') ('place.detailed', '1') ('place.detailed', '2')
[flowgraph,asicflow-bluespec,place.min,0,task]	str	minimum
[flowgraph,asicflow-bluespec,place.min,0,taskmodule]	str	siliconcompiler.tools.builtin.minimum/MinimumTask
[flowgraph,asicflow-bluespec,place.min,0,tool]	str	builtin

2.1.6.2.34. cts.clock_tree_synthesis/0

Keypath	Type	Value
[flowgraph,asicflow-bluespec,cts.clock_tree_synthesis,0,input]	[(str,str)]	('place.min', '0')
[flowgraph,asicflow-bluespec,cts.clock_tree_synthesis,0,task]	str	clock_tree_synthesis
[flowgraph,asicflow-bluespec,cts.clock_tree_synthesis,0,taskmodule]	str	siliconcompiler.tools.openroad.clock_tree_synthesis/CTSTask
[flowgraph,asicflow-bluespec,cts.clock_tree_synthesis,0,tool]	str	openroad

2.1.6.2.35. cts.clock_tree_synthesis/1

Keypath	Type	Value
[flowgraph,asicflow-bluespec,cts.clock_tree_synthesis,1,input]	[(str,str)]	('place.min', '0')
[flowgraph,asicflow-bluespec,cts.clock_tree_synthesis,1,task]	str	clock_tree_synthesis
[flowgraph,asicflow-bluespec,cts.clock_tree_synthesis,1,taskmodule]	str	siliconcompiler.tools.openroad.clock_tree_synthesis/CTSTask
[flowgraph,asicflow-bluespec,cts.clock_tree_synthesis,1,tool]	str	openroad

2.1.6.2.36. cts.clock_tree_synthesis/2

Keypath	Type	Value
[flowgraph,asicflow-bluespec,cts.clock_tree_synthesis,2,input]	[(str,str)]	('place.min', '0')
[flowgraph,asicflow-bluespec,cts.clock_tree_synthesis,2,task]	str	clock_tree_synthesis
[flowgraph,asicflow-bluespec,cts.clock_tree_synthesis,2,taskmodule]	str	siliconcompiler.tools.openroad.clock_tree_synthesis/CTSTask
[flowgraph,asicflow-bluespec,cts.clock_tree_synthesis,2,tool]	str	openroad

2.1.6.2.37. cts.repair_timing/0

Keypath	Type	Value
[flowgraph,asicflow-bluespec,cts.repair_timing,0,input]	[(str,str)]	('cts.clock_tree_synthesis', '0')
[flowgraph,asicflow-bluespec,cts.repair_timing,0,task]	str	repair_timing
[flowgraph,asicflow-bluespec,cts.repair_timing,0,taskmodule]	str	siliconcompiler.tools.openroad.repair_timing/RepairTimingTask
[flowgraph,asicflow-bluespec,cts.repair_timing,0,tool]	str	openroad

2.1.6.2.38. cts.repair_timing/1

Keypath	Type	Value
[flowgraph,asicflow-bluespec,cts.repair_timing,1,input]	[(str,str)]	('cts.clock_tree_synthesis', '1')
[flowgraph,asicflow-bluespec,cts.repair_timing,1,task]	str	repair_timing
[flowgraph,asicflow-bluespec,cts.repair_timing,1,taskmodule]	str	siliconcompiler.tools.openroad.repair_timing/RepairTimingTask
[flowgraph,asicflow-bluespec,cts.repair_timing,1,tool]	str	openroad

2.1.6.2.39. cts.repair_timing/2

Keypath	Type	Value
[flowgraph,asicflow-bluespec,cts.repair_timing,2,input]	[(str,str)]	('cts.clock_tree_synthesis', '2')
[flowgraph,asicflow-bluespec,cts.repair_timing,2,task]	str	repair_timing
[flowgraph,asicflow-bluespec,cts.repair_timing,2,taskmodule]	str	siliconcompiler.tools.openroad.repair_timing/RepairTimingTask
[flowgraph,asicflow-bluespec,cts.repair_timing,2,tool]	str	openroad

2.1.6.2.40. cts.min/0

Keypath	Type	Value
[flowgraph,asicflow-bluespec,cts.min,0,input]	[(str,str)]	('cts.repair_timing', '0') ('cts.repair_timing', '1') ('cts.repair_timing', '2')
[flowgraph,asicflow-bluespec,cts.min,0,task]	str	minimum
[flowgraph,asicflow-bluespec,cts.min,0,taskmodule]	str	siliconcompiler.tools.builtin.minimum/MinimumTask
[flowgraph,asicflow-bluespec,cts.min,0,tool]	str	builtin

2.1.6.2.41. cts.fillcell/0

Keypath	Type	Value
[flowgraph,asicflow-bluespec,cts.fillcell,0,input]	[(str,str)]	('cts.min', '0')
[flowgraph,asicflow-bluespec,cts.fillcell,0,task]	str	fillercell_insertion
[flowgraph,asicflow-bluespec,cts.fillcell,0,taskmodule]	str	siliconcompiler.tools.openroad.fillercell_insertion/FillCellTask
[flowgraph,asicflow-bluespec,cts.fillcell,0,tool]	str	openroad

2.1.6.2.42. route.global/0

Keypath	Type	Value
[flowgraph,asicflow-bluespec,route.global,0,input]	[(str,str)]	('cts.fillcell', '0')
[flowgraph,asicflow-bluespec,route.global,0,task]	str	global_route
[flowgraph,asicflow-bluespec,route.global,0,taskmodule]	str	siliconcompiler.tools.openroad.global_route/GlobalRouteTask
[flowgraph,asicflow-bluespec,route.global,0,tool]	str	openroad

2.1.6.2.43. route.global/1

Keypath	Type	Value
[flowgraph,asicflow-bluespec,route.global,1,input]	[(str,str)]	('cts.fillcell', '0')
[flowgraph,asicflow-bluespec,route.global,1,task]	str	global_route
[flowgraph,asicflow-bluespec,route.global,1,taskmodule]	str	siliconcompiler.tools.openroad.global_route/GlobalRouteTask
[flowgraph,asicflow-bluespec,route.global,1,tool]	str	openroad

2.1.6.2.44. route.global/2

Keypath	Type	Value
[flowgraph,asicflow-bluespec,route.global,2,input]	[(str,str)]	('cts.fillcell', '0')
[flowgraph,asicflow-bluespec,route.global,2,task]	str	global_route
[flowgraph,asicflow-bluespec,route.global,2,taskmodule]	str	siliconcompiler.tools.openroad.global_route/GlobalRouteTask
[flowgraph,asicflow-bluespec,route.global,2,tool]	str	openroad

2.1.6.2.45. route.antenna_repair/0

Keypath	Type	Value
[flowgraph,asicflow-bluespec,route.antenna_repair,0,input]	[(str,str)]	('route.global', '0')
[flowgraph,asicflow-bluespec,route.antenna_repair,0,task]	str	antenna_repair
[flowgraph,asicflow-bluespec,route.antenna_repair,0,taskmodule]	str	siliconcompiler.tools.openroad.antenna_repair/AntennaRepairTask
[flowgraph,asicflow-bluespec,route.antenna_repair,0,tool]	str	openroad

2.1.6.2.46. route.antenna_repair/1

Keypath	Type	Value
[flowgraph,asicflow-bluespec,route.antenna_repair,1,input]	[(str,str)]	('route.global', '1')
[flowgraph,asicflow-bluespec,route.antenna_repair,1,task]	str	antenna_repair
[flowgraph,asicflow-bluespec,route.antenna_repair,1,taskmodule]	str	siliconcompiler.tools.openroad.antenna_repair/AntennaRepairTask
[flowgraph,asicflow-bluespec,route.antenna_repair,1,tool]	str	openroad

2.1.6.2.47. route.antenna_repair/2

Keypath	Type	Value
[flowgraph,asicflow-bluespec,route.antenna_repair,2,input]	[(str,str)]	('route.global', '2')
[flowgraph,asicflow-bluespec,route.antenna_repair,2,task]	str	antenna_repair
[flowgraph,asicflow-bluespec,route.antenna_repair,2,taskmodule]	str	siliconcompiler.tools.openroad.antenna_repair/AntennaRepairTask
[flowgraph,asicflow-bluespec,route.antenna_repair,2,tool]	str	openroad

2.1.6.2.48. route.detailed/0

Keypath	Type	Value
[flowgraph,asicflow-bluespec,route.detailed,0,input]	[(str,str)]	('route.antenna_repair', '0')
[flowgraph,asicflow-bluespec,route.detailed,0,task]	str	detailed_route
[flowgraph,asicflow-bluespec,route.detailed,0,taskmodule]	str	siliconcompiler.tools.openroad.detailed_route/DetailedRouteTask
[flowgraph,asicflow-bluespec,route.detailed,0,tool]	str	openroad

2.1.6.2.49. route.detailed/1

Keypath	Type	Value
[flowgraph,asicflow-bluespec,route.detailed,1,input]	[(str,str)]	('route.antenna_repair', '1')
[flowgraph,asicflow-bluespec,route.detailed,1,task]	str	detailed_route
[flowgraph,asicflow-bluespec,route.detailed,1,taskmodule]	str	siliconcompiler.tools.openroad.detailed_route/DetailedRouteTask
[flowgraph,asicflow-bluespec,route.detailed,1,tool]	str	openroad

2.1.6.2.50. route.detailed/2

Keypath	Type	Value
[flowgraph,asicflow-bluespec,route.detailed,2,input]	[(str,str)]	('route.antenna_repair', '2')
[flowgraph,asicflow-bluespec,route.detailed,2,task]	str	detailed_route
[flowgraph,asicflow-bluespec,route.detailed,2,taskmodule]	str	siliconcompiler.tools.openroad.detailed_route/DetailedRouteTask
[flowgraph,asicflow-bluespec,route.detailed,2,tool]	str	openroad

2.1.6.2.51. route.min/0

Keypath	Type	Value
[flowgraph,asicflow-bluespec,route.min,0,input]	[(str,str)]	('route.detailed', '0') ('route.detailed', '1') ('route.detailed', '2')
[flowgraph,asicflow-bluespec,route.min,0,task]	str	minimum
[flowgraph,asicflow-bluespec,route.min,0,taskmodule]	str	siliconcompiler.tools.builtin.minimum/MinimumTask
[flowgraph,asicflow-bluespec,route.min,0,tool]	str	builtin

2.1.6.2.52. dfm.metal_fill/0

Keypath	Type	Value
[flowgraph,asicflow-bluespec,dfm.metal_fill,0,input]	[(str,str)]	('route.min', '0')
[flowgraph,asicflow-bluespec,dfm.metal_fill,0,task]	str	fillmetal_insertion
[flowgraph,asicflow-bluespec,dfm.metal_fill,0,taskmodule]	str	siliconcompiler.tools.openroad.fillmetal_insertion/FillMetalTask
[flowgraph,asicflow-bluespec,dfm.metal_fill,0,tool]	str	openroad

2.1.6.2.53. write.gds/0

Keypath	Type	Value
[flowgraph,asicflow-bluespec,write.gds,0,input]	[(str,str)]	('dfm.metal_fill', '0')
[flowgraph,asicflow-bluespec,write.gds,0,task]	str	export
[flowgraph,asicflow-bluespec,write.gds,0,taskmodule]	str	siliconcompiler.tools.klayout.export/ExportTask
[flowgraph,asicflow-bluespec,write.gds,0,tool]	str	klayout

2.1.6.2.54. write.views/0

Keypath	Type	Value
[flowgraph,asicflow-bluespec,write.views,0,input]	[(str,str)]	('dfm.metal_fill', '0')
[flowgraph,asicflow-bluespec,write.views,0,task]	str	write_data
[flowgraph,asicflow-bluespec,write.views,0,taskmodule]	str	siliconcompiler.tools.openroad.write_data/WriteViewsTask
[flowgraph,asicflow-bluespec,write.views,0,tool]	str	openroad

2.1.7. ASIC Subflows

The ASIC flow is assembled from the following stage-specific subflows. They can be used on their own to run or debug an individual stage of the back-end.

2.1.7.1. cleanup_synthflow

A flow that performs only the synthesis cleanup portion of the ASIC flow.

This flow is useful for quickly checking that a design can be successfully cleaned up after synthesis without running floorplanning or timing analysis. It includes the removal of synthesis buffers and dead logic.

File: asicflow.py

2.1.7.1.1. Graph

2.1.7.1.2. Nodes

2.1.7.1.2.1. clean/0

Keypath	Type	Value
[flowgraph,cleanup_synthflow,clean,0,task]	str	cleanup_synth
[flowgraph,cleanup_synthflow,clean,0,taskmodule]	str	siliconcompiler.tools.openroad.synth_cleanup/CleanupSynthTask
[flowgraph,cleanup_synthflow,clean,0,tool]	str	openroad

2.1.7.1.2.2. clean/1

Keypath	Type	Value
[flowgraph,cleanup_synthflow,clean,1,task]	str	cleanup_synth
[flowgraph,cleanup_synthflow,clean,1,taskmodule]	str	siliconcompiler.tools.openroad.synth_cleanup/CleanupSynthTask
[flowgraph,cleanup_synthflow,clean,1,tool]	str	openroad

2.1.7.1.2.3. clean/2

Keypath	Type	Value
[flowgraph,cleanup_synthflow,clean,2,task]	str	cleanup_synth
[flowgraph,cleanup_synthflow,clean,2,taskmodule]	str	siliconcompiler.tools.openroad.synth_cleanup/CleanupSynthTask
[flowgraph,cleanup_synthflow,clean,2,tool]	str	openroad

2.1.7.1.2.4. min/0

Keypath	Type	Value
[flowgraph,cleanup_synthflow,min,0,input]	[(str,str)]	('clean', '0') ('clean', '1') ('clean', '2')
[flowgraph,cleanup_synthflow,min,0,task]	str	minimum
[flowgraph,cleanup_synthflow,min,0,taskmodule]	str	siliconcompiler.tools.builtin.minimum/MinimumTask
[flowgraph,cleanup_synthflow,min,0,tool]	str	builtin

2.1.7.2. floorplanningflow

A flow that performs only the floorplanning portion of the ASIC flow.

This flow is useful for quickly checking that a design can be successfully floorplanned without running synthesis or timing analysis. It includes macro placement, tapcell/endcap insertion, power grid generation, and pin placement.

File: asicflow.py

2.1.7.2.1. Graph

2.1.7.2.2. Nodes

2.1.7.2.2.1. init/0

Keypath	Type	Value
[flowgraph,floorplanningflow,init,0,task]	str	init_floorplan
[flowgraph,floorplanningflow,init,0,taskmodule]	str	siliconcompiler.tools.openroad.init_floorplan/InitFloorplanTask
[flowgraph,floorplanningflow,init,0,tool]	str	openroad

2.1.7.2.2.2. init/1

Keypath	Type	Value
[flowgraph,floorplanningflow,init,1,task]	str	init_floorplan
[flowgraph,floorplanningflow,init,1,taskmodule]	str	siliconcompiler.tools.openroad.init_floorplan/InitFloorplanTask
[flowgraph,floorplanningflow,init,1,tool]	str	openroad

2.1.7.2.2.3. init/2

Keypath	Type	Value
[flowgraph,floorplanningflow,init,2,task]	str	init_floorplan
[flowgraph,floorplanningflow,init,2,taskmodule]	str	siliconcompiler.tools.openroad.init_floorplan/InitFloorplanTask
[flowgraph,floorplanningflow,init,2,tool]	str	openroad

2.1.7.2.2.4. macro_placement/0

Keypath	Type	Value
[flowgraph,floorplanningflow,macro_placement,0,input]	[(str,str)]	('init', '0')
[flowgraph,floorplanningflow,macro_placement,0,task]	str	macro_placement
[flowgraph,floorplanningflow,macro_placement,0,taskmodule]	str	siliconcompiler.tools.openroad.macro_placement/MacroPlacementTask
[flowgraph,floorplanningflow,macro_placement,0,tool]	str	openroad

2.1.7.2.2.5. macro_placement/1

Keypath	Type	Value
[flowgraph,floorplanningflow,macro_placement,1,input]	[(str,str)]	('init', '1')
[flowgraph,floorplanningflow,macro_placement,1,task]	str	macro_placement
[flowgraph,floorplanningflow,macro_placement,1,taskmodule]	str	siliconcompiler.tools.openroad.macro_placement/MacroPlacementTask
[flowgraph,floorplanningflow,macro_placement,1,tool]	str	openroad

2.1.7.2.2.6. macro_placement/2

Keypath	Type	Value
[flowgraph,floorplanningflow,macro_placement,2,input]	[(str,str)]	('init', '2')
[flowgraph,floorplanningflow,macro_placement,2,task]	str	macro_placement
[flowgraph,floorplanningflow,macro_placement,2,taskmodule]	str	siliconcompiler.tools.openroad.macro_placement/MacroPlacementTask
[flowgraph,floorplanningflow,macro_placement,2,tool]	str	openroad

2.1.7.2.2.7. tapcell/0

Keypath	Type	Value
[flowgraph,floorplanningflow,tapcell,0,input]	[(str,str)]	('macro_placement', '0')
[flowgraph,floorplanningflow,tapcell,0,task]	str	endcap_tapcell_insertion
[flowgraph,floorplanningflow,tapcell,0,taskmodule]	str	siliconcompiler.tools.openroad.endcap_tapcell_insertion/EndCapTapCellTask
[flowgraph,floorplanningflow,tapcell,0,tool]	str	openroad

2.1.7.2.2.8. tapcell/1

Keypath	Type	Value
[flowgraph,floorplanningflow,tapcell,1,input]	[(str,str)]	('macro_placement', '1')
[flowgraph,floorplanningflow,tapcell,1,task]	str	endcap_tapcell_insertion
[flowgraph,floorplanningflow,tapcell,1,taskmodule]	str	siliconcompiler.tools.openroad.endcap_tapcell_insertion/EndCapTapCellTask
[flowgraph,floorplanningflow,tapcell,1,tool]	str	openroad

2.1.7.2.2.9. tapcell/2

Keypath	Type	Value
[flowgraph,floorplanningflow,tapcell,2,input]	[(str,str)]	('macro_placement', '2')
[flowgraph,floorplanningflow,tapcell,2,task]	str	endcap_tapcell_insertion
[flowgraph,floorplanningflow,tapcell,2,taskmodule]	str	siliconcompiler.tools.openroad.endcap_tapcell_insertion/EndCapTapCellTask
[flowgraph,floorplanningflow,tapcell,2,tool]	str	openroad

2.1.7.2.2.10. power_grid/0

Keypath	Type	Value
[flowgraph,floorplanningflow,power_grid,0,input]	[(str,str)]	('tapcell', '0')
[flowgraph,floorplanningflow,power_grid,0,task]	str	power_grid
[flowgraph,floorplanningflow,power_grid,0,taskmodule]	str	siliconcompiler.tools.openroad.power_grid/PowerGridTask
[flowgraph,floorplanningflow,power_grid,0,tool]	str	openroad

2.1.7.2.2.11. power_grid/1

Keypath	Type	Value
[flowgraph,floorplanningflow,power_grid,1,input]	[(str,str)]	('tapcell', '1')
[flowgraph,floorplanningflow,power_grid,1,task]	str	power_grid
[flowgraph,floorplanningflow,power_grid,1,taskmodule]	str	siliconcompiler.tools.openroad.power_grid/PowerGridTask
[flowgraph,floorplanningflow,power_grid,1,tool]	str	openroad

2.1.7.2.2.12. power_grid/2

Keypath	Type	Value
[flowgraph,floorplanningflow,power_grid,2,input]	[(str,str)]	('tapcell', '2')
[flowgraph,floorplanningflow,power_grid,2,task]	str	power_grid
[flowgraph,floorplanningflow,power_grid,2,taskmodule]	str	siliconcompiler.tools.openroad.power_grid/PowerGridTask
[flowgraph,floorplanningflow,power_grid,2,tool]	str	openroad

2.1.7.2.2.13. pin_placement/0

Keypath	Type	Value
[flowgraph,floorplanningflow,pin_placement,0,input]	[(str,str)]	('power_grid', '0')
[flowgraph,floorplanningflow,pin_placement,0,task]	str	pin_placement
[flowgraph,floorplanningflow,pin_placement,0,taskmodule]	str	siliconcompiler.tools.openroad.pin_placement/PinPlacementTask
[flowgraph,floorplanningflow,pin_placement,0,tool]	str	openroad

2.1.7.2.2.14. pin_placement/1

Keypath	Type	Value
[flowgraph,floorplanningflow,pin_placement,1,input]	[(str,str)]	('power_grid', '1')
[flowgraph,floorplanningflow,pin_placement,1,task]	str	pin_placement
[flowgraph,floorplanningflow,pin_placement,1,taskmodule]	str	siliconcompiler.tools.openroad.pin_placement/PinPlacementTask
[flowgraph,floorplanningflow,pin_placement,1,tool]	str	openroad

2.1.7.2.2.15. pin_placement/2

Keypath	Type	Value
[flowgraph,floorplanningflow,pin_placement,2,input]	[(str,str)]	('power_grid', '2')
[flowgraph,floorplanningflow,pin_placement,2,task]	str	pin_placement
[flowgraph,floorplanningflow,pin_placement,2,taskmodule]	str	siliconcompiler.tools.openroad.pin_placement/PinPlacementTask
[flowgraph,floorplanningflow,pin_placement,2,tool]	str	openroad

2.1.7.2.2.16. min/0

Keypath	Type	Value
[flowgraph,floorplanningflow,min,0,input]	[(str,str)]	('pin_placement', '0') ('pin_placement', '1') ('pin_placement', '2')
[flowgraph,floorplanningflow,min,0,task]	str	minimum
[flowgraph,floorplanningflow,min,0,taskmodule]	str	siliconcompiler.tools.builtin.minimum/MinimumTask
[flowgraph,floorplanningflow,min,0,tool]	str	builtin

2.1.7.3. placementflow

A flow that performs only the placement portion of the ASIC flow.

This flow is useful for quickly checking that a design can be successfully placed without running synthesis or timing analysis. It includes global placement, repair, and detailed placement.

File: asicflow.py

2.1.7.3.1. Graph

2.1.7.3.2. Nodes

2.1.7.3.2.1. global/0

Keypath	Type	Value
[flowgraph,placementflow,global,0,task]	str	global_placement
[flowgraph,placementflow,global,0,taskmodule]	str	siliconcompiler.tools.openroad.global_placement/GlobalPlacementTask
[flowgraph,placementflow,global,0,tool]	str	openroad

2.1.7.3.2.2. global/1

Keypath	Type	Value
[flowgraph,placementflow,global,1,task]	str	global_placement
[flowgraph,placementflow,global,1,taskmodule]	str	siliconcompiler.tools.openroad.global_placement/GlobalPlacementTask
[flowgraph,placementflow,global,1,tool]	str	openroad

2.1.7.3.2.3. global/2

Keypath	Type	Value
[flowgraph,placementflow,global,2,task]	str	global_placement
[flowgraph,placementflow,global,2,taskmodule]	str	siliconcompiler.tools.openroad.global_placement/GlobalPlacementTask
[flowgraph,placementflow,global,2,tool]	str	openroad

2.1.7.3.2.4. repair_design/0

Keypath	Type	Value
[flowgraph,placementflow,repair_design,0,input]	[(str,str)]	('global', '0')
[flowgraph,placementflow,repair_design,0,task]	str	repair_design
[flowgraph,placementflow,repair_design,0,taskmodule]	str	siliconcompiler.tools.openroad.repair_design/RepairDesignTask
[flowgraph,placementflow,repair_design,0,tool]	str	openroad

2.1.7.3.2.5. repair_design/1

Keypath	Type	Value
[flowgraph,placementflow,repair_design,1,input]	[(str,str)]	('global', '1')
[flowgraph,placementflow,repair_design,1,task]	str	repair_design
[flowgraph,placementflow,repair_design,1,taskmodule]	str	siliconcompiler.tools.openroad.repair_design/RepairDesignTask
[flowgraph,placementflow,repair_design,1,tool]	str	openroad

2.1.7.3.2.6. repair_design/2

Keypath	Type	Value
[flowgraph,placementflow,repair_design,2,input]	[(str,str)]	('global', '2')
[flowgraph,placementflow,repair_design,2,task]	str	repair_design
[flowgraph,placementflow,repair_design,2,taskmodule]	str	siliconcompiler.tools.openroad.repair_design/RepairDesignTask
[flowgraph,placementflow,repair_design,2,tool]	str	openroad

2.1.7.3.2.7. detailed/0

Keypath	Type	Value
[flowgraph,placementflow,detailed,0,input]	[(str,str)]	('repair_design', '0')
[flowgraph,placementflow,detailed,0,task]	str	detailed_placement
[flowgraph,placementflow,detailed,0,taskmodule]	str	siliconcompiler.tools.openroad.detailed_placement/DetailedPlacementTask
[flowgraph,placementflow,detailed,0,tool]	str	openroad

2.1.7.3.2.8. detailed/1

Keypath	Type	Value
[flowgraph,placementflow,detailed,1,input]	[(str,str)]	('repair_design', '1')
[flowgraph,placementflow,detailed,1,task]	str	detailed_placement
[flowgraph,placementflow,detailed,1,taskmodule]	str	siliconcompiler.tools.openroad.detailed_placement/DetailedPlacementTask
[flowgraph,placementflow,detailed,1,tool]	str	openroad

2.1.7.3.2.9. detailed/2

Keypath	Type	Value
[flowgraph,placementflow,detailed,2,input]	[(str,str)]	('repair_design', '2')
[flowgraph,placementflow,detailed,2,task]	str	detailed_placement
[flowgraph,placementflow,detailed,2,taskmodule]	str	siliconcompiler.tools.openroad.detailed_placement/DetailedPlacementTask
[flowgraph,placementflow,detailed,2,tool]	str	openroad

2.1.7.3.2.10. min/0

Keypath	Type	Value
[flowgraph,placementflow,min,0,input]	[(str,str)]	('detailed', '0') ('detailed', '1') ('detailed', '2')
[flowgraph,placementflow,min,0,task]	str	minimum
[flowgraph,placementflow,min,0,taskmodule]	str	siliconcompiler.tools.builtin.minimum/MinimumTask
[flowgraph,placementflow,min,0,tool]	str	builtin

2.1.7.4. ctssflow

A flow that performs only the clock tree synthesis portion of the ASIC flow.

This flow is useful for quickly checking that a design can be successfully clock tree synthesized without running synthesis or timing analysis. It includes clock tree synthesis, repair, and filler cell insertion.

File: asicflow.py

2.1.7.4.1. Graph

2.1.7.4.2. Nodes

2.1.7.4.2.1. clock_tree_synthesis/0

Keypath	Type	Value
[flowgraph,ctssflow,clock_tree_synthesis,0,task]	str	clock_tree_synthesis
[flowgraph,ctssflow,clock_tree_synthesis,0,taskmodule]	str	siliconcompiler.tools.openroad.clock_tree_synthesis/CTSTask
[flowgraph,ctssflow,clock_tree_synthesis,0,tool]	str	openroad

2.1.7.4.2.2. clock_tree_synthesis/1

Keypath	Type	Value
[flowgraph,ctssflow,clock_tree_synthesis,1,task]	str	clock_tree_synthesis
[flowgraph,ctssflow,clock_tree_synthesis,1,taskmodule]	str	siliconcompiler.tools.openroad.clock_tree_synthesis/CTSTask
[flowgraph,ctssflow,clock_tree_synthesis,1,tool]	str	openroad

2.1.7.4.2.3. clock_tree_synthesis/2

Keypath	Type	Value
[flowgraph,ctssflow,clock_tree_synthesis,2,task]	str	clock_tree_synthesis
[flowgraph,ctssflow,clock_tree_synthesis,2,taskmodule]	str	siliconcompiler.tools.openroad.clock_tree_synthesis/CTSTask
[flowgraph,ctssflow,clock_tree_synthesis,2,tool]	str	openroad

2.1.7.4.2.4. repair_timing/0

Keypath	Type	Value
[flowgraph,ctssflow,repair_timing,0,input]	[(str,str)]	('clock_tree_synthesis', '0')
[flowgraph,ctssflow,repair_timing,0,task]	str	repair_timing
[flowgraph,ctssflow,repair_timing,0,taskmodule]	str	siliconcompiler.tools.openroad.repair_timing/RepairTimingTask
[flowgraph,ctssflow,repair_timing,0,tool]	str	openroad

2.1.7.4.2.5. repair_timing/1

Keypath	Type	Value
[flowgraph,ctssflow,repair_timing,1,input]	[(str,str)]	('clock_tree_synthesis', '1')
[flowgraph,ctssflow,repair_timing,1,task]	str	repair_timing
[flowgraph,ctssflow,repair_timing,1,taskmodule]	str	siliconcompiler.tools.openroad.repair_timing/RepairTimingTask
[flowgraph,ctssflow,repair_timing,1,tool]	str	openroad

2.1.7.4.2.6. repair_timing/2

Keypath	Type	Value
[flowgraph,ctssflow,repair_timing,2,input]	[(str,str)]	('clock_tree_synthesis', '2')
[flowgraph,ctssflow,repair_timing,2,task]	str	repair_timing
[flowgraph,ctssflow,repair_timing,2,taskmodule]	str	siliconcompiler.tools.openroad.repair_timing/RepairTimingTask
[flowgraph,ctssflow,repair_timing,2,tool]	str	openroad

2.1.7.4.2.7. min/0

Keypath	Type	Value
[flowgraph,ctssflow,min,0,input]	[(str,str)]	('repair_timing', '0') ('repair_timing', '1') ('repair_timing', '2')
[flowgraph,ctssflow,min,0,task]	str	minimum
[flowgraph,ctssflow,min,0,taskmodule]	str	siliconcompiler.tools.builtin.minimum/MinimumTask
[flowgraph,ctssflow,min,0,tool]	str	builtin

2.1.7.5. fillercellflow

A flow that performs only the design-for-manufacturing (DFM) portion of the ASIC flow.

This flow is useful for quickly checking that a design can be successfully processed for DFM without running synthesis or timing analysis. It includes filler cell insertion.

File: asicflow.py

2.1.7.5.1. Graph

2.1.7.5.2. Nodes

2.1.7.5.2.1. fillcell/0

Keypath	Type	Value
[flowgraph,fillercellflow,fillcell,0,task]	str	fillercell_insertion
[flowgraph,fillercellflow,fillcell,0,taskmodule]	str	siliconcompiler.tools.openroad.fillercell_insertion/FillCellTask
[flowgraph,fillercellflow,fillcell,0,tool]	str	openroad

2.1.7.5.2.2. fillcell/1

Keypath	Type	Value
[flowgraph,fillercellflow,fillcell,1,task]	str	fillercell_insertion
[flowgraph,fillercellflow,fillcell,1,taskmodule]	str	siliconcompiler.tools.openroad.fillercell_insertion/FillCellTask
[flowgraph,fillercellflow,fillcell,1,tool]	str	openroad

2.1.7.5.2.3. fillcell/2

Keypath	Type	Value
[flowgraph,fillercellflow,fillcell,2,task]	str	fillercell_insertion
[flowgraph,fillercellflow,fillcell,2,taskmodule]	str	siliconcompiler.tools.openroad.fillercell_insertion/FillCellTask
[flowgraph,fillercellflow,fillcell,2,tool]	str	openroad

2.1.7.5.2.4. min/0

Keypath	Type	Value
[flowgraph,fillercellflow,min,0,input]	[(str,str)]	('fillcell', '0') ('fillcell', '1') ('fillcell', '2')
[flowgraph,fillercellflow,min,0,task]	str	minimum
[flowgraph,fillercellflow,min,0,taskmodule]	str	siliconcompiler.tools.builtin.minimum/MinimumTask
[flowgraph,fillercellflow,min,0,tool]	str	builtin

2.1.7.6. routingflow

A flow that performs only the routing portion of the ASIC flow.

This flow is useful for quickly checking that a design can be successfully routed without running synthesis or timing analysis. It includes global routing, antenna repair, and detailed routing.

File: asicflow.py

2.1.7.6.1. Graph

2.1.7.6.2. Nodes

2.1.7.6.2.1. global/0

Keypath	Type	Value
[flowgraph,routingflow,global,0,task]	str	global_route
[flowgraph,routingflow,global,0,taskmodule]	str	siliconcompiler.tools.openroad.global_route/GlobalRouteTask
[flowgraph,routingflow,global,0,tool]	str	openroad

2.1.7.6.2.2. global/1

Keypath	Type	Value
[flowgraph,routingflow,global,1,task]	str	global_route
[flowgraph,routingflow,global,1,taskmodule]	str	siliconcompiler.tools.openroad.global_route/GlobalRouteTask
[flowgraph,routingflow,global,1,tool]	str	openroad

2.1.7.6.2.3. global/2

Keypath	Type	Value
[flowgraph,routingflow,global,2,task]	str	global_route
[flowgraph,routingflow,global,2,taskmodule]	str	siliconcompiler.tools.openroad.global_route/GlobalRouteTask
[flowgraph,routingflow,global,2,tool]	str	openroad

2.1.7.6.2.4. antenna_repair/0

Keypath	Type	Value
[flowgraph,routingflow,antenna_repair,0,input]	[(str,str)]	('global', '0')
[flowgraph,routingflow,antenna_repair,0,task]	str	antenna_repair
[flowgraph,routingflow,antenna_repair,0,taskmodule]	str	siliconcompiler.tools.openroad.antenna_repair/AntennaRepairTask
[flowgraph,routingflow,antenna_repair,0,tool]	str	openroad

2.1.7.6.2.5. antenna_repair/1

Keypath	Type	Value
[flowgraph,routingflow,antenna_repair,1,input]	[(str,str)]	('global', '1')
[flowgraph,routingflow,antenna_repair,1,task]	str	antenna_repair
[flowgraph,routingflow,antenna_repair,1,taskmodule]	str	siliconcompiler.tools.openroad.antenna_repair/AntennaRepairTask
[flowgraph,routingflow,antenna_repair,1,tool]	str	openroad

2.1.7.6.2.6. antenna_repair/2

Keypath	Type	Value
[flowgraph,routingflow,antenna_repair,2,input]	[(str,str)]	('global', '2')
[flowgraph,routingflow,antenna_repair,2,task]	str	antenna_repair
[flowgraph,routingflow,antenna_repair,2,taskmodule]	str	siliconcompiler.tools.openroad.antenna_repair/AntennaRepairTask
[flowgraph,routingflow,antenna_repair,2,tool]	str	openroad

2.1.7.6.2.7. detailed/0

Keypath	Type	Value
[flowgraph,routingflow,detailed,0,input]	[(str,str)]	('antenna_repair', '0')
[flowgraph,routingflow,detailed,0,task]	str	detailed_route
[flowgraph,routingflow,detailed,0,taskmodule]	str	siliconcompiler.tools.openroad.detailed_route/DetailedRouteTask
[flowgraph,routingflow,detailed,0,tool]	str	openroad

2.1.7.6.2.8. detailed/1

Keypath	Type	Value
[flowgraph,routingflow,detailed,1,input]	[(str,str)]	('antenna_repair', '1')
[flowgraph,routingflow,detailed,1,task]	str	detailed_route
[flowgraph,routingflow,detailed,1,taskmodule]	str	siliconcompiler.tools.openroad.detailed_route/DetailedRouteTask
[flowgraph,routingflow,detailed,1,tool]	str	openroad

2.1.7.6.2.9. detailed/2

Keypath	Type	Value
[flowgraph,routingflow,detailed,2,input]	[(str,str)]	('antenna_repair', '2')
[flowgraph,routingflow,detailed,2,task]	str	detailed_route
[flowgraph,routingflow,detailed,2,taskmodule]	str	siliconcompiler.tools.openroad.detailed_route/DetailedRouteTask
[flowgraph,routingflow,detailed,2,tool]	str	openroad

2.1.7.6.2.10. min/0

Keypath	Type	Value
[flowgraph,routingflow,min,0,input]	[(str,str)]	('detailed', '0') ('detailed', '1') ('detailed', '2')
[flowgraph,routingflow,min,0,task]	str	minimum
[flowgraph,routingflow,min,0,taskmodule]	str	siliconcompiler.tools.builtin.minimum/MinimumTask
[flowgraph,routingflow,min,0,tool]	str	builtin

2.1.7.7. metalfillflow

A flow that performs only the metal fill portion of the ASIC flow.

This flow is useful for quickly checking that a design can be successfully processed for metal fill without running synthesis or timing analysis. It includes metal fill insertion.

File: asicflow.py

2.1.7.7.1. Graph

2.1.7.7.2. Nodes

2.1.7.7.2.1. metal_fill/0

Keypath	Type	Value
[flowgraph,metalfillflow,metal_fill,0,task]	str	fillmetal_insertion
[flowgraph,metalfillflow,metal_fill,0,taskmodule]	str	siliconcompiler.tools.openroad.fillmetal_insertion/FillMetalTask
[flowgraph,metalfillflow,metal_fill,0,tool]	str	openroad

2.1.7.7.2.2. metal_fill/1

Keypath	Type	Value
[flowgraph,metalfillflow,metal_fill,1,task]	str	fillmetal_insertion
[flowgraph,metalfillflow,metal_fill,1,taskmodule]	str	siliconcompiler.tools.openroad.fillmetal_insertion/FillMetalTask
[flowgraph,metalfillflow,metal_fill,1,tool]	str	openroad

2.1.7.7.2.3. metal_fill/2

Keypath	Type	Value
[flowgraph,metalfillflow,metal_fill,2,task]	str	fillmetal_insertion
[flowgraph,metalfillflow,metal_fill,2,taskmodule]	str	siliconcompiler.tools.openroad.fillmetal_insertion/FillMetalTask
[flowgraph,metalfillflow,metal_fill,2,tool]	str	openroad

2.1.7.7.2.4. min/0

Keypath	Type	Value
[flowgraph,metalfillflow,min,0,input]	[(str,str)]	('metal_fill', '0') ('metal_fill', '1') ('metal_fill', '2')
[flowgraph,metalfillflow,min,0,task]	str	minimum
[flowgraph,metalfillflow,min,0,taskmodule]	str	siliconcompiler.tools.builtin.minimum/MinimumTask
[flowgraph,metalfillflow,min,0,tool]	str	builtin

2.2. Elaboration Flows

Front-end flows that elaborate an RTL design from its source files and emit Verilog. Because every variant produces Verilog, they can be used interchangeably as a front-end for any downstream flow that consumes a Verilog netlist.

2.2.1. elaborationflow-verilog / 0

A flow which elaborates an RTL design from its source files.

This flow performs only the elaboration portion of the synthesis flow, producing an elaborated design without running synthesis or timing analysis. It is useful for quickly checking that a design elaborates cleanly.

The flow consists of the following step:

• elaborate: Elaborates the RTL design from its source files.

The final node, elaborate, emits Verilog.

File: elaborationflow.py

2.2.1.1. Graph

2.2.1.2. Nodes

2.2.1.2.1. elaborate/0

Keypath	Type	Value
[flowgraph,elaborationflow-verilog,elaborate,0,task]	str	elaborate
[flowgraph,elaborationflow-verilog,elaborate,0,taskmodule]	str	siliconcompiler.tools.slang.elaborate/Elaborate
[flowgraph,elaborationflow-verilog,elaborate,0,tool]	str	slang

2.2.2. elaborationflow-systemverilog / 1

A flow which elaborates an RTL design from its source files.

This flow performs only the elaboration portion of the synthesis flow, producing an elaborated design without running synthesis or timing analysis. It is useful for quickly checking that a design elaborates cleanly.

The flow consists of the following step:

• elaborate: Elaborates the RTL design from its source files.

The final node, elaborate, emits Verilog.

File: elaborationflow.py

2.2.2.1. Graph

2.2.2.2. Nodes

2.2.2.2.1. elaborate/0

Keypath	Type	Value
[flowgraph,elaborationflow-systemverilog,elaborate,0,task]	str	elaborate
[flowgraph,elaborationflow-systemverilog,elaborate,0,taskmodule]	str	siliconcompiler.tools.slang.elaborate/Elaborate
[flowgraph,elaborationflow-systemverilog,elaborate,0,tool]	str	slang

2.2.3. elaborationflow-systemverilog-sv2v / 2

A flow which elaborates an RTL design from its source files.

This flow performs only the elaboration portion of the synthesis flow, producing an elaborated design without running synthesis or timing analysis. It is useful for quickly checking that a design elaborates cleanly.

The flow consists of the following step:

• elaborate: Elaborates the RTL design from its source files.

The final node, elaborate, emits Verilog.

File: elaborationflow.py

2.2.3.1. Graph

2.2.3.2. Nodes

2.2.3.2.1. elaborate/0

Keypath	Type	Value
[flowgraph,elaborationflow-systemverilog-sv2v,elaborate,0,task]	str	elaborate
[flowgraph,elaborationflow-systemverilog-sv2v,elaborate,0,taskmodule]	str	siliconcompiler.tools.slang.elaborate/Elaborate
[flowgraph,elaborationflow-systemverilog-sv2v,elaborate,0,tool]	str	slang

2.2.3.2.2. convert/0

Keypath	Type	Value
[flowgraph,elaborationflow-systemverilog-sv2v,convert,0,input]	[(str,str)]	('elaborate', '0')
[flowgraph,elaborationflow-systemverilog-sv2v,convert,0,task]	str	convert
[flowgraph,elaborationflow-systemverilog-sv2v,convert,0,taskmodule]	str	siliconcompiler.tools.sv2v.convert/ConvertTask
[flowgraph,elaborationflow-systemverilog-sv2v,convert,0,tool]	str	sv2v

2.2.4. elaborationflow-chisel / 3

A flow which elaborates an RTL design from its source files.

This flow performs only the elaboration portion of the synthesis flow, producing an elaborated design without running synthesis or timing analysis. It is useful for quickly checking that a design elaborates cleanly.

The flow consists of the following step:

• elaborate: Elaborates the RTL design from its source files.

The final node, elaborate, emits Verilog.

File: elaborationflow.py

2.2.4.1. Graph

2.2.4.2. Nodes

2.2.4.2.1. convert/0

Keypath	Type	Value
[flowgraph,elaborationflow-chisel,convert,0,task]	str	convert
[flowgraph,elaborationflow-chisel,convert,0,taskmodule]	str	siliconcompiler.tools.chisel.convert/ConvertTask
[flowgraph,elaborationflow-chisel,convert,0,tool]	str	chisel

2.2.5. elaborationflow-vhdl / 4

A flow which elaborates an RTL design from its source files.

This flow performs only the elaboration portion of the synthesis flow, producing an elaborated design without running synthesis or timing analysis. It is useful for quickly checking that a design elaborates cleanly.

The flow consists of the following step:

• elaborate: Elaborates the RTL design from its source files.

The final node, elaborate, emits Verilog.

File: elaborationflow.py

2.2.5.1. Graph

2.2.5.2. Nodes

2.2.5.2.1. convert/0

Keypath	Type	Value
[flowgraph,elaborationflow-vhdl,convert,0,task]	str	convert
[flowgraph,elaborationflow-vhdl,convert,0,taskmodule]	str	siliconcompiler.tools.ghdl.convert/ConvertTask
[flowgraph,elaborationflow-vhdl,convert,0,tool]	str	ghdl

2.2.6. elaborationflow-hls / 5

A flow which elaborates an RTL design from its source files.

This flow performs only the elaboration portion of the synthesis flow, producing an elaborated design without running synthesis or timing analysis. It is useful for quickly checking that a design elaborates cleanly.

The flow consists of the following step:

• elaborate: Elaborates the RTL design from its source files.

The final node, elaborate, emits Verilog.

File: elaborationflow.py

2.2.6.1. Graph

2.2.6.2. Nodes

2.2.6.2.1. convert/0

Keypath	Type	Value
[flowgraph,elaborationflow-hls,convert,0,task]	str	convert
[flowgraph,elaborationflow-hls,convert,0,taskmodule]	str	siliconcompiler.tools.bambu.convert/ConvertTask
[flowgraph,elaborationflow-hls,convert,0,tool]	str	bambu

2.2.7. elaborationflow-bluespec / 6

A flow which elaborates an RTL design from its source files.

This flow performs only the elaboration portion of the synthesis flow, producing an elaborated design without running synthesis or timing analysis. It is useful for quickly checking that a design elaborates cleanly.

The flow consists of the following step:

• elaborate: Elaborates the RTL design from its source files.

The final node, elaborate, emits Verilog.

File: elaborationflow.py

2.2.7.1. Graph

2.2.7.2. Nodes

2.2.7.2.1. convert/0

Keypath	Type	Value
[flowgraph,elaborationflow-bluespec,convert,0,task]	str	convert
[flowgraph,elaborationflow-bluespec,convert,0,taskmodule]	str	siliconcompiler.tools.bluespec.convert/ConvertTask
[flowgraph,elaborationflow-bluespec,convert,0,tool]	str	bluespec

2.2.8. Elaboration Subflows

The language-specific building blocks for elaborating a design in a single source language. They can be used on their own as a front-end.

2.2.8.1. slangelaborationflow

A flow which elaborates an RTL design from its source files.

This flow performs only the elaboration portion of the synthesis flow, producing an elaborated design without running synthesis or timing analysis. It is useful for quickly checking that a design elaborates cleanly.

The flow consists of the following step:

• elaborate: Elaborates the RTL design from its source files.

The final node, elaborate, emits Verilog.

File: elaborationflow.py

2.2.8.1.1. Graph

2.2.8.1.2. Nodes

2.2.8.1.2.1. elaborate/0

Keypath	Type	Value
[flowgraph,slangelaborationflow,elaborate,0,task]	str	elaborate
[flowgraph,slangelaborationflow,elaborate,0,taskmodule]	str	siliconcompiler.tools.slang.elaborate/Elaborate
[flowgraph,slangelaborationflow,elaborate,0,tool]	str	slang

2.2.8.2. sv2velaborationflow

A SystemVerilog-to-Verilog elaboration flow.

This flow is intended for designs written in SystemVerilog that may not be fully supported by downstream tools. It inserts a ‘convert’ step using SV2V before the standard ‘elaborate’ step to ensure the design is in a compatible Verilog format.

The final node, elaborate, emits Verilog.

File: elaborationflow.py

2.2.8.2.1. Graph

2.2.8.2.2. Nodes

2.2.8.2.2.1. elaborate/0

Keypath	Type	Value
[flowgraph,sv2velaborationflow,elaborate,0,task]	str	elaborate
[flowgraph,sv2velaborationflow,elaborate,0,taskmodule]	str	siliconcompiler.tools.slang.elaborate/Elaborate
[flowgraph,sv2velaborationflow,elaborate,0,tool]	str	slang

2.2.8.2.2.2. convert/0

Keypath	Type	Value
[flowgraph,sv2velaborationflow,convert,0,input]	[(str,str)]	('elaborate', '0')
[flowgraph,sv2velaborationflow,convert,0,task]	str	convert
[flowgraph,sv2velaborationflow,convert,0,taskmodule]	str	siliconcompiler.tools.sv2v.convert/ConvertTask
[flowgraph,sv2velaborationflow,convert,0,tool]	str	sv2v

2.2.8.3. hlselaborationflow

A High-Level Synthesis (HLS) elaboration flow.

This flow supports C-based HLS by using a ‘convert’ step which handles the conversion of HLS C code to RTL using the Bambu tool.

The final node, convert, emits Verilog.

File: elaborationflow.py

2.2.8.3.1. Graph

2.2.8.3.2. Nodes

2.2.8.3.2.1. convert/0

Keypath	Type	Value
[flowgraph,hlselaborationflow,convert,0,task]	str	convert
[flowgraph,hlselaborationflow,convert,0,taskmodule]	str	siliconcompiler.tools.bambu.convert/ConvertTask
[flowgraph,hlselaborationflow,convert,0,tool]	str	bambu

2.2.8.4. vhdlelaborationflow

A VHDL-based elaboration flow.

This flow supports VHDL input by using a ‘convert’ step which uses GHDL to analyze and elaborate the VHDL design.

The final node, convert, emits Verilog.

File: elaborationflow.py

2.2.8.4.1. Graph

2.2.8.4.2. Nodes

2.2.8.4.2.1. convert/0

Keypath	Type	Value
[flowgraph,vhdlelaborationflow,convert,0,task]	str	convert
[flowgraph,vhdlelaborationflow,convert,0,taskmodule]	str	siliconcompiler.tools.ghdl.convert/ConvertTask
[flowgraph,vhdlelaborationflow,convert,0,tool]	str	ghdl

2.2.8.5. chiselelaborationflow

A Chisel-based elaboration flow.

This flow supports designs written in the Chisel hardware construction language by using a ‘convert’ step that uses the Chisel compiler to generate Verilog from the Chisel source.

The final node, convert, emits Verilog.

File: elaborationflow.py

2.2.8.5.1. Graph

2.2.8.5.2. Nodes

2.2.8.5.2.1. convert/0

Keypath	Type	Value
[flowgraph,chiselelaborationflow,convert,0,task]	str	convert
[flowgraph,chiselelaborationflow,convert,0,taskmodule]	str	siliconcompiler.tools.chisel.convert/ConvertTask
[flowgraph,chiselelaborationflow,convert,0,tool]	str	chisel

2.2.8.6. bluespecelaborationflow

A Bluespec-based elaboration flow.

This flow supports designs written in the Bluespec hardware construction language by using a ‘convert’ step that uses the Bluespec compiler to generate Verilog from the Bluespec source.

The final node, convert, emits Verilog.

File: elaborationflow.py

2.2.8.6.1. Graph

2.2.8.6.2. Nodes

2.2.8.6.2.1. convert/0

Keypath	Type	Value
[flowgraph,bluespecelaborationflow,convert,0,task]	str	convert
[flowgraph,bluespecelaborationflow,convert,0,taskmodule]	str	siliconcompiler.tools.bluespec.convert/ConvertTask
[flowgraph,bluespecelaborationflow,convert,0,tool]	str	bluespec

2.3. Synthesis Flows

Flows that elaborate and synthesize an RTL design into a gate-level netlist. Each variant pairs a different front-end language with the shared Yosys synthesis step.

2.3.1. synflow-verilog / 0

A configurable ASIC synthesis flow with static timing analysis.

This flow translates RTL designs into a gate-level netlist and then performs static timing analysis (STA) on the result. It allows for parallel execution of both synthesis and timing steps to explore different strategies or speed up execution.

The flow consists of the following steps:

• elaborate: Elaborates the RTL design from its source files.

• synthesis: Translates the elaborated RTL into a gate-level netlist

  using Yosys.

• timing: Performs static timing analysis on the synthesized netlist

  using OpenSTA.

File: synflow.py

2.3.1.1. Graph

2.3.1.2. Nodes

2.3.1.2.1. elaborate/0

Keypath	Type	Value
[flowgraph,synflow-verilog,elaborate,0,task]	str	elaborate
[flowgraph,synflow-verilog,elaborate,0,taskmodule]	str	siliconcompiler.tools.slang.elaborate/Elaborate
[flowgraph,synflow-verilog,elaborate,0,tool]	str	slang

2.3.1.2.2. synthesis/0

Keypath	Type	Value
[flowgraph,synflow-verilog,synthesis,0,goal,errors]	float	0.0
[flowgraph,synflow-verilog,synthesis,0,input]	[(str,str)]	('elaborate', '0')
[flowgraph,synflow-verilog,synthesis,0,task]	str	syn_asic
[flowgraph,synflow-verilog,synthesis,0,taskmodule]	str	siliconcompiler.tools.yosys.syn_asic/ASICSynthesis
[flowgraph,synflow-verilog,synthesis,0,tool]	str	yosys

2.3.1.2.3. synthesis/1

Keypath	Type	Value
[flowgraph,synflow-verilog,synthesis,1,goal,errors]	float	0.0
[flowgraph,synflow-verilog,synthesis,1,input]	[(str,str)]	('elaborate', '0')
[flowgraph,synflow-verilog,synthesis,1,task]	str	syn_asic
[flowgraph,synflow-verilog,synthesis,1,taskmodule]	str	siliconcompiler.tools.yosys.syn_asic/ASICSynthesis
[flowgraph,synflow-verilog,synthesis,1,tool]	str	yosys

2.3.1.2.4. synthesis/2

Keypath	Type	Value
[flowgraph,synflow-verilog,synthesis,2,goal,errors]	float	0.0
[flowgraph,synflow-verilog,synthesis,2,input]	[(str,str)]	('elaborate', '0')
[flowgraph,synflow-verilog,synthesis,2,task]	str	syn_asic
[flowgraph,synflow-verilog,synthesis,2,taskmodule]	str	siliconcompiler.tools.yosys.syn_asic/ASICSynthesis
[flowgraph,synflow-verilog,synthesis,2,tool]	str	yosys

2.3.1.2.5. min/0

Keypath	Type	Value
[flowgraph,synflow-verilog,min,0,input]	[(str,str)]	('synthesis', '0') ('synthesis', '1') ('synthesis', '2')
[flowgraph,synflow-verilog,min,0,task]	str	minimum
[flowgraph,synflow-verilog,min,0,taskmodule]	str	siliconcompiler.tools.builtin.minimum/MinimumTask
[flowgraph,synflow-verilog,min,0,tool]	str	builtin

2.3.1.2.6. timing/0

Keypath	Type	Value
[flowgraph,synflow-verilog,timing,0,input]	[(str,str)]	('min', '0')
[flowgraph,synflow-verilog,timing,0,task]	str	timing
[flowgraph,synflow-verilog,timing,0,taskmodule]	str	siliconcompiler.tools.opensta.timing/TimingTask
[flowgraph,synflow-verilog,timing,0,tool]	str	opensta

2.3.1.2.7. timing/1

Keypath	Type	Value
[flowgraph,synflow-verilog,timing,1,input]	[(str,str)]	('min', '0')
[flowgraph,synflow-verilog,timing,1,task]	str	timing
[flowgraph,synflow-verilog,timing,1,taskmodule]	str	siliconcompiler.tools.opensta.timing/TimingTask
[flowgraph,synflow-verilog,timing,1,tool]	str	opensta

2.3.1.2.8. timing/2

Keypath	Type	Value
[flowgraph,synflow-verilog,timing,2,input]	[(str,str)]	('min', '0')
[flowgraph,synflow-verilog,timing,2,task]	str	timing
[flowgraph,synflow-verilog,timing,2,taskmodule]	str	siliconcompiler.tools.opensta.timing/TimingTask
[flowgraph,synflow-verilog,timing,2,tool]	str	opensta

2.3.2. synflow-systemverilog-sv2v / 1

A configurable ASIC synthesis flow with static timing analysis.

This flow translates RTL designs into a gate-level netlist and then performs static timing analysis (STA) on the result. It allows for parallel execution of both synthesis and timing steps to explore different strategies or speed up execution.

The flow consists of the following steps:

• elaborate: Elaborates the RTL design from its source files.

• synthesis: Translates the elaborated RTL into a gate-level netlist

  using Yosys.

• timing: Performs static timing analysis on the synthesized netlist

  using OpenSTA.

File: synflow.py

2.3.2.1. Graph

2.3.2.2. Nodes

2.3.2.2.1. elaborate/0

Keypath	Type	Value
[flowgraph,synflow-systemverilog-sv2v,elaborate,0,task]	str	elaborate
[flowgraph,synflow-systemverilog-sv2v,elaborate,0,taskmodule]	str	siliconcompiler.tools.slang.elaborate/Elaborate
[flowgraph,synflow-systemverilog-sv2v,elaborate,0,tool]	str	slang

2.3.2.2.2. convert/0

Keypath	Type	Value
[flowgraph,synflow-systemverilog-sv2v,convert,0,input]	[(str,str)]	('elaborate', '0')
[flowgraph,synflow-systemverilog-sv2v,convert,0,task]	str	convert
[flowgraph,synflow-systemverilog-sv2v,convert,0,taskmodule]	str	siliconcompiler.tools.sv2v.convert/ConvertTask
[flowgraph,synflow-systemverilog-sv2v,convert,0,tool]	str	sv2v

2.3.2.2.3. synthesis/0

Keypath	Type	Value
[flowgraph,synflow-systemverilog-sv2v,synthesis,0,goal,errors]	float	0.0
[flowgraph,synflow-systemverilog-sv2v,synthesis,0,input]	[(str,str)]	('convert', '0')
[flowgraph,synflow-systemverilog-sv2v,synthesis,0,task]	str	syn_asic
[flowgraph,synflow-systemverilog-sv2v,synthesis,0,taskmodule]	str	siliconcompiler.tools.yosys.syn_asic/ASICSynthesis
[flowgraph,synflow-systemverilog-sv2v,synthesis,0,tool]	str	yosys

2.3.2.2.4. synthesis/1

Keypath	Type	Value
[flowgraph,synflow-systemverilog-sv2v,synthesis,1,goal,errors]	float	0.0
[flowgraph,synflow-systemverilog-sv2v,synthesis,1,input]	[(str,str)]	('convert', '0')
[flowgraph,synflow-systemverilog-sv2v,synthesis,1,task]	str	syn_asic
[flowgraph,synflow-systemverilog-sv2v,synthesis,1,taskmodule]	str	siliconcompiler.tools.yosys.syn_asic/ASICSynthesis
[flowgraph,synflow-systemverilog-sv2v,synthesis,1,tool]	str	yosys

2.3.2.2.5. synthesis/2

Keypath	Type	Value
[flowgraph,synflow-systemverilog-sv2v,synthesis,2,goal,errors]	float	0.0
[flowgraph,synflow-systemverilog-sv2v,synthesis,2,input]	[(str,str)]	('convert', '0')
[flowgraph,synflow-systemverilog-sv2v,synthesis,2,task]	str	syn_asic
[flowgraph,synflow-systemverilog-sv2v,synthesis,2,taskmodule]	str	siliconcompiler.tools.yosys.syn_asic/ASICSynthesis
[flowgraph,synflow-systemverilog-sv2v,synthesis,2,tool]	str	yosys

2.3.2.2.6. min/0

Keypath	Type	Value
[flowgraph,synflow-systemverilog-sv2v,min,0,input]	[(str,str)]	('synthesis', '0') ('synthesis', '1') ('synthesis', '2')
[flowgraph,synflow-systemverilog-sv2v,min,0,task]	str	minimum
[flowgraph,synflow-systemverilog-sv2v,min,0,taskmodule]	str	siliconcompiler.tools.builtin.minimum/MinimumTask
[flowgraph,synflow-systemverilog-sv2v,min,0,tool]	str	builtin

2.3.2.2.7. timing/0

Keypath	Type	Value
[flowgraph,synflow-systemverilog-sv2v,timing,0,input]	[(str,str)]	('min', '0')
[flowgraph,synflow-systemverilog-sv2v,timing,0,task]	str	timing
[flowgraph,synflow-systemverilog-sv2v,timing,0,taskmodule]	str	siliconcompiler.tools.opensta.timing/TimingTask
[flowgraph,synflow-systemverilog-sv2v,timing,0,tool]	str	opensta

2.3.2.2.8. timing/1

Keypath	Type	Value
[flowgraph,synflow-systemverilog-sv2v,timing,1,input]	[(str,str)]	('min', '0')
[flowgraph,synflow-systemverilog-sv2v,timing,1,task]	str	timing
[flowgraph,synflow-systemverilog-sv2v,timing,1,taskmodule]	str	siliconcompiler.tools.opensta.timing/TimingTask
[flowgraph,synflow-systemverilog-sv2v,timing,1,tool]	str	opensta

2.3.2.2.9. timing/2

Keypath	Type	Value
[flowgraph,synflow-systemverilog-sv2v,timing,2,input]	[(str,str)]	('min', '0')
[flowgraph,synflow-systemverilog-sv2v,timing,2,task]	str	timing
[flowgraph,synflow-systemverilog-sv2v,timing,2,taskmodule]	str	siliconcompiler.tools.opensta.timing/TimingTask
[flowgraph,synflow-systemverilog-sv2v,timing,2,tool]	str	opensta

2.3.3. synflow-chisel / 2

A configurable ASIC synthesis flow with static timing analysis.

This flow translates RTL designs into a gate-level netlist and then performs static timing analysis (STA) on the result. It allows for parallel execution of both synthesis and timing steps to explore different strategies or speed up execution.

The flow consists of the following steps:

• elaborate: Elaborates the RTL design from its source files.

• synthesis: Translates the elaborated RTL into a gate-level netlist

  using Yosys.

• timing: Performs static timing analysis on the synthesized netlist

  using OpenSTA.

File: synflow.py

2.3.3.1. Graph

2.3.3.2. Nodes

2.3.3.2.1. convert/0

Keypath	Type	Value
[flowgraph,synflow-chisel,convert,0,task]	str	convert
[flowgraph,synflow-chisel,convert,0,taskmodule]	str	siliconcompiler.tools.chisel.convert/ConvertTask
[flowgraph,synflow-chisel,convert,0,tool]	str	chisel

2.3.3.2.2. synthesis/0

Keypath	Type	Value
[flowgraph,synflow-chisel,synthesis,0,goal,errors]	float	0.0
[flowgraph,synflow-chisel,synthesis,0,input]	[(str,str)]	('convert', '0')
[flowgraph,synflow-chisel,synthesis,0,task]	str	syn_asic
[flowgraph,synflow-chisel,synthesis,0,taskmodule]	str	siliconcompiler.tools.yosys.syn_asic/ASICSynthesis
[flowgraph,synflow-chisel,synthesis,0,tool]	str	yosys

2.3.3.2.3. synthesis/1

Keypath	Type	Value
[flowgraph,synflow-chisel,synthesis,1,goal,errors]	float	0.0
[flowgraph,synflow-chisel,synthesis,1,input]	[(str,str)]	('convert', '0')
[flowgraph,synflow-chisel,synthesis,1,task]	str	syn_asic
[flowgraph,synflow-chisel,synthesis,1,taskmodule]	str	siliconcompiler.tools.yosys.syn_asic/ASICSynthesis
[flowgraph,synflow-chisel,synthesis,1,tool]	str	yosys

2.3.3.2.4. synthesis/2

Keypath	Type	Value
[flowgraph,synflow-chisel,synthesis,2,goal,errors]	float	0.0
[flowgraph,synflow-chisel,synthesis,2,input]	[(str,str)]	('convert', '0')
[flowgraph,synflow-chisel,synthesis,2,task]	str	syn_asic
[flowgraph,synflow-chisel,synthesis,2,taskmodule]	str	siliconcompiler.tools.yosys.syn_asic/ASICSynthesis
[flowgraph,synflow-chisel,synthesis,2,tool]	str	yosys

2.3.3.2.5. min/0

Keypath	Type	Value
[flowgraph,synflow-chisel,min,0,input]	[(str,str)]	('synthesis', '0') ('synthesis', '1') ('synthesis', '2')
[flowgraph,synflow-chisel,min,0,task]	str	minimum
[flowgraph,synflow-chisel,min,0,taskmodule]	str	siliconcompiler.tools.builtin.minimum/MinimumTask
[flowgraph,synflow-chisel,min,0,tool]	str	builtin

2.3.3.2.6. timing/0

Keypath	Type	Value
[flowgraph,synflow-chisel,timing,0,input]	[(str,str)]	('min', '0')
[flowgraph,synflow-chisel,timing,0,task]	str	timing
[flowgraph,synflow-chisel,timing,0,taskmodule]	str	siliconcompiler.tools.opensta.timing/TimingTask
[flowgraph,synflow-chisel,timing,0,tool]	str	opensta

2.3.3.2.7. timing/1

Keypath	Type	Value
[flowgraph,synflow-chisel,timing,1,input]	[(str,str)]	('min', '0')
[flowgraph,synflow-chisel,timing,1,task]	str	timing
[flowgraph,synflow-chisel,timing,1,taskmodule]	str	siliconcompiler.tools.opensta.timing/TimingTask
[flowgraph,synflow-chisel,timing,1,tool]	str	opensta

2.3.3.2.8. timing/2

Keypath	Type	Value
[flowgraph,synflow-chisel,timing,2,input]	[(str,str)]	('min', '0')
[flowgraph,synflow-chisel,timing,2,task]	str	timing
[flowgraph,synflow-chisel,timing,2,taskmodule]	str	siliconcompiler.tools.opensta.timing/TimingTask
[flowgraph,synflow-chisel,timing,2,tool]	str	opensta

2.3.4. synflow-vhdl / 3

A configurable ASIC synthesis flow with static timing analysis.

This flow translates RTL designs into a gate-level netlist and then performs static timing analysis (STA) on the result. It allows for parallel execution of both synthesis and timing steps to explore different strategies or speed up execution.

The flow consists of the following steps:

• elaborate: Elaborates the RTL design from its source files.

• synthesis: Translates the elaborated RTL into a gate-level netlist

  using Yosys.

• timing: Performs static timing analysis on the synthesized netlist

  using OpenSTA.

File: synflow.py

2.3.4.1. Graph

2.3.4.2. Nodes

2.3.4.2.1. convert/0

Keypath	Type	Value
[flowgraph,synflow-vhdl,convert,0,task]	str	convert
[flowgraph,synflow-vhdl,convert,0,taskmodule]	str	siliconcompiler.tools.ghdl.convert/ConvertTask
[flowgraph,synflow-vhdl,convert,0,tool]	str	ghdl

2.3.4.2.2. synthesis/0

Keypath	Type	Value
[flowgraph,synflow-vhdl,synthesis,0,goal,errors]	float	0.0
[flowgraph,synflow-vhdl,synthesis,0,input]	[(str,str)]	('convert', '0')
[flowgraph,synflow-vhdl,synthesis,0,task]	str	syn_asic
[flowgraph,synflow-vhdl,synthesis,0,taskmodule]	str	siliconcompiler.tools.yosys.syn_asic/ASICSynthesis
[flowgraph,synflow-vhdl,synthesis,0,tool]	str	yosys

2.3.4.2.3. synthesis/1

Keypath	Type	Value
[flowgraph,synflow-vhdl,synthesis,1,goal,errors]	float	0.0
[flowgraph,synflow-vhdl,synthesis,1,input]	[(str,str)]	('convert', '0')
[flowgraph,synflow-vhdl,synthesis,1,task]	str	syn_asic
[flowgraph,synflow-vhdl,synthesis,1,taskmodule]	str	siliconcompiler.tools.yosys.syn_asic/ASICSynthesis
[flowgraph,synflow-vhdl,synthesis,1,tool]	str	yosys

2.3.4.2.4. synthesis/2

Keypath	Type	Value
[flowgraph,synflow-vhdl,synthesis,2,goal,errors]	float	0.0
[flowgraph,synflow-vhdl,synthesis,2,input]	[(str,str)]	('convert', '0')
[flowgraph,synflow-vhdl,synthesis,2,task]	str	syn_asic
[flowgraph,synflow-vhdl,synthesis,2,taskmodule]	str	siliconcompiler.tools.yosys.syn_asic/ASICSynthesis
[flowgraph,synflow-vhdl,synthesis,2,tool]	str	yosys

2.3.4.2.5. min/0

Keypath	Type	Value
[flowgraph,synflow-vhdl,min,0,input]	[(str,str)]	('synthesis', '0') ('synthesis', '1') ('synthesis', '2')
[flowgraph,synflow-vhdl,min,0,task]	str	minimum
[flowgraph,synflow-vhdl,min,0,taskmodule]	str	siliconcompiler.tools.builtin.minimum/MinimumTask
[flowgraph,synflow-vhdl,min,0,tool]	str	builtin

2.3.4.2.6. timing/0

Keypath	Type	Value
[flowgraph,synflow-vhdl,timing,0,input]	[(str,str)]	('min', '0')
[flowgraph,synflow-vhdl,timing,0,task]	str	timing
[flowgraph,synflow-vhdl,timing,0,taskmodule]	str	siliconcompiler.tools.opensta.timing/TimingTask
[flowgraph,synflow-vhdl,timing,0,tool]	str	opensta

2.3.4.2.7. timing/1

Keypath	Type	Value
[flowgraph,synflow-vhdl,timing,1,input]	[(str,str)]	('min', '0')
[flowgraph,synflow-vhdl,timing,1,task]	str	timing
[flowgraph,synflow-vhdl,timing,1,taskmodule]	str	siliconcompiler.tools.opensta.timing/TimingTask
[flowgraph,synflow-vhdl,timing,1,tool]	str	opensta

2.3.4.2.8. timing/2

Keypath	Type	Value
[flowgraph,synflow-vhdl,timing,2,input]	[(str,str)]	('min', '0')
[flowgraph,synflow-vhdl,timing,2,task]	str	timing
[flowgraph,synflow-vhdl,timing,2,taskmodule]	str	siliconcompiler.tools.opensta.timing/TimingTask
[flowgraph,synflow-vhdl,timing,2,tool]	str	opensta

2.3.5. synflow-hls / 4

A configurable ASIC synthesis flow with static timing analysis.

This flow translates RTL designs into a gate-level netlist and then performs static timing analysis (STA) on the result. It allows for parallel execution of both synthesis and timing steps to explore different strategies or speed up execution.

The flow consists of the following steps:

• elaborate: Elaborates the RTL design from its source files.

• synthesis: Translates the elaborated RTL into a gate-level netlist

  using Yosys.

• timing: Performs static timing analysis on the synthesized netlist

  using OpenSTA.

File: synflow.py

2.3.5.1. Graph

2.3.5.2. Nodes

2.3.5.2.1. convert/0

Keypath	Type	Value
[flowgraph,synflow-hls,convert,0,task]	str	convert
[flowgraph,synflow-hls,convert,0,taskmodule]	str	siliconcompiler.tools.bambu.convert/ConvertTask
[flowgraph,synflow-hls,convert,0,tool]	str	bambu

2.3.5.2.2. synthesis/0

Keypath	Type	Value
[flowgraph,synflow-hls,synthesis,0,goal,errors]	float	0.0
[flowgraph,synflow-hls,synthesis,0,input]	[(str,str)]	('convert', '0')
[flowgraph,synflow-hls,synthesis,0,task]	str	syn_asic
[flowgraph,synflow-hls,synthesis,0,taskmodule]	str	siliconcompiler.tools.yosys.syn_asic/ASICSynthesis
[flowgraph,synflow-hls,synthesis,0,tool]	str	yosys

2.3.5.2.3. synthesis/1

Keypath	Type	Value
[flowgraph,synflow-hls,synthesis,1,goal,errors]	float	0.0
[flowgraph,synflow-hls,synthesis,1,input]	[(str,str)]	('convert', '0')
[flowgraph,synflow-hls,synthesis,1,task]	str	syn_asic
[flowgraph,synflow-hls,synthesis,1,taskmodule]	str	siliconcompiler.tools.yosys.syn_asic/ASICSynthesis
[flowgraph,synflow-hls,synthesis,1,tool]	str	yosys

2.3.5.2.4. synthesis/2

Keypath	Type	Value
[flowgraph,synflow-hls,synthesis,2,goal,errors]	float	0.0
[flowgraph,synflow-hls,synthesis,2,input]	[(str,str)]	('convert', '0')
[flowgraph,synflow-hls,synthesis,2,task]	str	syn_asic
[flowgraph,synflow-hls,synthesis,2,taskmodule]	str	siliconcompiler.tools.yosys.syn_asic/ASICSynthesis
[flowgraph,synflow-hls,synthesis,2,tool]	str	yosys

2.3.5.2.5. min/0

Keypath	Type	Value
[flowgraph,synflow-hls,min,0,input]	[(str,str)]	('synthesis', '0') ('synthesis', '1') ('synthesis', '2')
[flowgraph,synflow-hls,min,0,task]	str	minimum
[flowgraph,synflow-hls,min,0,taskmodule]	str	siliconcompiler.tools.builtin.minimum/MinimumTask
[flowgraph,synflow-hls,min,0,tool]	str	builtin

2.3.5.2.6. timing/0

Keypath	Type	Value
[flowgraph,synflow-hls,timing,0,input]	[(str,str)]	('min', '0')
[flowgraph,synflow-hls,timing,0,task]	str	timing
[flowgraph,synflow-hls,timing,0,taskmodule]	str	siliconcompiler.tools.opensta.timing/TimingTask
[flowgraph,synflow-hls,timing,0,tool]	str	opensta

2.3.5.2.7. timing/1

Keypath	Type	Value
[flowgraph,synflow-hls,timing,1,input]	[(str,str)]	('min', '0')
[flowgraph,synflow-hls,timing,1,task]	str	timing
[flowgraph,synflow-hls,timing,1,taskmodule]	str	siliconcompiler.tools.opensta.timing/TimingTask
[flowgraph,synflow-hls,timing,1,tool]	str	opensta

2.3.5.2.8. timing/2

Keypath	Type	Value
[flowgraph,synflow-hls,timing,2,input]	[(str,str)]	('min', '0')
[flowgraph,synflow-hls,timing,2,task]	str	timing
[flowgraph,synflow-hls,timing,2,taskmodule]	str	siliconcompiler.tools.opensta.timing/TimingTask
[flowgraph,synflow-hls,timing,2,tool]	str	opensta

2.3.6. synflow-bluespec / 5

A configurable ASIC synthesis flow with static timing analysis.

This flow translates RTL designs into a gate-level netlist and then performs static timing analysis (STA) on the result. It allows for parallel execution of both synthesis and timing steps to explore different strategies or speed up execution.

The flow consists of the following steps:

• elaborate: Elaborates the RTL design from its source files.

• synthesis: Translates the elaborated RTL into a gate-level netlist

  using Yosys.

• timing: Performs static timing analysis on the synthesized netlist

  using OpenSTA.

File: synflow.py

2.3.6.1. Graph

2.3.6.2. Nodes

2.3.6.2.1. convert/0

Keypath	Type	Value
[flowgraph,synflow-bluespec,convert,0,task]	str	convert
[flowgraph,synflow-bluespec,convert,0,taskmodule]	str	siliconcompiler.tools.bluespec.convert/ConvertTask
[flowgraph,synflow-bluespec,convert,0,tool]	str	bluespec

2.3.6.2.2. synthesis/0

Keypath	Type	Value
[flowgraph,synflow-bluespec,synthesis,0,goal,errors]	float	0.0
[flowgraph,synflow-bluespec,synthesis,0,input]	[(str,str)]	('convert', '0')
[flowgraph,synflow-bluespec,synthesis,0,task]	str	syn_asic
[flowgraph,synflow-bluespec,synthesis,0,taskmodule]	str	siliconcompiler.tools.yosys.syn_asic/ASICSynthesis
[flowgraph,synflow-bluespec,synthesis,0,tool]	str	yosys

2.3.6.2.3. synthesis/1

Keypath	Type	Value
[flowgraph,synflow-bluespec,synthesis,1,goal,errors]	float	0.0
[flowgraph,synflow-bluespec,synthesis,1,input]	[(str,str)]	('convert', '0')
[flowgraph,synflow-bluespec,synthesis,1,task]	str	syn_asic
[flowgraph,synflow-bluespec,synthesis,1,taskmodule]	str	siliconcompiler.tools.yosys.syn_asic/ASICSynthesis
[flowgraph,synflow-bluespec,synthesis,1,tool]	str	yosys

2.3.6.2.4. synthesis/2

Keypath	Type	Value
[flowgraph,synflow-bluespec,synthesis,2,goal,errors]	float	0.0
[flowgraph,synflow-bluespec,synthesis,2,input]	[(str,str)]	('convert', '0')
[flowgraph,synflow-bluespec,synthesis,2,task]	str	syn_asic
[flowgraph,synflow-bluespec,synthesis,2,taskmodule]	str	siliconcompiler.tools.yosys.syn_asic/ASICSynthesis
[flowgraph,synflow-bluespec,synthesis,2,tool]	str	yosys

2.3.6.2.5. min/0

Keypath	Type	Value
[flowgraph,synflow-bluespec,min,0,input]	[(str,str)]	('synthesis', '0') ('synthesis', '1') ('synthesis', '2')
[flowgraph,synflow-bluespec,min,0,task]	str	minimum
[flowgraph,synflow-bluespec,min,0,taskmodule]	str	siliconcompiler.tools.builtin.minimum/MinimumTask
[flowgraph,synflow-bluespec,min,0,tool]	str	builtin

2.3.6.2.6. timing/0

Keypath	Type	Value
[flowgraph,synflow-bluespec,timing,0,input]	[(str,str)]	('min', '0')
[flowgraph,synflow-bluespec,timing,0,task]	str	timing
[flowgraph,synflow-bluespec,timing,0,taskmodule]	str	siliconcompiler.tools.opensta.timing/TimingTask
[flowgraph,synflow-bluespec,timing,0,tool]	str	opensta

2.3.6.2.7. timing/1

Keypath	Type	Value
[flowgraph,synflow-bluespec,timing,1,input]	[(str,str)]	('min', '0')
[flowgraph,synflow-bluespec,timing,1,task]	str	timing
[flowgraph,synflow-bluespec,timing,1,taskmodule]	str	siliconcompiler.tools.opensta.timing/TimingTask
[flowgraph,synflow-bluespec,timing,1,tool]	str	opensta

2.3.6.2.8. timing/2

Keypath	Type	Value
[flowgraph,synflow-bluespec,timing,2,input]	[(str,str)]	('min', '0')
[flowgraph,synflow-bluespec,timing,2,task]	str	timing
[flowgraph,synflow-bluespec,timing,2,taskmodule]	str	siliconcompiler.tools.opensta.timing/TimingTask
[flowgraph,synflow-bluespec,timing,2,tool]	str	opensta

2.4. Lint Flows

Flows for linting an RTL design.

2.4.1. lintflow-all / 0

An RTL linting flow.

This flow is designed to check RTL source files for stylistic, semantic, and syntactic issues using a specified linting tool.

Supported tools:

• ‘slang’: A linter based on the Slang compiler.

• ‘verilator’: A linter based on the Verilator tool.

File: lintflow.py

2.4.1.1. Graph

2.4.1.2. Nodes

2.4.1.2.1. slang.lint/0

Keypath	Type	Value
[flowgraph,lintflow-all,slang.lint,0,task]	str	lint
[flowgraph,lintflow-all,slang.lint,0,taskmodule]	str	siliconcompiler.tools.slang.lint/Lint
[flowgraph,lintflow-all,slang.lint,0,tool]	str	slang

2.4.1.2.2. verilator.lint/0

Keypath	Type	Value
[flowgraph,lintflow-all,verilator.lint,0,task]	str	lint
[flowgraph,lintflow-all,verilator.lint,0,taskmodule]	str	siliconcompiler.tools.verilator.lint/LintTask
[flowgraph,lintflow-all,verilator.lint,0,tool]	str	verilator

2.4.2. lintflow-slang / 1

An RTL linting flow.

This flow is designed to check RTL source files for stylistic, semantic, and syntactic issues using a specified linting tool.

Supported tools:

• ‘slang’: A linter based on the Slang compiler.

• ‘verilator’: A linter based on the Verilator tool.

File: lintflow.py

2.4.2.1. Graph

2.4.2.2. Nodes

2.4.2.2.1. lint/0

Keypath	Type	Value
[flowgraph,lintflow-slang,lint,0,task]	str	lint
[flowgraph,lintflow-slang,lint,0,taskmodule]	str	siliconcompiler.tools.slang.lint/Lint
[flowgraph,lintflow-slang,lint,0,tool]	str	slang

2.4.3. lintflow-verilator / 2

An RTL linting flow.

This flow is designed to check RTL source files for stylistic, semantic, and syntactic issues using a specified linting tool.

Supported tools:

• ‘slang’: A linter based on the Slang compiler.

• ‘verilator’: A linter based on the Verilator tool.

File: lintflow.py

2.4.3.1. Graph

2.4.3.2. Nodes

2.4.3.2.1. lint/0

Keypath	Type	Value
[flowgraph,lintflow-verilator,lint,0,task]	str	lint
[flowgraph,lintflow-verilator,lint,0,taskmodule]	str	siliconcompiler.tools.verilator.lint/LintTask
[flowgraph,lintflow-verilator,lint,0,tool]	str	verilator

2.4.4. verilatorlintflow

A Verilator-based RTL linting flow.

This flow is designed to check RTL source files for stylistic, semantic, and syntactic issues using the Verilator tool.

File: lintflow.py

2.4.4.1. Graph

2.4.4.2. Nodes

2.4.4.2.1. lint/0

Keypath	Type	Value
[flowgraph,verilatorlintflow,lint,0,task]	str	lint
[flowgraph,verilatorlintflow,lint,0,taskmodule]	str	siliconcompiler.tools.verilator.lint/LintTask
[flowgraph,verilatorlintflow,lint,0,tool]	str	verilator

2.4.5. slanglintflow

A Slang-based RTL linting flow.

This flow is designed to check RTL source files for stylistic, semantic, and syntactic issues using the Slang compiler.

File: lintflow.py

2.4.5.1. Graph

2.4.5.2. Nodes

2.4.5.2.1. lint/0

Keypath	Type	Value
[flowgraph,slanglintflow,lint,0,task]	str	lint
[flowgraph,slanglintflow,lint,0,taskmodule]	str	siliconcompiler.tools.slang.lint/Lint
[flowgraph,slanglintflow,lint,0,tool]	str	slang

2.5. Design Verification Flows

Flows for simulating and verifying a design. Each variant targets a specific simulator (and optionally cocotb-based testbenches).

2.5.1. dvflow-icarus / 0

A configurable constrained random stimulus DV flow.

The verification pipeline includes the following steps:

• compile: RTL sources are compiled into an intermediate format.

• sim: The compiled design is simulated with a generated testbench.

The dvflow can be parametrized using the ‘np’ parameter. Setting ‘np’ > 1 results in multiple independent verification pipelines being launched in parallel.

Supported tools are:

• ‘icarus’: Compiles and simulates with the Icarus Verilog simulator.

• ‘icarus-cocotb’: Compiles with Icarus and runs cocotb Python testbenches.

• ‘verilator’: Compiles and simulates with Verilator.

• ‘verilator-cocotb’: Compiles with Verilator and runs cocotb Python testbenches.

• ‘xyce’: Simulates a netlist with the Xyce circuit simulator.

• ‘xdm-xyce’: Converts a design to a Xyce-compatible format and simulates.

File: dvflow.py

2.5.1.1. Graph

2.5.1.2. Nodes

2.5.1.2.1. compile/0

Keypath	Type	Value
[flowgraph,dvflow-icarus,compile,0,task]	str	compile
[flowgraph,dvflow-icarus,compile,0,taskmodule]	str	siliconcompiler.tools.icarus.compile/CompileTask
[flowgraph,dvflow-icarus,compile,0,tool]	str	icarus

2.5.1.2.2. simulate/0

Keypath	Type	Value
[flowgraph,dvflow-icarus,simulate,0,input]	[(str,str)]	('compile', '0')
[flowgraph,dvflow-icarus,simulate,0,task]	str	exec_input
[flowgraph,dvflow-icarus,simulate,0,taskmodule]	str	siliconcompiler.tools.execute.exec_input/ExecInputTask
[flowgraph,dvflow-icarus,simulate,0,tool]	str	execute

2.5.1.2.3. simulate/1

Keypath	Type	Value
[flowgraph,dvflow-icarus,simulate,1,input]	[(str,str)]	('compile', '0')
[flowgraph,dvflow-icarus,simulate,1,task]	str	exec_input
[flowgraph,dvflow-icarus,simulate,1,taskmodule]	str	siliconcompiler.tools.execute.exec_input/ExecInputTask
[flowgraph,dvflow-icarus,simulate,1,tool]	str	execute

2.5.1.2.4. simulate/2

Keypath	Type	Value
[flowgraph,dvflow-icarus,simulate,2,input]	[(str,str)]	('compile', '0')
[flowgraph,dvflow-icarus,simulate,2,task]	str	exec_input
[flowgraph,dvflow-icarus,simulate,2,taskmodule]	str	siliconcompiler.tools.execute.exec_input/ExecInputTask
[flowgraph,dvflow-icarus,simulate,2,tool]	str	execute

2.5.2. dvflow-icarus-cocotb / 1

A configurable constrained random stimulus DV flow.

The verification pipeline includes the following steps:

• compile: RTL sources are compiled into an intermediate format.

• sim: The compiled design is simulated with a generated testbench.

The dvflow can be parametrized using the ‘np’ parameter. Setting ‘np’ > 1 results in multiple independent verification pipelines being launched in parallel.

Supported tools are:

• ‘icarus’: Compiles and simulates with the Icarus Verilog simulator.

• ‘icarus-cocotb’: Compiles with Icarus and runs cocotb Python testbenches.

• ‘verilator’: Compiles and simulates with Verilator.

• ‘verilator-cocotb’: Compiles with Verilator and runs cocotb Python testbenches.

• ‘xyce’: Simulates a netlist with the Xyce circuit simulator.

• ‘xdm-xyce’: Converts a design to a Xyce-compatible format and simulates.

File: dvflow.py

2.5.2.1. Graph

2.5.2.2. Nodes

2.5.2.2.1. compile/0

Keypath	Type	Value
[flowgraph,dvflow-icarus-cocotb,compile,0,task]	str	compile
[flowgraph,dvflow-icarus-cocotb,compile,0,taskmodule]	str	siliconcompiler.tools.icarus.compile/CompileTask
[flowgraph,dvflow-icarus-cocotb,compile,0,tool]	str	icarus

2.5.2.2.2. simulate/0

Keypath	Type	Value
[flowgraph,dvflow-icarus-cocotb,simulate,0,input]	[(str,str)]	('compile', '0')
[flowgraph,dvflow-icarus-cocotb,simulate,0,task]	str	exec_cocotb
[flowgraph,dvflow-icarus-cocotb,simulate,0,taskmodule]	str	siliconcompiler.tools.icarus.cocotb_exec/CocotbExecTask
[flowgraph,dvflow-icarus-cocotb,simulate,0,tool]	str	icarus

2.5.2.2.3. simulate/1

Keypath	Type	Value
[flowgraph,dvflow-icarus-cocotb,simulate,1,input]	[(str,str)]	('compile', '0')
[flowgraph,dvflow-icarus-cocotb,simulate,1,task]	str	exec_cocotb
[flowgraph,dvflow-icarus-cocotb,simulate,1,taskmodule]	str	siliconcompiler.tools.icarus.cocotb_exec/CocotbExecTask
[flowgraph,dvflow-icarus-cocotb,simulate,1,tool]	str	icarus

2.5.2.2.4. simulate/2

Keypath	Type	Value
[flowgraph,dvflow-icarus-cocotb,simulate,2,input]	[(str,str)]	('compile', '0')
[flowgraph,dvflow-icarus-cocotb,simulate,2,task]	str	exec_cocotb
[flowgraph,dvflow-icarus-cocotb,simulate,2,taskmodule]	str	siliconcompiler.tools.icarus.cocotb_exec/CocotbExecTask
[flowgraph,dvflow-icarus-cocotb,simulate,2,tool]	str	icarus

2.5.3. dvflow-verilator / 2

A configurable constrained random stimulus DV flow.

The verification pipeline includes the following steps:

• compile: RTL sources are compiled into an intermediate format.

• sim: The compiled design is simulated with a generated testbench.

The dvflow can be parametrized using the ‘np’ parameter. Setting ‘np’ > 1 results in multiple independent verification pipelines being launched in parallel.

Supported tools are:

• ‘icarus’: Compiles and simulates with the Icarus Verilog simulator.

• ‘icarus-cocotb’: Compiles with Icarus and runs cocotb Python testbenches.

• ‘verilator’: Compiles and simulates with Verilator.

• ‘verilator-cocotb’: Compiles with Verilator and runs cocotb Python testbenches.

• ‘xyce’: Simulates a netlist with the Xyce circuit simulator.

• ‘xdm-xyce’: Converts a design to a Xyce-compatible format and simulates.

File: dvflow.py

2.5.3.1. Graph

2.5.3.2. Nodes

2.5.3.2.1. compile/0

Keypath	Type	Value
[flowgraph,dvflow-verilator,compile,0,task]	str	compile
[flowgraph,dvflow-verilator,compile,0,taskmodule]	str	siliconcompiler.tools.verilator.compile/CompileTask
[flowgraph,dvflow-verilator,compile,0,tool]	str	verilator

2.5.3.2.2. simulate/0

Keypath	Type	Value
[flowgraph,dvflow-verilator,simulate,0,input]	[(str,str)]	('compile', '0')
[flowgraph,dvflow-verilator,simulate,0,task]	str	exec_input
[flowgraph,dvflow-verilator,simulate,0,taskmodule]	str	siliconcompiler.tools.execute.exec_input/ExecInputTask
[flowgraph,dvflow-verilator,simulate,0,tool]	str	execute

2.5.3.2.3. simulate/1

Keypath	Type	Value
[flowgraph,dvflow-verilator,simulate,1,input]	[(str,str)]	('compile', '0')
[flowgraph,dvflow-verilator,simulate,1,task]	str	exec_input
[flowgraph,dvflow-verilator,simulate,1,taskmodule]	str	siliconcompiler.tools.execute.exec_input/ExecInputTask
[flowgraph,dvflow-verilator,simulate,1,tool]	str	execute

2.5.3.2.4. simulate/2

Keypath	Type	Value
[flowgraph,dvflow-verilator,simulate,2,input]	[(str,str)]	('compile', '0')
[flowgraph,dvflow-verilator,simulate,2,task]	str	exec_input
[flowgraph,dvflow-verilator,simulate,2,taskmodule]	str	siliconcompiler.tools.execute.exec_input/ExecInputTask
[flowgraph,dvflow-verilator,simulate,2,tool]	str	execute

2.5.4. dvflow-verilator-cocotb / 3

A configurable constrained random stimulus DV flow.

The verification pipeline includes the following steps:

• compile: RTL sources are compiled into an intermediate format.

• sim: The compiled design is simulated with a generated testbench.

The dvflow can be parametrized using the ‘np’ parameter. Setting ‘np’ > 1 results in multiple independent verification pipelines being launched in parallel.

Supported tools are:

• ‘icarus’: Compiles and simulates with the Icarus Verilog simulator.

• ‘icarus-cocotb’: Compiles with Icarus and runs cocotb Python testbenches.

• ‘verilator’: Compiles and simulates with Verilator.

• ‘verilator-cocotb’: Compiles with Verilator and runs cocotb Python testbenches.

• ‘xyce’: Simulates a netlist with the Xyce circuit simulator.

• ‘xdm-xyce’: Converts a design to a Xyce-compatible format and simulates.

File: dvflow.py

2.5.4.1. Graph

2.5.4.2. Nodes

2.5.4.2.1. compile/0

Keypath	Type	Value
[flowgraph,dvflow-verilator-cocotb,compile,0,task]	str	cocotb_compile
[flowgraph,dvflow-verilator-cocotb,compile,0,taskmodule]	str	siliconcompiler.tools.verilator.cocotb_compile/CocotbCompileTask
[flowgraph,dvflow-verilator-cocotb,compile,0,tool]	str	verilator

2.5.4.2.2. simulate/0

Keypath	Type	Value
[flowgraph,dvflow-verilator-cocotb,simulate,0,input]	[(str,str)]	('compile', '0')
[flowgraph,dvflow-verilator-cocotb,simulate,0,task]	str	exec_cocotb
[flowgraph,dvflow-verilator-cocotb,simulate,0,taskmodule]	str	siliconcompiler.tools.verilator.cocotb_exec/CocotbExecTask
[flowgraph,dvflow-verilator-cocotb,simulate,0,tool]	str	verilator

2.5.4.2.3. simulate/1

Keypath	Type	Value
[flowgraph,dvflow-verilator-cocotb,simulate,1,input]	[(str,str)]	('compile', '0')
[flowgraph,dvflow-verilator-cocotb,simulate,1,task]	str	exec_cocotb
[flowgraph,dvflow-verilator-cocotb,simulate,1,taskmodule]	str	siliconcompiler.tools.verilator.cocotb_exec/CocotbExecTask
[flowgraph,dvflow-verilator-cocotb,simulate,1,tool]	str	verilator

2.5.4.2.4. simulate/2

Keypath	Type	Value
[flowgraph,dvflow-verilator-cocotb,simulate,2,input]	[(str,str)]	('compile', '0')
[flowgraph,dvflow-verilator-cocotb,simulate,2,task]	str	exec_cocotb
[flowgraph,dvflow-verilator-cocotb,simulate,2,taskmodule]	str	siliconcompiler.tools.verilator.cocotb_exec/CocotbExecTask
[flowgraph,dvflow-verilator-cocotb,simulate,2,tool]	str	verilator

2.5.5. dvflow-xyce / 4

A configurable constrained random stimulus DV flow.

The verification pipeline includes the following steps:

• compile: RTL sources are compiled into an intermediate format.

• sim: The compiled design is simulated with a generated testbench.

The dvflow can be parametrized using the ‘np’ parameter. Setting ‘np’ > 1 results in multiple independent verification pipelines being launched in parallel.

Supported tools are:

• ‘icarus’: Compiles and simulates with the Icarus Verilog simulator.

• ‘icarus-cocotb’: Compiles with Icarus and runs cocotb Python testbenches.

• ‘verilator’: Compiles and simulates with Verilator.

• ‘verilator-cocotb’: Compiles with Verilator and runs cocotb Python testbenches.

• ‘xyce’: Simulates a netlist with the Xyce circuit simulator.

• ‘xdm-xyce’: Converts a design to a Xyce-compatible format and simulates.

File: dvflow.py

2.5.5.1. Graph

2.5.5.2. Nodes

2.5.5.2.1. simulate/0

Keypath	Type	Value
[flowgraph,dvflow-xyce,simulate,0,task]	str	simulate
[flowgraph,dvflow-xyce,simulate,0,taskmodule]	str	siliconcompiler.tools.xyce.simulate/SimulateTask
[flowgraph,dvflow-xyce,simulate,0,tool]	str	xyce

2.5.5.2.2. simulate/1

Keypath	Type	Value
[flowgraph,dvflow-xyce,simulate,1,task]	str	simulate
[flowgraph,dvflow-xyce,simulate,1,taskmodule]	str	siliconcompiler.tools.xyce.simulate/SimulateTask
[flowgraph,dvflow-xyce,simulate,1,tool]	str	xyce

2.5.5.2.3. simulate/2

Keypath	Type	Value
[flowgraph,dvflow-xyce,simulate,2,task]	str	simulate
[flowgraph,dvflow-xyce,simulate,2,taskmodule]	str	siliconcompiler.tools.xyce.simulate/SimulateTask
[flowgraph,dvflow-xyce,simulate,2,tool]	str	xyce

2.5.6. dvflow-xdm-xyce / 5

A configurable constrained random stimulus DV flow.

The verification pipeline includes the following steps:

• compile: RTL sources are compiled into an intermediate format.

• sim: The compiled design is simulated with a generated testbench.

The dvflow can be parametrized using the ‘np’ parameter. Setting ‘np’ > 1 results in multiple independent verification pipelines being launched in parallel.

Supported tools are:

• ‘icarus’: Compiles and simulates with the Icarus Verilog simulator.

• ‘icarus-cocotb’: Compiles with Icarus and runs cocotb Python testbenches.

• ‘verilator’: Compiles and simulates with Verilator.

• ‘verilator-cocotb’: Compiles with Verilator and runs cocotb Python testbenches.

• ‘xyce’: Simulates a netlist with the Xyce circuit simulator.

• ‘xdm-xyce’: Converts a design to a Xyce-compatible format and simulates.

File: dvflow.py

2.5.6.1. Graph

2.5.6.2. Nodes

2.5.6.2.1. compile/0

Keypath	Type	Value
[flowgraph,dvflow-xdm-xyce,compile,0,task]	str	convert
[flowgraph,dvflow-xdm-xyce,compile,0,taskmodule]	str	siliconcompiler.tools.xdm.convert/ConvertTask
[flowgraph,dvflow-xdm-xyce,compile,0,tool]	str	xdm

2.5.6.2.2. simulate/0

Keypath	Type	Value
[flowgraph,dvflow-xdm-xyce,simulate,0,input]	[(str,str)]	('compile', '0')
[flowgraph,dvflow-xdm-xyce,simulate,0,task]	str	simulate
[flowgraph,dvflow-xdm-xyce,simulate,0,taskmodule]	str	siliconcompiler.tools.xyce.simulate/SimulateTask
[flowgraph,dvflow-xdm-xyce,simulate,0,tool]	str	xyce

2.5.6.2.3. simulate/1

Keypath	Type	Value
[flowgraph,dvflow-xdm-xyce,simulate,1,input]	[(str,str)]	('compile', '0')
[flowgraph,dvflow-xdm-xyce,simulate,1,task]	str	simulate
[flowgraph,dvflow-xdm-xyce,simulate,1,taskmodule]	str	siliconcompiler.tools.xyce.simulate/SimulateTask
[flowgraph,dvflow-xdm-xyce,simulate,1,tool]	str	xyce

2.5.6.2.4. simulate/2

Keypath	Type	Value
[flowgraph,dvflow-xdm-xyce,simulate,2,input]	[(str,str)]	('compile', '0')
[flowgraph,dvflow-xdm-xyce,simulate,2,task]	str	simulate
[flowgraph,dvflow-xdm-xyce,simulate,2,taskmodule]	str	siliconcompiler.tools.xyce.simulate/SimulateTask
[flowgraph,dvflow-xdm-xyce,simulate,2,tool]	str	xyce

2.5.7. icarusdvflow

A DV flow using the Icarus Verilog simulator.

File: dvflow.py

2.5.7.1. Graph

2.5.7.2. Nodes

2.5.7.2.1. compile/0

Keypath	Type	Value
[flowgraph,icarusdvflow,compile,0,task]	str	compile
[flowgraph,icarusdvflow,compile,0,taskmodule]	str	siliconcompiler.tools.icarus.compile/CompileTask
[flowgraph,icarusdvflow,compile,0,tool]	str	icarus

2.5.7.2.2. simulate/0

Keypath	Type	Value
[flowgraph,icarusdvflow,simulate,0,input]	[(str,str)]	('compile', '0')
[flowgraph,icarusdvflow,simulate,0,task]	str	exec_input
[flowgraph,icarusdvflow,simulate,0,taskmodule]	str	siliconcompiler.tools.execute.exec_input/ExecInputTask
[flowgraph,icarusdvflow,simulate,0,tool]	str	execute

2.5.7.2.3. simulate/1

Keypath	Type	Value
[flowgraph,icarusdvflow,simulate,1,input]	[(str,str)]	('compile', '0')
[flowgraph,icarusdvflow,simulate,1,task]	str	exec_input
[flowgraph,icarusdvflow,simulate,1,taskmodule]	str	siliconcompiler.tools.execute.exec_input/ExecInputTask
[flowgraph,icarusdvflow,simulate,1,tool]	str	execute

2.5.7.2.4. simulate/2

Keypath	Type	Value
[flowgraph,icarusdvflow,simulate,2,input]	[(str,str)]	('compile', '0')
[flowgraph,icarusdvflow,simulate,2,task]	str	exec_input
[flowgraph,icarusdvflow,simulate,2,taskmodule]	str	siliconcompiler.tools.execute.exec_input/ExecInputTask
[flowgraph,icarusdvflow,simulate,2,tool]	str	execute

2.5.8. icaruscocotbdvflow

A DV flow using the Icarus Verilog simulator with cocotb testbenches.

File: dvflow.py

2.5.8.1. Graph

2.5.8.2. Nodes

2.5.8.2.1. compile/0

Keypath	Type	Value
[flowgraph,icaruscocotbdvflow,compile,0,task]	str	compile
[flowgraph,icaruscocotbdvflow,compile,0,taskmodule]	str	siliconcompiler.tools.icarus.compile/CompileTask
[flowgraph,icaruscocotbdvflow,compile,0,tool]	str	icarus

2.5.8.2.2. simulate/0

Keypath	Type	Value
[flowgraph,icaruscocotbdvflow,simulate,0,input]	[(str,str)]	('compile', '0')
[flowgraph,icaruscocotbdvflow,simulate,0,task]	str	exec_cocotb
[flowgraph,icaruscocotbdvflow,simulate,0,taskmodule]	str	siliconcompiler.tools.icarus.cocotb_exec/CocotbExecTask
[flowgraph,icaruscocotbdvflow,simulate,0,tool]	str	icarus

2.5.8.2.3. simulate/1

Keypath	Type	Value
[flowgraph,icaruscocotbdvflow,simulate,1,input]	[(str,str)]	('compile', '0')
[flowgraph,icaruscocotbdvflow,simulate,1,task]	str	exec_cocotb
[flowgraph,icaruscocotbdvflow,simulate,1,taskmodule]	str	siliconcompiler.tools.icarus.cocotb_exec/CocotbExecTask
[flowgraph,icaruscocotbdvflow,simulate,1,tool]	str	icarus

2.5.8.2.4. simulate/2

Keypath	Type	Value
[flowgraph,icaruscocotbdvflow,simulate,2,input]	[(str,str)]	('compile', '0')
[flowgraph,icaruscocotbdvflow,simulate,2,task]	str	exec_cocotb
[flowgraph,icaruscocotbdvflow,simulate,2,taskmodule]	str	siliconcompiler.tools.icarus.cocotb_exec/CocotbExecTask
[flowgraph,icaruscocotbdvflow,simulate,2,tool]	str	icarus

2.5.9. verilatordvflow

A DV flow using the Verilator simulator.

File: dvflow.py

2.5.9.1. Graph

2.5.9.2. Nodes

2.5.9.2.1. compile/0

Keypath	Type	Value
[flowgraph,verilatordvflow,compile,0,task]	str	compile
[flowgraph,verilatordvflow,compile,0,taskmodule]	str	siliconcompiler.tools.verilator.compile/CompileTask
[flowgraph,verilatordvflow,compile,0,tool]	str	verilator

2.5.9.2.2. simulate/0

Keypath	Type	Value
[flowgraph,verilatordvflow,simulate,0,input]	[(str,str)]	('compile', '0')
[flowgraph,verilatordvflow,simulate,0,task]	str	exec_input
[flowgraph,verilatordvflow,simulate,0,taskmodule]	str	siliconcompiler.tools.execute.exec_input/ExecInputTask
[flowgraph,verilatordvflow,simulate,0,tool]	str	execute

2.5.9.2.3. simulate/1

Keypath	Type	Value
[flowgraph,verilatordvflow,simulate,1,input]	[(str,str)]	('compile', '0')
[flowgraph,verilatordvflow,simulate,1,task]	str	exec_input
[flowgraph,verilatordvflow,simulate,1,taskmodule]	str	siliconcompiler.tools.execute.exec_input/ExecInputTask
[flowgraph,verilatordvflow,simulate,1,tool]	str	execute

2.5.9.2.4. simulate/2

Keypath	Type	Value
[flowgraph,verilatordvflow,simulate,2,input]	[(str,str)]	('compile', '0')
[flowgraph,verilatordvflow,simulate,2,task]	str	exec_input
[flowgraph,verilatordvflow,simulate,2,taskmodule]	str	siliconcompiler.tools.execute.exec_input/ExecInputTask
[flowgraph,verilatordvflow,simulate,2,tool]	str	execute

2.5.10. verilatorcocotbdvflow

A DV flow using the Verilator simulator with cocotb testbenches.

File: dvflow.py

2.5.10.1. Graph

2.5.10.2. Nodes

2.5.10.2.1. compile/0

Keypath	Type	Value
[flowgraph,verilatorcocotbdvflow,compile,0,task]	str	cocotb_compile
[flowgraph,verilatorcocotbdvflow,compile,0,taskmodule]	str	siliconcompiler.tools.verilator.cocotb_compile/CocotbCompileTask
[flowgraph,verilatorcocotbdvflow,compile,0,tool]	str	verilator

2.5.10.2.2. simulate/0

Keypath	Type	Value
[flowgraph,verilatorcocotbdvflow,simulate,0,input]	[(str,str)]	('compile', '0')
[flowgraph,verilatorcocotbdvflow,simulate,0,task]	str	exec_cocotb
[flowgraph,verilatorcocotbdvflow,simulate,0,taskmodule]	str	siliconcompiler.tools.verilator.cocotb_exec/CocotbExecTask
[flowgraph,verilatorcocotbdvflow,simulate,0,tool]	str	verilator

2.5.10.2.3. simulate/1

Keypath	Type	Value
[flowgraph,verilatorcocotbdvflow,simulate,1,input]	[(str,str)]	('compile', '0')
[flowgraph,verilatorcocotbdvflow,simulate,1,task]	str	exec_cocotb
[flowgraph,verilatorcocotbdvflow,simulate,1,taskmodule]	str	siliconcompiler.tools.verilator.cocotb_exec/CocotbExecTask
[flowgraph,verilatorcocotbdvflow,simulate,1,tool]	str	verilator

2.5.10.2.4. simulate/2

Keypath	Type	Value
[flowgraph,verilatorcocotbdvflow,simulate,2,input]	[(str,str)]	('compile', '0')
[flowgraph,verilatorcocotbdvflow,simulate,2,task]	str	exec_cocotb
[flowgraph,verilatorcocotbdvflow,simulate,2,taskmodule]	str	siliconcompiler.tools.verilator.cocotb_exec/CocotbExecTask
[flowgraph,verilatorcocotbdvflow,simulate,2,tool]	str	verilator

2.5.11. xycedvflow

A DV flow using the Xyce circuit simulator.

File: dvflow.py

2.5.11.1. Graph

2.5.11.2. Nodes

2.5.11.2.1. simulate/0

Keypath	Type	Value
[flowgraph,xycedvflow,simulate,0,task]	str	simulate
[flowgraph,xycedvflow,simulate,0,taskmodule]	str	siliconcompiler.tools.xyce.simulate/SimulateTask
[flowgraph,xycedvflow,simulate,0,tool]	str	xyce

2.5.11.2.2. simulate/1

Keypath	Type	Value
[flowgraph,xycedvflow,simulate,1,task]	str	simulate
[flowgraph,xycedvflow,simulate,1,taskmodule]	str	siliconcompiler.tools.xyce.simulate/SimulateTask
[flowgraph,xycedvflow,simulate,1,tool]	str	xyce

2.5.11.2.3. simulate/2

Keypath	Type	Value
[flowgraph,xycedvflow,simulate,2,task]	str	simulate
[flowgraph,xycedvflow,simulate,2,taskmodule]	str	siliconcompiler.tools.xyce.simulate/SimulateTask
[flowgraph,xycedvflow,simulate,2,tool]	str	xyce

2.5.12. xdmxycedvflow

A DV flow using the Xyce circuit simulator with XDM conversion.

File: dvflow.py

2.5.12.1. Graph

2.5.12.2. Nodes

2.5.12.2.1. compile/0

Keypath	Type	Value
[flowgraph,xdmxycedvflow,compile,0,task]	str	convert
[flowgraph,xdmxycedvflow,compile,0,taskmodule]	str	siliconcompiler.tools.xdm.convert/ConvertTask
[flowgraph,xdmxycedvflow,compile,0,tool]	str	xdm

2.5.12.2.2. simulate/0

Keypath	Type	Value
[flowgraph,xdmxycedvflow,simulate,0,input]	[(str,str)]	('compile', '0')
[flowgraph,xdmxycedvflow,simulate,0,task]	str	simulate
[flowgraph,xdmxycedvflow,simulate,0,taskmodule]	str	siliconcompiler.tools.xyce.simulate/SimulateTask
[flowgraph,xdmxycedvflow,simulate,0,tool]	str	xyce

2.5.12.2.3. simulate/1

Keypath	Type	Value
[flowgraph,xdmxycedvflow,simulate,1,input]	[(str,str)]	('compile', '0')
[flowgraph,xdmxycedvflow,simulate,1,task]	str	simulate
[flowgraph,xdmxycedvflow,simulate,1,taskmodule]	str	siliconcompiler.tools.xyce.simulate/SimulateTask
[flowgraph,xdmxycedvflow,simulate,1,tool]	str	xyce

2.5.12.2.4. simulate/2

Keypath	Type	Value
[flowgraph,xdmxycedvflow,simulate,2,input]	[(str,str)]	('compile', '0')
[flowgraph,xdmxycedvflow,simulate,2,task]	str	simulate
[flowgraph,xdmxycedvflow,simulate,2,taskmodule]	str	siliconcompiler.tools.xyce.simulate/SimulateTask
[flowgraph,xdmxycedvflow,simulate,2,tool]	str	xyce

2.6. DRC Flows

Flows for running design rule checking (DRC) signoff on a layout.

2.6.1. drcflow-klayout / 0

A design rule check (DRC) flow.

This flow is designed to perform a DRC run on an input GDSII file using KLayout or Magic.

File: drcflow.py

2.6.1.1. Graph

2.6.1.2. Nodes

2.6.1.2.1. drc/0

Keypath	Type	Value
[flowgraph,drcflow-klayout,drc,0,task]	str	drc
[flowgraph,drcflow-klayout,drc,0,taskmodule]	str	siliconcompiler.tools.klayout.drc/DRCTask
[flowgraph,drcflow-klayout,drc,0,tool]	str	klayout

2.6.2. drcflow-magic / 1

A design rule check (DRC) flow.

This flow is designed to perform a DRC run on an input GDSII file using KLayout or Magic.

File: drcflow.py

2.6.2.1. Graph

2.6.2.2. Nodes

2.6.2.2.1. drc/0

Keypath	Type	Value
[flowgraph,drcflow-magic,drc,0,task]	str	drc
[flowgraph,drcflow-magic,drc,0,taskmodule]	str	siliconcompiler.tools.magic.drc/DRCTask
[flowgraph,drcflow-magic,drc,0,tool]	str	magic

2.6.3. klayoutdrcflow

A KLayout-based design rule check (DRC) flow.

This flow is designed to perform a DRC run on an input GDSII file using KLayout.

File: drcflow.py

2.6.3.1. Graph

2.6.3.2. Nodes

2.6.3.2.1. drc/0

Keypath	Type	Value
[flowgraph,klayoutdrcflow,drc,0,task]	str	drc
[flowgraph,klayoutdrcflow,drc,0,taskmodule]	str	siliconcompiler.tools.klayout.drc/DRCTask
[flowgraph,klayoutdrcflow,drc,0,tool]	str	klayout

2.6.4. magicdrcflow

A Magic-based design rule check (DRC) flow.

This flow is designed to perform a DRC run on an input GDSII file using Magic.

File: drcflow.py

2.6.4.1. Graph

2.6.4.2. Nodes

2.6.4.2.1. drc/0

Keypath	Type	Value
[flowgraph,magicdrcflow,drc,0,task]	str	drc
[flowgraph,magicdrcflow,drc,0,taskmodule]	str	siliconcompiler.tools.magic.drc/DRCTask
[flowgraph,magicdrcflow,drc,0,tool]	str	magic

2.7. LVS Flows

Flows for running layout-versus-schematic (LVS) signoff on a layout.

2.7.1. magiclvsflow

A flow for running LVS signoff on a GDS layout.

This flow performs a key physical verification step:

1. Layout Versus Schematic (LVS) checking using Netgen.

The LVS step first requires extracting a SPICE netlist from the layout, which is also handled by Magic.

File: lvsflow.py

2.7.1.1. Graph

2.7.1.2. Nodes

2.7.1.2.1. extspice/0

Keypath	Type	Value
[flowgraph,magiclvsflow,extspice,0,task]	str	extspice
[flowgraph,magiclvsflow,extspice,0,taskmodule]	str	siliconcompiler.tools.magic.extspice/ExtractTask
[flowgraph,magiclvsflow,extspice,0,tool]	str	magic

2.7.1.2.2. lvs/0

Keypath	Type	Value
[flowgraph,magiclvsflow,lvs,0,input]	[(str,str)]	('extspice', '0')
[flowgraph,magiclvsflow,lvs,0,task]	str	lvs
[flowgraph,magiclvsflow,lvs,0,taskmodule]	str	siliconcompiler.tools.netgen.lvs/LVSTask
[flowgraph,magiclvsflow,lvs,0,tool]	str	netgen

2.8. Signoff Flows

Flows that combine the physical verification steps into a single signoff flow.

2.8.1. signoffflow

A flow for running LVS/DRC signoff on a GDS layout.

This flow performs two key physical verification steps in parallel:

1. Design Rule Checking (DRC) using Magic.

2. Layout Versus Schematic (LVS) checking using Netgen.

The LVS step first requires extracting a SPICE netlist from the layout, which is also handled by Magic. A final ‘join’ step ensures that both DRC and LVS tasks must complete successfully for the flow to finish.

File: signoffflow.py

2.8.1.1. Graph

2.8.1.2. Nodes

2.8.1.2.1. drc/0

Keypath	Type	Value
[flowgraph,signoffflow,drc,0,task]	str	drc
[flowgraph,signoffflow,drc,0,taskmodule]	str	siliconcompiler.tools.magic.drc/DRCTask
[flowgraph,signoffflow,drc,0,tool]	str	magic

2.8.1.2.2. extspice/0

Keypath	Type	Value
[flowgraph,signoffflow,extspice,0,task]	str	extspice
[flowgraph,signoffflow,extspice,0,taskmodule]	str	siliconcompiler.tools.magic.extspice/ExtractTask
[flowgraph,signoffflow,extspice,0,tool]	str	magic

2.8.1.2.3. lvs/0

Keypath	Type	Value
[flowgraph,signoffflow,lvs,0,input]	[(str,str)]	('extspice', '0')
[flowgraph,signoffflow,lvs,0,task]	str	lvs
[flowgraph,signoffflow,lvs,0,taskmodule]	str	siliconcompiler.tools.netgen.lvs/LVSTask
[flowgraph,signoffflow,lvs,0,tool]	str	netgen

2.8.1.2.4. signoff/0

Keypath	Type	Value
[flowgraph,signoffflow,signoff,0,input]	[(str,str)]	('drc', '0') ('lvs', '0')
[flowgraph,signoffflow,signoff,0,task]	str	join
[flowgraph,signoffflow,signoff,0,taskmodule]	str	siliconcompiler.tools.builtin.join/JoinTask
[flowgraph,signoffflow,signoff,0,tool]	str	builtin

2.9. FPGA Flows

Complete FPGA compilation flows. Each variant targets a different FPGA toolchain.

2.9.1. fpgaflow-nextpnr-verilog / 0

An open-source FPGA flow using Yosys and NextPNR.

This flow is tailored for FPGAs supported by the NextPNR tool, which handles placement, routing, and bitstream generation in a single step.

The flow consists of the following steps:

• elaborate: Elaborate the RTL design from sources.

• syn_fpga: Synthesize RTL into a device-specific netlist using Yosys.

• apr: Perform automatic place and route (APR) and generate the

  bitstream using NextPNR.

File: fpgaflow.py

2.9.1.1. Graph

2.9.1.2. Nodes

2.9.1.2.1. elaborate/0

Keypath	Type	Value
[flowgraph,fpgaflow-nextpnr-verilog,elaborate,0,task]	str	elaborate
[flowgraph,fpgaflow-nextpnr-verilog,elaborate,0,taskmodule]	str	siliconcompiler.tools.slang.elaborate/Elaborate
[flowgraph,fpgaflow-nextpnr-verilog,elaborate,0,tool]	str	slang

2.9.1.2.2. syn_fpga/0

Keypath	Type	Value
[flowgraph,fpgaflow-nextpnr-verilog,syn_fpga,0,input]	[(str,str)]	('elaborate', '0')
[flowgraph,fpgaflow-nextpnr-verilog,syn_fpga,0,task]	str	syn_fpga
[flowgraph,fpgaflow-nextpnr-verilog,syn_fpga,0,taskmodule]	str	siliconcompiler.tools.yosys.syn_fpga/FPGASynthesis
[flowgraph,fpgaflow-nextpnr-verilog,syn_fpga,0,tool]	str	yosys

2.9.1.2.3. apr/0

Keypath	Type	Value
[flowgraph,fpgaflow-nextpnr-verilog,apr,0,input]	[(str,str)]	('syn_fpga', '0')
[flowgraph,fpgaflow-nextpnr-verilog,apr,0,task]	str	apr
[flowgraph,fpgaflow-nextpnr-verilog,apr,0,taskmodule]	str	siliconcompiler.tools.nextpnr.apr/APRTask
[flowgraph,fpgaflow-nextpnr-verilog,apr,0,tool]	str	nextpnr

2.9.2. fpgaflow-nextpnr-systemverilog-sv2v / 1

An open-source FPGA flow using Yosys and NextPNR.

This flow is tailored for FPGAs supported by the NextPNR tool, which handles placement, routing, and bitstream generation in a single step.

The flow consists of the following steps:

• elaborate: Elaborate the RTL design from sources.

• syn_fpga: Synthesize RTL into a device-specific netlist using Yosys.

• apr: Perform automatic place and route (APR) and generate the

  bitstream using NextPNR.

File: fpgaflow.py

2.9.2.1. Graph

2.9.2.2. Nodes

2.9.2.2.1. elaborate/0

Keypath	Type	Value
[flowgraph,fpgaflow-nextpnr-systemverilog-sv2v,elaborate,0,task]	str	elaborate
[flowgraph,fpgaflow-nextpnr-systemverilog-sv2v,elaborate,0,taskmodule]	str	siliconcompiler.tools.slang.elaborate/Elaborate
[flowgraph,fpgaflow-nextpnr-systemverilog-sv2v,elaborate,0,tool]	str	slang

2.9.2.2.2. convert/0

Keypath	Type	Value
[flowgraph,fpgaflow-nextpnr-systemverilog-sv2v,convert,0,input]	[(str,str)]	('elaborate', '0')
[flowgraph,fpgaflow-nextpnr-systemverilog-sv2v,convert,0,task]	str	convert
[flowgraph,fpgaflow-nextpnr-systemverilog-sv2v,convert,0,taskmodule]	str	siliconcompiler.tools.sv2v.convert/ConvertTask
[flowgraph,fpgaflow-nextpnr-systemverilog-sv2v,convert,0,tool]	str	sv2v

2.9.2.2.3. syn_fpga/0

Keypath	Type	Value
[flowgraph,fpgaflow-nextpnr-systemverilog-sv2v,syn_fpga,0,input]	[(str,str)]	('convert', '0')
[flowgraph,fpgaflow-nextpnr-systemverilog-sv2v,syn_fpga,0,task]	str	syn_fpga
[flowgraph,fpgaflow-nextpnr-systemverilog-sv2v,syn_fpga,0,taskmodule]	str	siliconcompiler.tools.yosys.syn_fpga/FPGASynthesis
[flowgraph,fpgaflow-nextpnr-systemverilog-sv2v,syn_fpga,0,tool]	str	yosys

2.9.2.2.4. apr/0

Keypath	Type	Value
[flowgraph,fpgaflow-nextpnr-systemverilog-sv2v,apr,0,input]	[(str,str)]	('syn_fpga', '0')
[flowgraph,fpgaflow-nextpnr-systemverilog-sv2v,apr,0,task]	str	apr
[flowgraph,fpgaflow-nextpnr-systemverilog-sv2v,apr,0,taskmodule]	str	siliconcompiler.tools.nextpnr.apr/APRTask
[flowgraph,fpgaflow-nextpnr-systemverilog-sv2v,apr,0,tool]	str	nextpnr

2.9.3. fpgaflow-nextpnr-chisel / 2

An open-source FPGA flow using Yosys and NextPNR.

This flow is tailored for FPGAs supported by the NextPNR tool, which handles placement, routing, and bitstream generation in a single step.

The flow consists of the following steps:

• elaborate: Elaborate the RTL design from sources.

• syn_fpga: Synthesize RTL into a device-specific netlist using Yosys.

• apr: Perform automatic place and route (APR) and generate the

  bitstream using NextPNR.

File: fpgaflow.py

2.9.3.1. Graph

2.9.3.2. Nodes

2.9.3.2.1. convert/0

Keypath	Type	Value
[flowgraph,fpgaflow-nextpnr-chisel,convert,0,task]	str	convert
[flowgraph,fpgaflow-nextpnr-chisel,convert,0,taskmodule]	str	siliconcompiler.tools.chisel.convert/ConvertTask
[flowgraph,fpgaflow-nextpnr-chisel,convert,0,tool]	str	chisel

2.9.3.2.2. syn_fpga/0

Keypath	Type	Value
[flowgraph,fpgaflow-nextpnr-chisel,syn_fpga,0,input]	[(str,str)]	('convert', '0')
[flowgraph,fpgaflow-nextpnr-chisel,syn_fpga,0,task]	str	syn_fpga
[flowgraph,fpgaflow-nextpnr-chisel,syn_fpga,0,taskmodule]	str	siliconcompiler.tools.yosys.syn_fpga/FPGASynthesis
[flowgraph,fpgaflow-nextpnr-chisel,syn_fpga,0,tool]	str	yosys

2.9.3.2.3. apr/0

Keypath	Type	Value
[flowgraph,fpgaflow-nextpnr-chisel,apr,0,input]	[(str,str)]	('syn_fpga', '0')
[flowgraph,fpgaflow-nextpnr-chisel,apr,0,task]	str	apr
[flowgraph,fpgaflow-nextpnr-chisel,apr,0,taskmodule]	str	siliconcompiler.tools.nextpnr.apr/APRTask
[flowgraph,fpgaflow-nextpnr-chisel,apr,0,tool]	str	nextpnr

2.9.4. fpgaflow-nextpnr-vhdl / 3

An open-source FPGA flow using Yosys and NextPNR.

This flow is tailored for FPGAs supported by the NextPNR tool, which handles placement, routing, and bitstream generation in a single step.

The flow consists of the following steps:

• elaborate: Elaborate the RTL design from sources.

• syn_fpga: Synthesize RTL into a device-specific netlist using Yosys.

• apr: Perform automatic place and route (APR) and generate the

  bitstream using NextPNR.

File: fpgaflow.py

2.9.4.1. Graph

2.9.4.2. Nodes

2.9.4.2.1. convert/0

Keypath	Type	Value
[flowgraph,fpgaflow-nextpnr-vhdl,convert,0,task]	str	convert
[flowgraph,fpgaflow-nextpnr-vhdl,convert,0,taskmodule]	str	siliconcompiler.tools.ghdl.convert/ConvertTask
[flowgraph,fpgaflow-nextpnr-vhdl,convert,0,tool]	str	ghdl

2.9.4.2.2. syn_fpga/0

Keypath	Type	Value
[flowgraph,fpgaflow-nextpnr-vhdl,syn_fpga,0,input]	[(str,str)]	('convert', '0')
[flowgraph,fpgaflow-nextpnr-vhdl,syn_fpga,0,task]	str	syn_fpga
[flowgraph,fpgaflow-nextpnr-vhdl,syn_fpga,0,taskmodule]	str	siliconcompiler.tools.yosys.syn_fpga/FPGASynthesis
[flowgraph,fpgaflow-nextpnr-vhdl,syn_fpga,0,tool]	str	yosys

2.9.4.2.3. apr/0

Keypath	Type	Value
[flowgraph,fpgaflow-nextpnr-vhdl,apr,0,input]	[(str,str)]	('syn_fpga', '0')
[flowgraph,fpgaflow-nextpnr-vhdl,apr,0,task]	str	apr
[flowgraph,fpgaflow-nextpnr-vhdl,apr,0,taskmodule]	str	siliconcompiler.tools.nextpnr.apr/APRTask
[flowgraph,fpgaflow-nextpnr-vhdl,apr,0,tool]	str	nextpnr

2.9.5. fpgaflow-nextpnr-hls / 4

An open-source FPGA flow using Yosys and NextPNR.

This flow is tailored for FPGAs supported by the NextPNR tool, which handles placement, routing, and bitstream generation in a single step.

The flow consists of the following steps:

• elaborate: Elaborate the RTL design from sources.

• syn_fpga: Synthesize RTL into a device-specific netlist using Yosys.

• apr: Perform automatic place and route (APR) and generate the

  bitstream using NextPNR.

File: fpgaflow.py

2.9.5.1. Graph

2.9.5.2. Nodes

2.9.5.2.1. convert/0

Keypath	Type	Value
[flowgraph,fpgaflow-nextpnr-hls,convert,0,task]	str	convert
[flowgraph,fpgaflow-nextpnr-hls,convert,0,taskmodule]	str	siliconcompiler.tools.bambu.convert/ConvertTask
[flowgraph,fpgaflow-nextpnr-hls,convert,0,tool]	str	bambu

2.9.5.2.2. syn_fpga/0

Keypath	Type	Value
[flowgraph,fpgaflow-nextpnr-hls,syn_fpga,0,input]	[(str,str)]	('convert', '0')
[flowgraph,fpgaflow-nextpnr-hls,syn_fpga,0,task]	str	syn_fpga
[flowgraph,fpgaflow-nextpnr-hls,syn_fpga,0,taskmodule]	str	siliconcompiler.tools.yosys.syn_fpga/FPGASynthesis
[flowgraph,fpgaflow-nextpnr-hls,syn_fpga,0,tool]	str	yosys

2.9.5.2.3. apr/0

Keypath	Type	Value
[flowgraph,fpgaflow-nextpnr-hls,apr,0,input]	[(str,str)]	('syn_fpga', '0')
[flowgraph,fpgaflow-nextpnr-hls,apr,0,task]	str	apr
[flowgraph,fpgaflow-nextpnr-hls,apr,0,taskmodule]	str	siliconcompiler.tools.nextpnr.apr/APRTask
[flowgraph,fpgaflow-nextpnr-hls,apr,0,tool]	str	nextpnr

2.9.6. fpgaflow-nextpnr-bluespec / 5

An open-source FPGA flow using Yosys and NextPNR.

This flow is tailored for FPGAs supported by the NextPNR tool, which handles placement, routing, and bitstream generation in a single step.

The flow consists of the following steps:

• elaborate: Elaborate the RTL design from sources.

• syn_fpga: Synthesize RTL into a device-specific netlist using Yosys.

• apr: Perform automatic place and route (APR) and generate the

  bitstream using NextPNR.

File: fpgaflow.py

2.9.6.1. Graph

2.9.6.2. Nodes

2.9.6.2.1. convert/0

Keypath	Type	Value
[flowgraph,fpgaflow-nextpnr-bluespec,convert,0,task]	str	convert
[flowgraph,fpgaflow-nextpnr-bluespec,convert,0,taskmodule]	str	siliconcompiler.tools.bluespec.convert/ConvertTask
[flowgraph,fpgaflow-nextpnr-bluespec,convert,0,tool]	str	bluespec

2.9.6.2.2. syn_fpga/0

Keypath	Type	Value
[flowgraph,fpgaflow-nextpnr-bluespec,syn_fpga,0,input]	[(str,str)]	('convert', '0')
[flowgraph,fpgaflow-nextpnr-bluespec,syn_fpga,0,task]	str	syn_fpga
[flowgraph,fpgaflow-nextpnr-bluespec,syn_fpga,0,taskmodule]	str	siliconcompiler.tools.yosys.syn_fpga/FPGASynthesis
[flowgraph,fpgaflow-nextpnr-bluespec,syn_fpga,0,tool]	str	yosys

2.9.6.2.3. apr/0

Keypath	Type	Value
[flowgraph,fpgaflow-nextpnr-bluespec,apr,0,input]	[(str,str)]	('syn_fpga', '0')
[flowgraph,fpgaflow-nextpnr-bluespec,apr,0,task]	str	apr
[flowgraph,fpgaflow-nextpnr-bluespec,apr,0,taskmodule]	str	siliconcompiler.tools.nextpnr.apr/APRTask
[flowgraph,fpgaflow-nextpnr-bluespec,apr,0,tool]	str	nextpnr

2.9.7. fpgaflow-vpr-verilog / 0

An open-source FPGA flow using Yosys, VPR, and GenFasm.

This flow is designed for academic and research FPGAs, utilizing VPR (Versatile Place and Route) for placement and routing.

The flow consists of the following steps:

• elaborate: Elaborate the RTL design from sources.

• synthesis: Synthesize the elaborated design into a netlist using Yosys.

• place: Place the netlist components onto the FPGA architecture using VPR.

• route: Route the connections between placed components using VPR.

• bitstream: Generate the final bitstream using GenFasm.

File: fpgaflow.py

2.9.7.1. Graph

2.9.7.2. Nodes

2.9.7.2.1. elaborate/0

Keypath	Type	Value
[flowgraph,fpgaflow-vpr-verilog,elaborate,0,task]	str	elaborate
[flowgraph,fpgaflow-vpr-verilog,elaborate,0,taskmodule]	str	siliconcompiler.tools.slang.elaborate/Elaborate
[flowgraph,fpgaflow-vpr-verilog,elaborate,0,tool]	str	slang

2.9.7.2.2. synthesis/0

Keypath	Type	Value
[flowgraph,fpgaflow-vpr-verilog,synthesis,0,input]	[(str,str)]	('elaborate', '0')
[flowgraph,fpgaflow-vpr-verilog,synthesis,0,task]	str	syn_fpga
[flowgraph,fpgaflow-vpr-verilog,synthesis,0,taskmodule]	str	siliconcompiler.tools.yosys.syn_fpga/FPGASynthesis
[flowgraph,fpgaflow-vpr-verilog,synthesis,0,tool]	str	yosys

2.9.7.2.3. place/0

Keypath	Type	Value
[flowgraph,fpgaflow-vpr-verilog,place,0,input]	[(str,str)]	('synthesis', '0')
[flowgraph,fpgaflow-vpr-verilog,place,0,task]	str	place
[flowgraph,fpgaflow-vpr-verilog,place,0,taskmodule]	str	siliconcompiler.tools.vpr.place/PlaceTask
[flowgraph,fpgaflow-vpr-verilog,place,0,tool]	str	vpr

2.9.7.2.4. route/0

Keypath	Type	Value
[flowgraph,fpgaflow-vpr-verilog,route,0,input]	[(str,str)]	('place', '0')
[flowgraph,fpgaflow-vpr-verilog,route,0,task]	str	route
[flowgraph,fpgaflow-vpr-verilog,route,0,taskmodule]	str	siliconcompiler.tools.vpr.route/RouteTask
[flowgraph,fpgaflow-vpr-verilog,route,0,tool]	str	vpr

2.9.7.2.5. bitstream/0

Keypath	Type	Value
[flowgraph,fpgaflow-vpr-verilog,bitstream,0,input]	[(str,str)]	('route', '0')
[flowgraph,fpgaflow-vpr-verilog,bitstream,0,task]	str	bitstream
[flowgraph,fpgaflow-vpr-verilog,bitstream,0,taskmodule]	str	siliconcompiler.tools.genfasm.bitstream/BitstreamTask
[flowgraph,fpgaflow-vpr-verilog,bitstream,0,tool]	str	genfasm

2.9.8. fpgaflow-vpr-systemverilog-sv2v / 1

An open-source FPGA flow using Yosys, VPR, and GenFasm.

This flow is designed for academic and research FPGAs, utilizing VPR (Versatile Place and Route) for placement and routing.

The flow consists of the following steps:

• elaborate: Elaborate the RTL design from sources.

• synthesis: Synthesize the elaborated design into a netlist using Yosys.

• place: Place the netlist components onto the FPGA architecture using VPR.

• route: Route the connections between placed components using VPR.

• bitstream: Generate the final bitstream using GenFasm.

File: fpgaflow.py

2.9.8.1. Graph

2.9.8.2. Nodes

2.9.8.2.1. elaborate/0

Keypath	Type	Value
[flowgraph,fpgaflow-vpr-systemverilog-sv2v,elaborate,0,task]	str	elaborate
[flowgraph,fpgaflow-vpr-systemverilog-sv2v,elaborate,0,taskmodule]	str	siliconcompiler.tools.slang.elaborate/Elaborate
[flowgraph,fpgaflow-vpr-systemverilog-sv2v,elaborate,0,tool]	str	slang

2.9.8.2.2. convert/0

Keypath	Type	Value
[flowgraph,fpgaflow-vpr-systemverilog-sv2v,convert,0,input]	[(str,str)]	('elaborate', '0')
[flowgraph,fpgaflow-vpr-systemverilog-sv2v,convert,0,task]	str	convert
[flowgraph,fpgaflow-vpr-systemverilog-sv2v,convert,0,taskmodule]	str	siliconcompiler.tools.sv2v.convert/ConvertTask
[flowgraph,fpgaflow-vpr-systemverilog-sv2v,convert,0,tool]	str	sv2v

2.9.8.2.3. synthesis/0

Keypath	Type	Value
[flowgraph,fpgaflow-vpr-systemverilog-sv2v,synthesis,0,input]	[(str,str)]	('convert', '0')
[flowgraph,fpgaflow-vpr-systemverilog-sv2v,synthesis,0,task]	str	syn_fpga
[flowgraph,fpgaflow-vpr-systemverilog-sv2v,synthesis,0,taskmodule]	str	siliconcompiler.tools.yosys.syn_fpga/FPGASynthesis
[flowgraph,fpgaflow-vpr-systemverilog-sv2v,synthesis,0,tool]	str	yosys

2.9.8.2.4. place/0

Keypath	Type	Value
[flowgraph,fpgaflow-vpr-systemverilog-sv2v,place,0,input]	[(str,str)]	('synthesis', '0')
[flowgraph,fpgaflow-vpr-systemverilog-sv2v,place,0,task]	str	place
[flowgraph,fpgaflow-vpr-systemverilog-sv2v,place,0,taskmodule]	str	siliconcompiler.tools.vpr.place/PlaceTask
[flowgraph,fpgaflow-vpr-systemverilog-sv2v,place,0,tool]	str	vpr

2.9.8.2.5. route/0

Keypath	Type	Value
[flowgraph,fpgaflow-vpr-systemverilog-sv2v,route,0,input]	[(str,str)]	('place', '0')
[flowgraph,fpgaflow-vpr-systemverilog-sv2v,route,0,task]	str	route
[flowgraph,fpgaflow-vpr-systemverilog-sv2v,route,0,taskmodule]	str	siliconcompiler.tools.vpr.route/RouteTask
[flowgraph,fpgaflow-vpr-systemverilog-sv2v,route,0,tool]	str	vpr

2.9.8.2.6. bitstream/0

Keypath	Type	Value
[flowgraph,fpgaflow-vpr-systemverilog-sv2v,bitstream,0,input]	[(str,str)]	('route', '0')
[flowgraph,fpgaflow-vpr-systemverilog-sv2v,bitstream,0,task]	str	bitstream
[flowgraph,fpgaflow-vpr-systemverilog-sv2v,bitstream,0,taskmodule]	str	siliconcompiler.tools.genfasm.bitstream/BitstreamTask
[flowgraph,fpgaflow-vpr-systemverilog-sv2v,bitstream,0,tool]	str	genfasm

2.9.9. fpgaflow-vpr-chisel / 2

An open-source FPGA flow using Yosys, VPR, and GenFasm.

This flow is designed for academic and research FPGAs, utilizing VPR (Versatile Place and Route) for placement and routing.

The flow consists of the following steps:

• elaborate: Elaborate the RTL design from sources.

• synthesis: Synthesize the elaborated design into a netlist using Yosys.

• place: Place the netlist components onto the FPGA architecture using VPR.

• route: Route the connections between placed components using VPR.

• bitstream: Generate the final bitstream using GenFasm.

File: fpgaflow.py

2.9.9.1. Graph

2.9.9.2. Nodes

2.9.9.2.1. convert/0

Keypath	Type	Value
[flowgraph,fpgaflow-vpr-chisel,convert,0,task]	str	convert
[flowgraph,fpgaflow-vpr-chisel,convert,0,taskmodule]	str	siliconcompiler.tools.chisel.convert/ConvertTask
[flowgraph,fpgaflow-vpr-chisel,convert,0,tool]	str	chisel

2.9.9.2.2. synthesis/0

Keypath	Type	Value
[flowgraph,fpgaflow-vpr-chisel,synthesis,0,input]	[(str,str)]	('convert', '0')
[flowgraph,fpgaflow-vpr-chisel,synthesis,0,task]	str	syn_fpga
[flowgraph,fpgaflow-vpr-chisel,synthesis,0,taskmodule]	str	siliconcompiler.tools.yosys.syn_fpga/FPGASynthesis
[flowgraph,fpgaflow-vpr-chisel,synthesis,0,tool]	str	yosys

2.9.9.2.3. place/0

Keypath	Type	Value
[flowgraph,fpgaflow-vpr-chisel,place,0,input]	[(str,str)]	('synthesis', '0')
[flowgraph,fpgaflow-vpr-chisel,place,0,task]	str	place
[flowgraph,fpgaflow-vpr-chisel,place,0,taskmodule]	str	siliconcompiler.tools.vpr.place/PlaceTask
[flowgraph,fpgaflow-vpr-chisel,place,0,tool]	str	vpr

2.9.9.2.4. route/0

Keypath	Type	Value
[flowgraph,fpgaflow-vpr-chisel,route,0,input]	[(str,str)]	('place', '0')
[flowgraph,fpgaflow-vpr-chisel,route,0,task]	str	route
[flowgraph,fpgaflow-vpr-chisel,route,0,taskmodule]	str	siliconcompiler.tools.vpr.route/RouteTask
[flowgraph,fpgaflow-vpr-chisel,route,0,tool]	str	vpr

2.9.9.2.5. bitstream/0

Keypath	Type	Value
[flowgraph,fpgaflow-vpr-chisel,bitstream,0,input]	[(str,str)]	('route', '0')
[flowgraph,fpgaflow-vpr-chisel,bitstream,0,task]	str	bitstream
[flowgraph,fpgaflow-vpr-chisel,bitstream,0,taskmodule]	str	siliconcompiler.tools.genfasm.bitstream/BitstreamTask
[flowgraph,fpgaflow-vpr-chisel,bitstream,0,tool]	str	genfasm

2.9.10. fpgaflow-vpr-vhdl / 3

An open-source FPGA flow using Yosys, VPR, and GenFasm.

This flow is designed for academic and research FPGAs, utilizing VPR (Versatile Place and Route) for placement and routing.

The flow consists of the following steps:

• elaborate: Elaborate the RTL design from sources.

• synthesis: Synthesize the elaborated design into a netlist using Yosys.

• place: Place the netlist components onto the FPGA architecture using VPR.

• route: Route the connections between placed components using VPR.

• bitstream: Generate the final bitstream using GenFasm.

File: fpgaflow.py

2.9.10.1. Graph

2.9.10.2. Nodes

2.9.10.2.1. convert/0

Keypath	Type	Value
[flowgraph,fpgaflow-vpr-vhdl,convert,0,task]	str	convert
[flowgraph,fpgaflow-vpr-vhdl,convert,0,taskmodule]	str	siliconcompiler.tools.ghdl.convert/ConvertTask
[flowgraph,fpgaflow-vpr-vhdl,convert,0,tool]	str	ghdl

2.9.10.2.2. synthesis/0

Keypath	Type	Value
[flowgraph,fpgaflow-vpr-vhdl,synthesis,0,input]	[(str,str)]	('convert', '0')
[flowgraph,fpgaflow-vpr-vhdl,synthesis,0,task]	str	syn_fpga
[flowgraph,fpgaflow-vpr-vhdl,synthesis,0,taskmodule]	str	siliconcompiler.tools.yosys.syn_fpga/FPGASynthesis
[flowgraph,fpgaflow-vpr-vhdl,synthesis,0,tool]	str	yosys

2.9.10.2.3. place/0

Keypath	Type	Value
[flowgraph,fpgaflow-vpr-vhdl,place,0,input]	[(str,str)]	('synthesis', '0')
[flowgraph,fpgaflow-vpr-vhdl,place,0,task]	str	place
[flowgraph,fpgaflow-vpr-vhdl,place,0,taskmodule]	str	siliconcompiler.tools.vpr.place/PlaceTask
[flowgraph,fpgaflow-vpr-vhdl,place,0,tool]	str	vpr

2.9.10.2.4. route/0

Keypath	Type	Value
[flowgraph,fpgaflow-vpr-vhdl,route,0,input]	[(str,str)]	('place', '0')
[flowgraph,fpgaflow-vpr-vhdl,route,0,task]	str	route
[flowgraph,fpgaflow-vpr-vhdl,route,0,taskmodule]	str	siliconcompiler.tools.vpr.route/RouteTask
[flowgraph,fpgaflow-vpr-vhdl,route,0,tool]	str	vpr

2.9.10.2.5. bitstream/0

Keypath	Type	Value
[flowgraph,fpgaflow-vpr-vhdl,bitstream,0,input]	[(str,str)]	('route', '0')
[flowgraph,fpgaflow-vpr-vhdl,bitstream,0,task]	str	bitstream
[flowgraph,fpgaflow-vpr-vhdl,bitstream,0,taskmodule]	str	siliconcompiler.tools.genfasm.bitstream/BitstreamTask
[flowgraph,fpgaflow-vpr-vhdl,bitstream,0,tool]	str	genfasm

2.9.11. fpgaflow-vpr-hls / 4

An open-source FPGA flow using Yosys, VPR, and GenFasm.

This flow is designed for academic and research FPGAs, utilizing VPR (Versatile Place and Route) for placement and routing.

The flow consists of the following steps:

• elaborate: Elaborate the RTL design from sources.

• synthesis: Synthesize the elaborated design into a netlist using Yosys.

• place: Place the netlist components onto the FPGA architecture using VPR.

• route: Route the connections between placed components using VPR.

• bitstream: Generate the final bitstream using GenFasm.

File: fpgaflow.py

2.9.11.1. Graph

2.9.11.2. Nodes

2.9.11.2.1. convert/0

Keypath	Type	Value
[flowgraph,fpgaflow-vpr-hls,convert,0,task]	str	convert
[flowgraph,fpgaflow-vpr-hls,convert,0,taskmodule]	str	siliconcompiler.tools.bambu.convert/ConvertTask
[flowgraph,fpgaflow-vpr-hls,convert,0,tool]	str	bambu

2.9.11.2.2. synthesis/0

Keypath	Type	Value
[flowgraph,fpgaflow-vpr-hls,synthesis,0,input]	[(str,str)]	('convert', '0')
[flowgraph,fpgaflow-vpr-hls,synthesis,0,task]	str	syn_fpga
[flowgraph,fpgaflow-vpr-hls,synthesis,0,taskmodule]	str	siliconcompiler.tools.yosys.syn_fpga/FPGASynthesis
[flowgraph,fpgaflow-vpr-hls,synthesis,0,tool]	str	yosys

2.9.11.2.3. place/0

Keypath	Type	Value
[flowgraph,fpgaflow-vpr-hls,place,0,input]	[(str,str)]	('synthesis', '0')
[flowgraph,fpgaflow-vpr-hls,place,0,task]	str	place
[flowgraph,fpgaflow-vpr-hls,place,0,taskmodule]	str	siliconcompiler.tools.vpr.place/PlaceTask
[flowgraph,fpgaflow-vpr-hls,place,0,tool]	str	vpr

2.9.11.2.4. route/0

Keypath	Type	Value
[flowgraph,fpgaflow-vpr-hls,route,0,input]	[(str,str)]	('place', '0')
[flowgraph,fpgaflow-vpr-hls,route,0,task]	str	route
[flowgraph,fpgaflow-vpr-hls,route,0,taskmodule]	str	siliconcompiler.tools.vpr.route/RouteTask
[flowgraph,fpgaflow-vpr-hls,route,0,tool]	str	vpr

2.9.11.2.5. bitstream/0

Keypath	Type	Value
[flowgraph,fpgaflow-vpr-hls,bitstream,0,input]	[(str,str)]	('route', '0')
[flowgraph,fpgaflow-vpr-hls,bitstream,0,task]	str	bitstream
[flowgraph,fpgaflow-vpr-hls,bitstream,0,taskmodule]	str	siliconcompiler.tools.genfasm.bitstream/BitstreamTask
[flowgraph,fpgaflow-vpr-hls,bitstream,0,tool]	str	genfasm

2.9.12. fpgaflow-vpr-bluespec / 5

An open-source FPGA flow using Yosys, VPR, and GenFasm.

This flow is designed for academic and research FPGAs, utilizing VPR (Versatile Place and Route) for placement and routing.

The flow consists of the following steps:

• elaborate: Elaborate the RTL design from sources.

• synthesis: Synthesize the elaborated design into a netlist using Yosys.

• place: Place the netlist components onto the FPGA architecture using VPR.

• route: Route the connections between placed components using VPR.

• bitstream: Generate the final bitstream using GenFasm.

File: fpgaflow.py

2.9.12.1. Graph

2.9.12.2. Nodes

2.9.12.2.1. convert/0

Keypath	Type	Value
[flowgraph,fpgaflow-vpr-bluespec,convert,0,task]	str	convert
[flowgraph,fpgaflow-vpr-bluespec,convert,0,taskmodule]	str	siliconcompiler.tools.bluespec.convert/ConvertTask
[flowgraph,fpgaflow-vpr-bluespec,convert,0,tool]	str	bluespec

2.9.12.2.2. synthesis/0

Keypath	Type	Value
[flowgraph,fpgaflow-vpr-bluespec,synthesis,0,input]	[(str,str)]	('convert', '0')
[flowgraph,fpgaflow-vpr-bluespec,synthesis,0,task]	str	syn_fpga
[flowgraph,fpgaflow-vpr-bluespec,synthesis,0,taskmodule]	str	siliconcompiler.tools.yosys.syn_fpga/FPGASynthesis
[flowgraph,fpgaflow-vpr-bluespec,synthesis,0,tool]	str	yosys

2.9.12.2.3. place/0

Keypath	Type	Value
[flowgraph,fpgaflow-vpr-bluespec,place,0,input]	[(str,str)]	('synthesis', '0')
[flowgraph,fpgaflow-vpr-bluespec,place,0,task]	str	place
[flowgraph,fpgaflow-vpr-bluespec,place,0,taskmodule]	str	siliconcompiler.tools.vpr.place/PlaceTask
[flowgraph,fpgaflow-vpr-bluespec,place,0,tool]	str	vpr

2.9.12.2.4. route/0

Keypath	Type	Value
[flowgraph,fpgaflow-vpr-bluespec,route,0,input]	[(str,str)]	('place', '0')
[flowgraph,fpgaflow-vpr-bluespec,route,0,task]	str	route
[flowgraph,fpgaflow-vpr-bluespec,route,0,taskmodule]	str	siliconcompiler.tools.vpr.route/RouteTask
[flowgraph,fpgaflow-vpr-bluespec,route,0,tool]	str	vpr

2.9.12.2.5. bitstream/0

Keypath	Type	Value
[flowgraph,fpgaflow-vpr-bluespec,bitstream,0,input]	[(str,str)]	('route', '0')
[flowgraph,fpgaflow-vpr-bluespec,bitstream,0,task]	str	bitstream
[flowgraph,fpgaflow-vpr-bluespec,bitstream,0,taskmodule]	str	siliconcompiler.tools.genfasm.bitstream/BitstreamTask
[flowgraph,fpgaflow-vpr-bluespec,bitstream,0,tool]	str	genfasm

2.9.13. fpgaflow-vpr-open-sta-verilog / 0

An open-source FPGA flow using Yosys, VPR, GenFasm, and OpenSTA.

This flow is designed for academic and research FPGAs, utilizing VPR (Versatile Place and Route) for placement and routing and OpenSTA for post-implementation timing analysis.

The flow consists of the following steps:

• elaborate: Elaborate the RTL design from sources.

• synthesis: Synthesize the elaborated design into a netlist using Yosys.

• place: Place the netlist components onto the FPGA architecture using VPR.

• route: Route the connections between placed components using VPR.

• bitstream: Generate the final bitstream using GenFasm.

• timing: Perform post-implementation static timing analysis of the design.

File: fpgaflow.py

2.9.13.1. Graph

2.9.13.2. Nodes

2.9.13.2.1. elaborate/0

Keypath	Type	Value
[flowgraph,fpgaflow-vpr-open-sta-verilog,elaborate,0,task]	str	elaborate
[flowgraph,fpgaflow-vpr-open-sta-verilog,elaborate,0,taskmodule]	str	siliconcompiler.tools.slang.elaborate/Elaborate
[flowgraph,fpgaflow-vpr-open-sta-verilog,elaborate,0,tool]	str	slang

2.9.13.2.2. synthesis/0

Keypath	Type	Value
[flowgraph,fpgaflow-vpr-open-sta-verilog,synthesis,0,input]	[(str,str)]	('elaborate', '0')
[flowgraph,fpgaflow-vpr-open-sta-verilog,synthesis,0,task]	str	syn_fpga
[flowgraph,fpgaflow-vpr-open-sta-verilog,synthesis,0,taskmodule]	str	siliconcompiler.tools.yosys.syn_fpga/FPGASynthesis
[flowgraph,fpgaflow-vpr-open-sta-verilog,synthesis,0,tool]	str	yosys

2.9.13.2.3. place/0

Keypath	Type	Value
[flowgraph,fpgaflow-vpr-open-sta-verilog,place,0,input]	[(str,str)]	('synthesis', '0')
[flowgraph,fpgaflow-vpr-open-sta-verilog,place,0,task]	str	place
[flowgraph,fpgaflow-vpr-open-sta-verilog,place,0,taskmodule]	str	siliconcompiler.tools.vpr.place/PlaceTask
[flowgraph,fpgaflow-vpr-open-sta-verilog,place,0,tool]	str	vpr

2.9.13.2.4. route/0

Keypath	Type	Value
[flowgraph,fpgaflow-vpr-open-sta-verilog,route,0,input]	[(str,str)]	('place', '0')
[flowgraph,fpgaflow-vpr-open-sta-verilog,route,0,task]	str	route
[flowgraph,fpgaflow-vpr-open-sta-verilog,route,0,taskmodule]	str	siliconcompiler.tools.vpr.route/RouteTask
[flowgraph,fpgaflow-vpr-open-sta-verilog,route,0,tool]	str	vpr

2.9.13.2.5. bitstream/0

Keypath	Type	Value
[flowgraph,fpgaflow-vpr-open-sta-verilog,bitstream,0,input]	[(str,str)]	('route', '0')
[flowgraph,fpgaflow-vpr-open-sta-verilog,bitstream,0,task]	str	bitstream
[flowgraph,fpgaflow-vpr-open-sta-verilog,bitstream,0,taskmodule]	str	siliconcompiler.tools.genfasm.bitstream/BitstreamTask
[flowgraph,fpgaflow-vpr-open-sta-verilog,bitstream,0,tool]	str	genfasm

2.9.13.2.6. timing/0

Keypath	Type	Value
[flowgraph,fpgaflow-vpr-open-sta-verilog,timing,0,input]	[(str,str)]	('route', '0')
[flowgraph,fpgaflow-vpr-open-sta-verilog,timing,0,task]	str	fpga_timing
[flowgraph,fpgaflow-vpr-open-sta-verilog,timing,0,taskmodule]	str	siliconcompiler.tools.opensta.timing/FPGATimingTask
[flowgraph,fpgaflow-vpr-open-sta-verilog,timing,0,tool]	str	opensta

2.9.14. fpgaflow-vpr-open-sta-systemverilog-sv2v / 1

An open-source FPGA flow using Yosys, VPR, GenFasm, and OpenSTA.

This flow is designed for academic and research FPGAs, utilizing VPR (Versatile Place and Route) for placement and routing and OpenSTA for post-implementation timing analysis.

The flow consists of the following steps:

• elaborate: Elaborate the RTL design from sources.

• synthesis: Synthesize the elaborated design into a netlist using Yosys.

• place: Place the netlist components onto the FPGA architecture using VPR.

• route: Route the connections between placed components using VPR.

• bitstream: Generate the final bitstream using GenFasm.

• timing: Perform post-implementation static timing analysis of the design.

File: fpgaflow.py

2.9.14.1. Graph

2.9.14.2. Nodes

2.9.14.2.1. elaborate/0

Keypath	Type	Value
[flowgraph,fpgaflow-vpr-open-sta-systemverilog-sv2v,elaborate,0,task]	str	elaborate
[flowgraph,fpgaflow-vpr-open-sta-systemverilog-sv2v,elaborate,0,taskmodule]	str	siliconcompiler.tools.slang.elaborate/Elaborate
[flowgraph,fpgaflow-vpr-open-sta-systemverilog-sv2v,elaborate,0,tool]	str	slang

2.9.14.2.2. convert/0

Keypath	Type	Value
[flowgraph,fpgaflow-vpr-open-sta-systemverilog-sv2v,convert,0,input]	[(str,str)]	('elaborate', '0')
[flowgraph,fpgaflow-vpr-open-sta-systemverilog-sv2v,convert,0,task]	str	convert
[flowgraph,fpgaflow-vpr-open-sta-systemverilog-sv2v,convert,0,taskmodule]	str	siliconcompiler.tools.sv2v.convert/ConvertTask
[flowgraph,fpgaflow-vpr-open-sta-systemverilog-sv2v,convert,0,tool]	str	sv2v

2.9.14.2.3. synthesis/0

Keypath	Type	Value
[flowgraph,fpgaflow-vpr-open-sta-systemverilog-sv2v,synthesis,0,input]	[(str,str)]	('convert', '0')
[flowgraph,fpgaflow-vpr-open-sta-systemverilog-sv2v,synthesis,0,task]	str	syn_fpga
[flowgraph,fpgaflow-vpr-open-sta-systemverilog-sv2v,synthesis,0,taskmodule]	str	siliconcompiler.tools.yosys.syn_fpga/FPGASynthesis
[flowgraph,fpgaflow-vpr-open-sta-systemverilog-sv2v,synthesis,0,tool]	str	yosys

2.9.14.2.4. place/0

Keypath	Type	Value
[flowgraph,fpgaflow-vpr-open-sta-systemverilog-sv2v,place,0,input]	[(str,str)]	('synthesis', '0')
[flowgraph,fpgaflow-vpr-open-sta-systemverilog-sv2v,place,0,task]	str	place
[flowgraph,fpgaflow-vpr-open-sta-systemverilog-sv2v,place,0,taskmodule]	str	siliconcompiler.tools.vpr.place/PlaceTask
[flowgraph,fpgaflow-vpr-open-sta-systemverilog-sv2v,place,0,tool]	str	vpr

2.9.14.2.5. route/0

Keypath	Type	Value
[flowgraph,fpgaflow-vpr-open-sta-systemverilog-sv2v,route,0,input]	[(str,str)]	('place', '0')
[flowgraph,fpgaflow-vpr-open-sta-systemverilog-sv2v,route,0,task]	str	route
[flowgraph,fpgaflow-vpr-open-sta-systemverilog-sv2v,route,0,taskmodule]	str	siliconcompiler.tools.vpr.route/RouteTask
[flowgraph,fpgaflow-vpr-open-sta-systemverilog-sv2v,route,0,tool]	str	vpr

2.9.14.2.6. bitstream/0

Keypath	Type	Value
[flowgraph,fpgaflow-vpr-open-sta-systemverilog-sv2v,bitstream,0,input]	[(str,str)]	('route', '0')
[flowgraph,fpgaflow-vpr-open-sta-systemverilog-sv2v,bitstream,0,task]	str	bitstream
[flowgraph,fpgaflow-vpr-open-sta-systemverilog-sv2v,bitstream,0,taskmodule]	str	siliconcompiler.tools.genfasm.bitstream/BitstreamTask
[flowgraph,fpgaflow-vpr-open-sta-systemverilog-sv2v,bitstream,0,tool]	str	genfasm

2.9.14.2.7. timing/0

Keypath	Type	Value
[flowgraph,fpgaflow-vpr-open-sta-systemverilog-sv2v,timing,0,input]	[(str,str)]	('route', '0')
[flowgraph,fpgaflow-vpr-open-sta-systemverilog-sv2v,timing,0,task]	str	fpga_timing
[flowgraph,fpgaflow-vpr-open-sta-systemverilog-sv2v,timing,0,taskmodule]	str	siliconcompiler.tools.opensta.timing/FPGATimingTask
[flowgraph,fpgaflow-vpr-open-sta-systemverilog-sv2v,timing,0,tool]	str	opensta

2.9.15. fpgaflow-vpr-open-sta-chisel / 2

An open-source FPGA flow using Yosys, VPR, GenFasm, and OpenSTA.

This flow is designed for academic and research FPGAs, utilizing VPR (Versatile Place and Route) for placement and routing and OpenSTA for post-implementation timing analysis.

The flow consists of the following steps:

• elaborate: Elaborate the RTL design from sources.

• synthesis: Synthesize the elaborated design into a netlist using Yosys.

• place: Place the netlist components onto the FPGA architecture using VPR.

• route: Route the connections between placed components using VPR.

• bitstream: Generate the final bitstream using GenFasm.

• timing: Perform post-implementation static timing analysis of the design.

File: fpgaflow.py

2.9.15.1. Graph

2.9.15.2. Nodes

2.9.15.2.1. convert/0

Keypath	Type	Value
[flowgraph,fpgaflow-vpr-open-sta-chisel,convert,0,task]	str	convert
[flowgraph,fpgaflow-vpr-open-sta-chisel,convert,0,taskmodule]	str	siliconcompiler.tools.chisel.convert/ConvertTask
[flowgraph,fpgaflow-vpr-open-sta-chisel,convert,0,tool]	str	chisel

2.9.15.2.2. synthesis/0

Keypath	Type	Value
[flowgraph,fpgaflow-vpr-open-sta-chisel,synthesis,0,input]	[(str,str)]	('convert', '0')
[flowgraph,fpgaflow-vpr-open-sta-chisel,synthesis,0,task]	str	syn_fpga
[flowgraph,fpgaflow-vpr-open-sta-chisel,synthesis,0,taskmodule]	str	siliconcompiler.tools.yosys.syn_fpga/FPGASynthesis
[flowgraph,fpgaflow-vpr-open-sta-chisel,synthesis,0,tool]	str	yosys

2.9.15.2.3. place/0

Keypath	Type	Value
[flowgraph,fpgaflow-vpr-open-sta-chisel,place,0,input]	[(str,str)]	('synthesis', '0')
[flowgraph,fpgaflow-vpr-open-sta-chisel,place,0,task]	str	place
[flowgraph,fpgaflow-vpr-open-sta-chisel,place,0,taskmodule]	str	siliconcompiler.tools.vpr.place/PlaceTask
[flowgraph,fpgaflow-vpr-open-sta-chisel,place,0,tool]	str	vpr

2.9.15.2.4. route/0

Keypath	Type	Value
[flowgraph,fpgaflow-vpr-open-sta-chisel,route,0,input]	[(str,str)]	('place', '0')
[flowgraph,fpgaflow-vpr-open-sta-chisel,route,0,task]	str	route
[flowgraph,fpgaflow-vpr-open-sta-chisel,route,0,taskmodule]	str	siliconcompiler.tools.vpr.route/RouteTask
[flowgraph,fpgaflow-vpr-open-sta-chisel,route,0,tool]	str	vpr

2.9.15.2.5. bitstream/0

Keypath	Type	Value
[flowgraph,fpgaflow-vpr-open-sta-chisel,bitstream,0,input]	[(str,str)]	('route', '0')
[flowgraph,fpgaflow-vpr-open-sta-chisel,bitstream,0,task]	str	bitstream
[flowgraph,fpgaflow-vpr-open-sta-chisel,bitstream,0,taskmodule]	str	siliconcompiler.tools.genfasm.bitstream/BitstreamTask
[flowgraph,fpgaflow-vpr-open-sta-chisel,bitstream,0,tool]	str	genfasm

2.9.15.2.6. timing/0

Keypath	Type	Value
[flowgraph,fpgaflow-vpr-open-sta-chisel,timing,0,input]	[(str,str)]	('route', '0')
[flowgraph,fpgaflow-vpr-open-sta-chisel,timing,0,task]	str	fpga_timing
[flowgraph,fpgaflow-vpr-open-sta-chisel,timing,0,taskmodule]	str	siliconcompiler.tools.opensta.timing/FPGATimingTask
[flowgraph,fpgaflow-vpr-open-sta-chisel,timing,0,tool]	str	opensta

2.9.16. fpgaflow-vpr-open-sta-vhdl / 3

An open-source FPGA flow using Yosys, VPR, GenFasm, and OpenSTA.

This flow is designed for academic and research FPGAs, utilizing VPR (Versatile Place and Route) for placement and routing and OpenSTA for post-implementation timing analysis.

The flow consists of the following steps:

• elaborate: Elaborate the RTL design from sources.

• synthesis: Synthesize the elaborated design into a netlist using Yosys.

• place: Place the netlist components onto the FPGA architecture using VPR.

• route: Route the connections between placed components using VPR.

• bitstream: Generate the final bitstream using GenFasm.

• timing: Perform post-implementation static timing analysis of the design.

File: fpgaflow.py

2.9.16.1. Graph

2.9.16.2. Nodes

2.9.16.2.1. convert/0

Keypath	Type	Value
[flowgraph,fpgaflow-vpr-open-sta-vhdl,convert,0,task]	str	convert
[flowgraph,fpgaflow-vpr-open-sta-vhdl,convert,0,taskmodule]	str	siliconcompiler.tools.ghdl.convert/ConvertTask
[flowgraph,fpgaflow-vpr-open-sta-vhdl,convert,0,tool]	str	ghdl

2.9.16.2.2. synthesis/0

Keypath	Type	Value
[flowgraph,fpgaflow-vpr-open-sta-vhdl,synthesis,0,input]	[(str,str)]	('convert', '0')
[flowgraph,fpgaflow-vpr-open-sta-vhdl,synthesis,0,task]	str	syn_fpga
[flowgraph,fpgaflow-vpr-open-sta-vhdl,synthesis,0,taskmodule]	str	siliconcompiler.tools.yosys.syn_fpga/FPGASynthesis
[flowgraph,fpgaflow-vpr-open-sta-vhdl,synthesis,0,tool]	str	yosys

2.9.16.2.3. place/0

Keypath	Type	Value
[flowgraph,fpgaflow-vpr-open-sta-vhdl,place,0,input]	[(str,str)]	('synthesis', '0')
[flowgraph,fpgaflow-vpr-open-sta-vhdl,place,0,task]	str	place
[flowgraph,fpgaflow-vpr-open-sta-vhdl,place,0,taskmodule]	str	siliconcompiler.tools.vpr.place/PlaceTask
[flowgraph,fpgaflow-vpr-open-sta-vhdl,place,0,tool]	str	vpr

2.9.16.2.4. route/0

Keypath	Type	Value
[flowgraph,fpgaflow-vpr-open-sta-vhdl,route,0,input]	[(str,str)]	('place', '0')
[flowgraph,fpgaflow-vpr-open-sta-vhdl,route,0,task]	str	route
[flowgraph,fpgaflow-vpr-open-sta-vhdl,route,0,taskmodule]	str	siliconcompiler.tools.vpr.route/RouteTask
[flowgraph,fpgaflow-vpr-open-sta-vhdl,route,0,tool]	str	vpr

2.9.16.2.5. bitstream/0

Keypath	Type	Value
[flowgraph,fpgaflow-vpr-open-sta-vhdl,bitstream,0,input]	[(str,str)]	('route', '0')
[flowgraph,fpgaflow-vpr-open-sta-vhdl,bitstream,0,task]	str	bitstream
[flowgraph,fpgaflow-vpr-open-sta-vhdl,bitstream,0,taskmodule]	str	siliconcompiler.tools.genfasm.bitstream/BitstreamTask
[flowgraph,fpgaflow-vpr-open-sta-vhdl,bitstream,0,tool]	str	genfasm

2.9.16.2.6. timing/0

Keypath	Type	Value
[flowgraph,fpgaflow-vpr-open-sta-vhdl,timing,0,input]	[(str,str)]	('route', '0')
[flowgraph,fpgaflow-vpr-open-sta-vhdl,timing,0,task]	str	fpga_timing
[flowgraph,fpgaflow-vpr-open-sta-vhdl,timing,0,taskmodule]	str	siliconcompiler.tools.opensta.timing/FPGATimingTask
[flowgraph,fpgaflow-vpr-open-sta-vhdl,timing,0,tool]	str	opensta

2.9.17. fpgaflow-vpr-open-sta-hls / 4

An open-source FPGA flow using Yosys, VPR, GenFasm, and OpenSTA.

This flow is designed for academic and research FPGAs, utilizing VPR (Versatile Place and Route) for placement and routing and OpenSTA for post-implementation timing analysis.

The flow consists of the following steps:

• elaborate: Elaborate the RTL design from sources.

• synthesis: Synthesize the elaborated design into a netlist using Yosys.

• place: Place the netlist components onto the FPGA architecture using VPR.

• route: Route the connections between placed components using VPR.

• bitstream: Generate the final bitstream using GenFasm.

• timing: Perform post-implementation static timing analysis of the design.

File: fpgaflow.py

2.9.17.1. Graph

2.9.17.2. Nodes

2.9.17.2.1. convert/0

Keypath	Type	Value
[flowgraph,fpgaflow-vpr-open-sta-hls,convert,0,task]	str	convert
[flowgraph,fpgaflow-vpr-open-sta-hls,convert,0,taskmodule]	str	siliconcompiler.tools.bambu.convert/ConvertTask
[flowgraph,fpgaflow-vpr-open-sta-hls,convert,0,tool]	str	bambu

2.9.17.2.2. synthesis/0

Keypath	Type	Value
[flowgraph,fpgaflow-vpr-open-sta-hls,synthesis,0,input]	[(str,str)]	('convert', '0')
[flowgraph,fpgaflow-vpr-open-sta-hls,synthesis,0,task]	str	syn_fpga
[flowgraph,fpgaflow-vpr-open-sta-hls,synthesis,0,taskmodule]	str	siliconcompiler.tools.yosys.syn_fpga/FPGASynthesis
[flowgraph,fpgaflow-vpr-open-sta-hls,synthesis,0,tool]	str	yosys

2.9.17.2.3. place/0

Keypath	Type	Value
[flowgraph,fpgaflow-vpr-open-sta-hls,place,0,input]	[(str,str)]	('synthesis', '0')
[flowgraph,fpgaflow-vpr-open-sta-hls,place,0,task]	str	place
[flowgraph,fpgaflow-vpr-open-sta-hls,place,0,taskmodule]	str	siliconcompiler.tools.vpr.place/PlaceTask
[flowgraph,fpgaflow-vpr-open-sta-hls,place,0,tool]	str	vpr

2.9.17.2.4. route/0

Keypath	Type	Value
[flowgraph,fpgaflow-vpr-open-sta-hls,route,0,input]	[(str,str)]	('place', '0')
[flowgraph,fpgaflow-vpr-open-sta-hls,route,0,task]	str	route
[flowgraph,fpgaflow-vpr-open-sta-hls,route,0,taskmodule]	str	siliconcompiler.tools.vpr.route/RouteTask
[flowgraph,fpgaflow-vpr-open-sta-hls,route,0,tool]	str	vpr

2.9.17.2.5. bitstream/0

Keypath	Type	Value
[flowgraph,fpgaflow-vpr-open-sta-hls,bitstream,0,input]	[(str,str)]	('route', '0')
[flowgraph,fpgaflow-vpr-open-sta-hls,bitstream,0,task]	str	bitstream
[flowgraph,fpgaflow-vpr-open-sta-hls,bitstream,0,taskmodule]	str	siliconcompiler.tools.genfasm.bitstream/BitstreamTask
[flowgraph,fpgaflow-vpr-open-sta-hls,bitstream,0,tool]	str	genfasm

2.9.17.2.6. timing/0

Keypath	Type	Value
[flowgraph,fpgaflow-vpr-open-sta-hls,timing,0,input]	[(str,str)]	('route', '0')
[flowgraph,fpgaflow-vpr-open-sta-hls,timing,0,task]	str	fpga_timing
[flowgraph,fpgaflow-vpr-open-sta-hls,timing,0,taskmodule]	str	siliconcompiler.tools.opensta.timing/FPGATimingTask
[flowgraph,fpgaflow-vpr-open-sta-hls,timing,0,tool]	str	opensta

2.9.18. fpgaflow-vpr-open-sta-bluespec / 5

An open-source FPGA flow using Yosys, VPR, GenFasm, and OpenSTA.

This flow is designed for academic and research FPGAs, utilizing VPR (Versatile Place and Route) for placement and routing and OpenSTA for post-implementation timing analysis.

The flow consists of the following steps:

• elaborate: Elaborate the RTL design from sources.

• synthesis: Synthesize the elaborated design into a netlist using Yosys.

• place: Place the netlist components onto the FPGA architecture using VPR.

• route: Route the connections between placed components using VPR.

• bitstream: Generate the final bitstream using GenFasm.

• timing: Perform post-implementation static timing analysis of the design.

File: fpgaflow.py

2.9.18.1. Graph

2.9.18.2. Nodes

2.9.18.2.1. convert/0

Keypath	Type	Value
[flowgraph,fpgaflow-vpr-open-sta-bluespec,convert,0,task]	str	convert
[flowgraph,fpgaflow-vpr-open-sta-bluespec,convert,0,taskmodule]	str	siliconcompiler.tools.bluespec.convert/ConvertTask
[flowgraph,fpgaflow-vpr-open-sta-bluespec,convert,0,tool]	str	bluespec

2.9.18.2.2. synthesis/0

Keypath	Type	Value
[flowgraph,fpgaflow-vpr-open-sta-bluespec,synthesis,0,input]	[(str,str)]	('convert', '0')
[flowgraph,fpgaflow-vpr-open-sta-bluespec,synthesis,0,task]	str	syn_fpga
[flowgraph,fpgaflow-vpr-open-sta-bluespec,synthesis,0,taskmodule]	str	siliconcompiler.tools.yosys.syn_fpga/FPGASynthesis
[flowgraph,fpgaflow-vpr-open-sta-bluespec,synthesis,0,tool]	str	yosys

2.9.18.2.3. place/0

Keypath	Type	Value
[flowgraph,fpgaflow-vpr-open-sta-bluespec,place,0,input]	[(str,str)]	('synthesis', '0')
[flowgraph,fpgaflow-vpr-open-sta-bluespec,place,0,task]	str	place
[flowgraph,fpgaflow-vpr-open-sta-bluespec,place,0,taskmodule]	str	siliconcompiler.tools.vpr.place/PlaceTask
[flowgraph,fpgaflow-vpr-open-sta-bluespec,place,0,tool]	str	vpr

2.9.18.2.4. route/0

Keypath	Type	Value
[flowgraph,fpgaflow-vpr-open-sta-bluespec,route,0,input]	[(str,str)]	('place', '0')
[flowgraph,fpgaflow-vpr-open-sta-bluespec,route,0,task]	str	route
[flowgraph,fpgaflow-vpr-open-sta-bluespec,route,0,taskmodule]	str	siliconcompiler.tools.vpr.route/RouteTask
[flowgraph,fpgaflow-vpr-open-sta-bluespec,route,0,tool]	str	vpr

2.9.18.2.5. bitstream/0

Keypath	Type	Value
[flowgraph,fpgaflow-vpr-open-sta-bluespec,bitstream,0,input]	[(str,str)]	('route', '0')
[flowgraph,fpgaflow-vpr-open-sta-bluespec,bitstream,0,task]	str	bitstream
[flowgraph,fpgaflow-vpr-open-sta-bluespec,bitstream,0,taskmodule]	str	siliconcompiler.tools.genfasm.bitstream/BitstreamTask
[flowgraph,fpgaflow-vpr-open-sta-bluespec,bitstream,0,tool]	str	genfasm

2.9.18.2.6. timing/0

Keypath	Type	Value
[flowgraph,fpgaflow-vpr-open-sta-bluespec,timing,0,input]	[(str,str)]	('route', '0')
[flowgraph,fpgaflow-vpr-open-sta-bluespec,timing,0,task]	str	fpga_timing
[flowgraph,fpgaflow-vpr-open-sta-bluespec,timing,0,taskmodule]	str	siliconcompiler.tools.opensta.timing/FPGATimingTask
[flowgraph,fpgaflow-vpr-open-sta-bluespec,timing,0,tool]	str	opensta

2.9.19. fpgaflow-xilinx-verilog / 0

An FPGA compilation flow targeting Xilinx devices using Vivado.

This flow uses the commercial Vivado toolchain for synthesis, placement, routing, and bitstream generation.

The flow consists of the following steps:

• elaborate: Elaborate the RTL design from sources.

• syn_fpga: Synthesize RTL into a device-specific netlist.

• place: Place the synthesized netlist onto the FPGA fabric.

• route: Route the connections between placed components.

• bitstream: Generate the final bitstream for device programming.

File: fpgaflow.py

2.9.19.1. Graph

2.9.19.2. Nodes

2.9.19.2.1. elaborate/0

Keypath	Type	Value
[flowgraph,fpgaflow-xilinx-verilog,elaborate,0,task]	str	elaborate
[flowgraph,fpgaflow-xilinx-verilog,elaborate,0,taskmodule]	str	siliconcompiler.tools.slang.elaborate/Elaborate
[flowgraph,fpgaflow-xilinx-verilog,elaborate,0,tool]	str	slang

2.9.19.2.2. syn_fpga/0

Keypath	Type	Value
[flowgraph,fpgaflow-xilinx-verilog,syn_fpga,0,input]	[(str,str)]	('elaborate', '0')
[flowgraph,fpgaflow-xilinx-verilog,syn_fpga,0,task]	str	syn_fpga
[flowgraph,fpgaflow-xilinx-verilog,syn_fpga,0,taskmodule]	str	siliconcompiler.tools.vivado.syn_fpga/SynthesisTask
[flowgraph,fpgaflow-xilinx-verilog,syn_fpga,0,tool]	str	vivado

2.9.19.2.3. place/0

Keypath	Type	Value
[flowgraph,fpgaflow-xilinx-verilog,place,0,input]	[(str,str)]	('syn_fpga', '0')
[flowgraph,fpgaflow-xilinx-verilog,place,0,task]	str	place
[flowgraph,fpgaflow-xilinx-verilog,place,0,taskmodule]	str	siliconcompiler.tools.vivado.place/PlaceTask
[flowgraph,fpgaflow-xilinx-verilog,place,0,tool]	str	vivado

2.9.19.2.4. route/0

Keypath	Type	Value
[flowgraph,fpgaflow-xilinx-verilog,route,0,input]	[(str,str)]	('place', '0')
[flowgraph,fpgaflow-xilinx-verilog,route,0,task]	str	route
[flowgraph,fpgaflow-xilinx-verilog,route,0,taskmodule]	str	siliconcompiler.tools.vivado.route/RouteTask
[flowgraph,fpgaflow-xilinx-verilog,route,0,tool]	str	vivado

2.9.19.2.5. bitstream/0

Keypath	Type	Value
[flowgraph,fpgaflow-xilinx-verilog,bitstream,0,input]	[(str,str)]	('route', '0')
[flowgraph,fpgaflow-xilinx-verilog,bitstream,0,task]	str	bitstream
[flowgraph,fpgaflow-xilinx-verilog,bitstream,0,taskmodule]	str	siliconcompiler.tools.vivado.bitstream/BitstreamTask
[flowgraph,fpgaflow-xilinx-verilog,bitstream,0,tool]	str	vivado

2.9.20. fpgaflow-xilinx-systemverilog-sv2v / 1

An FPGA compilation flow targeting Xilinx devices using Vivado.

This flow uses the commercial Vivado toolchain for synthesis, placement, routing, and bitstream generation.

The flow consists of the following steps:

• elaborate: Elaborate the RTL design from sources.

• syn_fpga: Synthesize RTL into a device-specific netlist.

• place: Place the synthesized netlist onto the FPGA fabric.

• route: Route the connections between placed components.

• bitstream: Generate the final bitstream for device programming.

File: fpgaflow.py

2.9.20.1. Graph

2.9.20.2. Nodes

2.9.20.2.1. elaborate/0

Keypath	Type	Value
[flowgraph,fpgaflow-xilinx-systemverilog-sv2v,elaborate,0,task]	str	elaborate
[flowgraph,fpgaflow-xilinx-systemverilog-sv2v,elaborate,0,taskmodule]	str	siliconcompiler.tools.slang.elaborate/Elaborate
[flowgraph,fpgaflow-xilinx-systemverilog-sv2v,elaborate,0,tool]	str	slang

2.9.20.2.2. convert/0

Keypath	Type	Value
[flowgraph,fpgaflow-xilinx-systemverilog-sv2v,convert,0,input]	[(str,str)]	('elaborate', '0')
[flowgraph,fpgaflow-xilinx-systemverilog-sv2v,convert,0,task]	str	convert
[flowgraph,fpgaflow-xilinx-systemverilog-sv2v,convert,0,taskmodule]	str	siliconcompiler.tools.sv2v.convert/ConvertTask
[flowgraph,fpgaflow-xilinx-systemverilog-sv2v,convert,0,tool]	str	sv2v

2.9.20.2.3. syn_fpga/0

Keypath	Type	Value
[flowgraph,fpgaflow-xilinx-systemverilog-sv2v,syn_fpga,0,input]	[(str,str)]	('convert', '0')
[flowgraph,fpgaflow-xilinx-systemverilog-sv2v,syn_fpga,0,task]	str	syn_fpga
[flowgraph,fpgaflow-xilinx-systemverilog-sv2v,syn_fpga,0,taskmodule]	str	siliconcompiler.tools.vivado.syn_fpga/SynthesisTask
[flowgraph,fpgaflow-xilinx-systemverilog-sv2v,syn_fpga,0,tool]	str	vivado

2.9.20.2.4. place/0

Keypath	Type	Value
[flowgraph,fpgaflow-xilinx-systemverilog-sv2v,place,0,input]	[(str,str)]	('syn_fpga', '0')
[flowgraph,fpgaflow-xilinx-systemverilog-sv2v,place,0,task]	str	place
[flowgraph,fpgaflow-xilinx-systemverilog-sv2v,place,0,taskmodule]	str	siliconcompiler.tools.vivado.place/PlaceTask
[flowgraph,fpgaflow-xilinx-systemverilog-sv2v,place,0,tool]	str	vivado

2.9.20.2.5. route/0

Keypath	Type	Value
[flowgraph,fpgaflow-xilinx-systemverilog-sv2v,route,0,input]	[(str,str)]	('place', '0')
[flowgraph,fpgaflow-xilinx-systemverilog-sv2v,route,0,task]	str	route
[flowgraph,fpgaflow-xilinx-systemverilog-sv2v,route,0,taskmodule]	str	siliconcompiler.tools.vivado.route/RouteTask
[flowgraph,fpgaflow-xilinx-systemverilog-sv2v,route,0,tool]	str	vivado

2.9.20.2.6. bitstream/0

Keypath	Type	Value
[flowgraph,fpgaflow-xilinx-systemverilog-sv2v,bitstream,0,input]	[(str,str)]	('route', '0')
[flowgraph,fpgaflow-xilinx-systemverilog-sv2v,bitstream,0,task]	str	bitstream
[flowgraph,fpgaflow-xilinx-systemverilog-sv2v,bitstream,0,taskmodule]	str	siliconcompiler.tools.vivado.bitstream/BitstreamTask
[flowgraph,fpgaflow-xilinx-systemverilog-sv2v,bitstream,0,tool]	str	vivado

2.9.21. fpgaflow-xilinx-chisel / 2

An FPGA compilation flow targeting Xilinx devices using Vivado.

This flow uses the commercial Vivado toolchain for synthesis, placement, routing, and bitstream generation.

The flow consists of the following steps:

• elaborate: Elaborate the RTL design from sources.

• syn_fpga: Synthesize RTL into a device-specific netlist.

• place: Place the synthesized netlist onto the FPGA fabric.

• route: Route the connections between placed components.

• bitstream: Generate the final bitstream for device programming.

File: fpgaflow.py

2.9.21.1. Graph

2.9.21.2. Nodes

2.9.21.2.1. convert/0

Keypath	Type	Value
[flowgraph,fpgaflow-xilinx-chisel,convert,0,task]	str	convert
[flowgraph,fpgaflow-xilinx-chisel,convert,0,taskmodule]	str	siliconcompiler.tools.chisel.convert/ConvertTask
[flowgraph,fpgaflow-xilinx-chisel,convert,0,tool]	str	chisel

2.9.21.2.2. syn_fpga/0

Keypath	Type	Value
[flowgraph,fpgaflow-xilinx-chisel,syn_fpga,0,input]	[(str,str)]	('convert', '0')
[flowgraph,fpgaflow-xilinx-chisel,syn_fpga,0,task]	str	syn_fpga
[flowgraph,fpgaflow-xilinx-chisel,syn_fpga,0,taskmodule]	str	siliconcompiler.tools.vivado.syn_fpga/SynthesisTask
[flowgraph,fpgaflow-xilinx-chisel,syn_fpga,0,tool]	str	vivado

2.9.21.2.3. place/0

Keypath	Type	Value
[flowgraph,fpgaflow-xilinx-chisel,place,0,input]	[(str,str)]	('syn_fpga', '0')
[flowgraph,fpgaflow-xilinx-chisel,place,0,task]	str	place
[flowgraph,fpgaflow-xilinx-chisel,place,0,taskmodule]	str	siliconcompiler.tools.vivado.place/PlaceTask
[flowgraph,fpgaflow-xilinx-chisel,place,0,tool]	str	vivado

2.9.21.2.4. route/0

Keypath	Type	Value
[flowgraph,fpgaflow-xilinx-chisel,route,0,input]	[(str,str)]	('place', '0')
[flowgraph,fpgaflow-xilinx-chisel,route,0,task]	str	route
[flowgraph,fpgaflow-xilinx-chisel,route,0,taskmodule]	str	siliconcompiler.tools.vivado.route/RouteTask
[flowgraph,fpgaflow-xilinx-chisel,route,0,tool]	str	vivado

2.9.21.2.5. bitstream/0

Keypath	Type	Value
[flowgraph,fpgaflow-xilinx-chisel,bitstream,0,input]	[(str,str)]	('route', '0')
[flowgraph,fpgaflow-xilinx-chisel,bitstream,0,task]	str	bitstream
[flowgraph,fpgaflow-xilinx-chisel,bitstream,0,taskmodule]	str	siliconcompiler.tools.vivado.bitstream/BitstreamTask
[flowgraph,fpgaflow-xilinx-chisel,bitstream,0,tool]	str	vivado

2.9.22. fpgaflow-xilinx-vhdl / 3

An FPGA compilation flow targeting Xilinx devices using Vivado.

This flow uses the commercial Vivado toolchain for synthesis, placement, routing, and bitstream generation.

The flow consists of the following steps:

• elaborate: Elaborate the RTL design from sources.

• syn_fpga: Synthesize RTL into a device-specific netlist.

• place: Place the synthesized netlist onto the FPGA fabric.

• route: Route the connections between placed components.

• bitstream: Generate the final bitstream for device programming.

File: fpgaflow.py

2.9.22.1. Graph

2.9.22.2. Nodes

2.9.22.2.1. convert/0

Keypath	Type	Value
[flowgraph,fpgaflow-xilinx-vhdl,convert,0,task]	str	convert
[flowgraph,fpgaflow-xilinx-vhdl,convert,0,taskmodule]	str	siliconcompiler.tools.ghdl.convert/ConvertTask
[flowgraph,fpgaflow-xilinx-vhdl,convert,0,tool]	str	ghdl

2.9.22.2.2. syn_fpga/0

Keypath	Type	Value
[flowgraph,fpgaflow-xilinx-vhdl,syn_fpga,0,input]	[(str,str)]	('convert', '0')
[flowgraph,fpgaflow-xilinx-vhdl,syn_fpga,0,task]	str	syn_fpga
[flowgraph,fpgaflow-xilinx-vhdl,syn_fpga,0,taskmodule]	str	siliconcompiler.tools.vivado.syn_fpga/SynthesisTask
[flowgraph,fpgaflow-xilinx-vhdl,syn_fpga,0,tool]	str	vivado

2.9.22.2.3. place/0

Keypath	Type	Value
[flowgraph,fpgaflow-xilinx-vhdl,place,0,input]	[(str,str)]	('syn_fpga', '0')
[flowgraph,fpgaflow-xilinx-vhdl,place,0,task]	str	place
[flowgraph,fpgaflow-xilinx-vhdl,place,0,taskmodule]	str	siliconcompiler.tools.vivado.place/PlaceTask
[flowgraph,fpgaflow-xilinx-vhdl,place,0,tool]	str	vivado

2.9.22.2.4. route/0

Keypath	Type	Value
[flowgraph,fpgaflow-xilinx-vhdl,route,0,input]	[(str,str)]	('place', '0')
[flowgraph,fpgaflow-xilinx-vhdl,route,0,task]	str	route
[flowgraph,fpgaflow-xilinx-vhdl,route,0,taskmodule]	str	siliconcompiler.tools.vivado.route/RouteTask
[flowgraph,fpgaflow-xilinx-vhdl,route,0,tool]	str	vivado

2.9.22.2.5. bitstream/0

Keypath	Type	Value
[flowgraph,fpgaflow-xilinx-vhdl,bitstream,0,input]	[(str,str)]	('route', '0')
[flowgraph,fpgaflow-xilinx-vhdl,bitstream,0,task]	str	bitstream
[flowgraph,fpgaflow-xilinx-vhdl,bitstream,0,taskmodule]	str	siliconcompiler.tools.vivado.bitstream/BitstreamTask
[flowgraph,fpgaflow-xilinx-vhdl,bitstream,0,tool]	str	vivado

2.9.23. fpgaflow-xilinx-hls / 4

An FPGA compilation flow targeting Xilinx devices using Vivado.

This flow uses the commercial Vivado toolchain for synthesis, placement, routing, and bitstream generation.

The flow consists of the following steps:

• elaborate: Elaborate the RTL design from sources.

• syn_fpga: Synthesize RTL into a device-specific netlist.

• place: Place the synthesized netlist onto the FPGA fabric.

• route: Route the connections between placed components.

• bitstream: Generate the final bitstream for device programming.

File: fpgaflow.py

2.9.23.1. Graph

2.9.23.2. Nodes

2.9.23.2.1. convert/0

Keypath	Type	Value
[flowgraph,fpgaflow-xilinx-hls,convert,0,task]	str	convert
[flowgraph,fpgaflow-xilinx-hls,convert,0,taskmodule]	str	siliconcompiler.tools.bambu.convert/ConvertTask
[flowgraph,fpgaflow-xilinx-hls,convert,0,tool]	str	bambu

2.9.23.2.2. syn_fpga/0

Keypath	Type	Value
[flowgraph,fpgaflow-xilinx-hls,syn_fpga,0,input]	[(str,str)]	('convert', '0')
[flowgraph,fpgaflow-xilinx-hls,syn_fpga,0,task]	str	syn_fpga
[flowgraph,fpgaflow-xilinx-hls,syn_fpga,0,taskmodule]	str	siliconcompiler.tools.vivado.syn_fpga/SynthesisTask
[flowgraph,fpgaflow-xilinx-hls,syn_fpga,0,tool]	str	vivado

2.9.23.2.3. place/0

Keypath	Type	Value
[flowgraph,fpgaflow-xilinx-hls,place,0,input]	[(str,str)]	('syn_fpga', '0')
[flowgraph,fpgaflow-xilinx-hls,place,0,task]	str	place
[flowgraph,fpgaflow-xilinx-hls,place,0,taskmodule]	str	siliconcompiler.tools.vivado.place/PlaceTask
[flowgraph,fpgaflow-xilinx-hls,place,0,tool]	str	vivado

2.9.23.2.4. route/0

Keypath	Type	Value
[flowgraph,fpgaflow-xilinx-hls,route,0,input]	[(str,str)]	('place', '0')
[flowgraph,fpgaflow-xilinx-hls,route,0,task]	str	route
[flowgraph,fpgaflow-xilinx-hls,route,0,taskmodule]	str	siliconcompiler.tools.vivado.route/RouteTask
[flowgraph,fpgaflow-xilinx-hls,route,0,tool]	str	vivado

2.9.23.2.5. bitstream/0

Keypath	Type	Value
[flowgraph,fpgaflow-xilinx-hls,bitstream,0,input]	[(str,str)]	('route', '0')
[flowgraph,fpgaflow-xilinx-hls,bitstream,0,task]	str	bitstream
[flowgraph,fpgaflow-xilinx-hls,bitstream,0,taskmodule]	str	siliconcompiler.tools.vivado.bitstream/BitstreamTask
[flowgraph,fpgaflow-xilinx-hls,bitstream,0,tool]	str	vivado

2.9.24. fpgaflow-xilinx-bluespec / 5

An FPGA compilation flow targeting Xilinx devices using Vivado.

This flow uses the commercial Vivado toolchain for synthesis, placement, routing, and bitstream generation.

The flow consists of the following steps:

• elaborate: Elaborate the RTL design from sources.

• syn_fpga: Synthesize RTL into a device-specific netlist.

• place: Place the synthesized netlist onto the FPGA fabric.

• route: Route the connections between placed components.

• bitstream: Generate the final bitstream for device programming.

File: fpgaflow.py

2.9.24.1. Graph

2.9.24.2. Nodes

2.9.24.2.1. convert/0

Keypath	Type	Value
[flowgraph,fpgaflow-xilinx-bluespec,convert,0,task]	str	convert
[flowgraph,fpgaflow-xilinx-bluespec,convert,0,taskmodule]	str	siliconcompiler.tools.bluespec.convert/ConvertTask
[flowgraph,fpgaflow-xilinx-bluespec,convert,0,tool]	str	bluespec

2.9.24.2.2. syn_fpga/0

Keypath	Type	Value
[flowgraph,fpgaflow-xilinx-bluespec,syn_fpga,0,input]	[(str,str)]	('convert', '0')
[flowgraph,fpgaflow-xilinx-bluespec,syn_fpga,0,task]	str	syn_fpga
[flowgraph,fpgaflow-xilinx-bluespec,syn_fpga,0,taskmodule]	str	siliconcompiler.tools.vivado.syn_fpga/SynthesisTask
[flowgraph,fpgaflow-xilinx-bluespec,syn_fpga,0,tool]	str	vivado

2.9.24.2.3. place/0

Keypath	Type	Value
[flowgraph,fpgaflow-xilinx-bluespec,place,0,input]	[(str,str)]	('syn_fpga', '0')
[flowgraph,fpgaflow-xilinx-bluespec,place,0,task]	str	place
[flowgraph,fpgaflow-xilinx-bluespec,place,0,taskmodule]	str	siliconcompiler.tools.vivado.place/PlaceTask
[flowgraph,fpgaflow-xilinx-bluespec,place,0,tool]	str	vivado

2.9.24.2.4. route/0

Keypath	Type	Value
[flowgraph,fpgaflow-xilinx-bluespec,route,0,input]	[(str,str)]	('place', '0')
[flowgraph,fpgaflow-xilinx-bluespec,route,0,task]	str	route
[flowgraph,fpgaflow-xilinx-bluespec,route,0,taskmodule]	str	siliconcompiler.tools.vivado.route/RouteTask
[flowgraph,fpgaflow-xilinx-bluespec,route,0,tool]	str	vivado

2.9.24.2.5. bitstream/0

Keypath	Type	Value
[flowgraph,fpgaflow-xilinx-bluespec,bitstream,0,input]	[(str,str)]	('route', '0')
[flowgraph,fpgaflow-xilinx-bluespec,bitstream,0,task]	str	bitstream
[flowgraph,fpgaflow-xilinx-bluespec,bitstream,0,taskmodule]	str	siliconcompiler.tools.vivado.bitstream/BitstreamTask
[flowgraph,fpgaflow-xilinx-bluespec,bitstream,0,tool]	str	vivado

2.10. Utility Flows

Supporting flows for screenshots, format conversion, parasitic extraction, and interposer assembly.

2.10.1. showflow

A minimal flow to display a design file using its associated viewer.

This flow is automatically generated and consists of a single node that runs a specific ‘show’ or ‘screenshot’ task for a given file format (e.g., GDS, DEF).

File: showflow.py

2.10.1.1. Graph

2.10.1.2. Nodes

2.10.1.2.1. show/0

Keypath	Type	Value
[flowgraph,showflow,show,0,task]	str	show
[flowgraph,showflow,show,0,taskmodule]	str	siliconcompiler.tools.klayout.show/ShowTask
[flowgraph,showflow,show,0,tool]	str	klayout

2.10.2. screenshotflow / 0

A high resolution screenshot flow.

This flow is designed to generate a high resolution design image from a GDS or OAS file by preparing the layout, taking tiled screenshots, and merging them into a single image.

File: highresscreenshotflow.py

2.10.2.1. Graph

2.10.2.2. Nodes

2.10.2.2.1. import/0

Keypath	Type	Value
[flowgraph,screenshotflow,import,0,task]	str	importfiles
[flowgraph,screenshotflow,import,0,taskmodule]	str	siliconcompiler.tools.builtin.importfiles/ImportFilesTask
[flowgraph,screenshotflow,import,0,tool]	str	builtin

2.10.2.2.2. prepare/0

Keypath	Type	Value
[flowgraph,screenshotflow,prepare,0,input]	[(str,str)]	('import', '0')
[flowgraph,screenshotflow,prepare,0,task]	str	operations
[flowgraph,screenshotflow,prepare,0,taskmodule]	str	siliconcompiler.tools.klayout.operations/OperationsTask
[flowgraph,screenshotflow,prepare,0,tool]	str	klayout

2.10.2.2.3. screenshot/0

Keypath	Type	Value
[flowgraph,screenshotflow,screenshot,0,input]	[(str,str)]	('prepare', '0')
[flowgraph,screenshotflow,screenshot,0,task]	str	screenshot
[flowgraph,screenshotflow,screenshot,0,taskmodule]	str	siliconcompiler.tools.klayout.screenshot/ScreenshotTask
[flowgraph,screenshotflow,screenshot,0,tool]	str	klayout

2.10.2.2.4. merge/0

Keypath	Type	Value
[flowgraph,screenshotflow,merge,0,input]	[(str,str)]	('screenshot', '0')
[flowgraph,screenshotflow,merge,0,task]	str	tile
[flowgraph,screenshotflow,merge,0,taskmodule]	str	siliconcompiler.tools.montage.tile/TileTask
[flowgraph,screenshotflow,merge,0,tool]	str	montage

2.10.3. screenshotflow / 1

A high resolution screenshot flow.

This flow is designed to generate a high resolution design image from a GDS or OAS file by preparing the layout, taking tiled screenshots, and merging them into a single image.

File: highresscreenshotflow.py

2.10.3.1. Graph

2.10.3.2. Nodes

2.10.3.2.1. import/0

Keypath	Type	Value
[flowgraph,screenshotflow,import,0,task]	str	importfiles
[flowgraph,screenshotflow,import,0,taskmodule]	str	siliconcompiler.tools.builtin.importfiles/ImportFilesTask
[flowgraph,screenshotflow,import,0,tool]	str	builtin

2.10.3.2.2. screenshot/0

Keypath	Type	Value
[flowgraph,screenshotflow,screenshot,0,input]	[(str,str)]	('import', '0')
[flowgraph,screenshotflow,screenshot,0,task]	str	screenshot
[flowgraph,screenshotflow,screenshot,0,taskmodule]	str	siliconcompiler.tools.klayout.screenshot/ScreenshotTask
[flowgraph,screenshotflow,screenshot,0,tool]	str	klayout

2.10.3.2.3. merge/0

Keypath	Type	Value
[flowgraph,screenshotflow,merge,0,input]	[(str,str)]	('screenshot', '0')
[flowgraph,screenshotflow,merge,0,task]	str	tile
[flowgraph,screenshotflow,merge,0,taskmodule]	str	siliconcompiler.tools.montage.tile/TileTask
[flowgraph,screenshotflow,merge,0,tool]	str	montage

2.10.4. img2streamflow / 0

An image-to-stream flow with DRC verification.

This flow converts an image file (PNG/JPG) to a GDSII or OASIS stream using KLayout, then runs a design rule check on the resulting layout.

File: img2streamflow.py

2.10.4.1. Graph

2.10.4.2. Nodes

2.10.4.2.1. image/0

Keypath	Type	Value
[flowgraph,img2streamflow,image,0,task]	str	image2stream
[flowgraph,img2streamflow,image,0,taskmodule]	str	siliconcompiler.tools.klayout.img2stream/Img2StreamTask
[flowgraph,img2streamflow,image,0,tool]	str	klayout

2.10.5. img2streamflow-klayout / 1

An image-to-stream flow with DRC verification.

This flow converts an image file (PNG/JPG) to a GDSII or OASIS stream using KLayout, then runs a design rule check on the resulting layout.

File: img2streamflow.py

2.10.5.1. Graph

2.10.5.2. Nodes

2.10.5.2.1. image/0

Keypath	Type	Value
[flowgraph,img2streamflow-klayout,image,0,task]	str	image2stream
[flowgraph,img2streamflow-klayout,image,0,taskmodule]	str	siliconcompiler.tools.klayout.img2stream/Img2StreamTask
[flowgraph,img2streamflow-klayout,image,0,tool]	str	klayout

2.10.5.2.2. drc/0

Keypath	Type	Value
[flowgraph,img2streamflow-klayout,drc,0,input]	[(str,str)]	('image', '0')
[flowgraph,img2streamflow-klayout,drc,0,task]	str	drc
[flowgraph,img2streamflow-klayout,drc,0,taskmodule]	str	siliconcompiler.tools.klayout.drc/DRCTask
[flowgraph,img2streamflow-klayout,drc,0,tool]	str	klayout

2.10.6. img2streamflow-magic / 2

An image-to-stream flow with DRC verification.

This flow converts an image file (PNG/JPG) to a GDSII or OASIS stream using KLayout, then runs a design rule check on the resulting layout.

File: img2streamflow.py

2.10.6.1. Graph

2.10.6.2. Nodes

2.10.6.2.1. image/0

Keypath	Type	Value
[flowgraph,img2streamflow-magic,image,0,task]	str	image2stream
[flowgraph,img2streamflow-magic,image,0,taskmodule]	str	siliconcompiler.tools.klayout.img2stream/Img2StreamTask
[flowgraph,img2streamflow-magic,image,0,tool]	str	klayout

2.10.6.2.2. drc/0

Keypath	Type	Value
[flowgraph,img2streamflow-magic,drc,0,input]	[(str,str)]	('image', '0')
[flowgraph,img2streamflow-magic,drc,0,task]	str	drc
[flowgraph,img2streamflow-magic,drc,0,taskmodule]	str	siliconcompiler.tools.magic.drc/DRCTask
[flowgraph,img2streamflow-magic,drc,0,tool]	str	magic

2.10.7. generate_rcx / 0

A flow to generate OpenRCX parasitic extraction decks for OpenROAD.

This flow automates the process of characterizing a parasitic extraction tool to generate the necessary configuration files (RCX decks) for OpenROAD’s built-in OpenRCX engine. It works by comparing the output of a third-party “golden” extraction tool against OpenRCX’s results and calibrating OpenRCX accordingly.

The flow consists of the following main steps for each specified corner:

1. bench: A benchmark design with simple structures is created.

2. pex: A user-provided third-party PEX tool is run on the benchmark

   to generate a “golden” SPEF file.

3. extract: The golden SPEF is used to generate a calibrated OpenRCX

   deck.

File: generate_openroad_rcx.py

2.10.7.1. Graph

2.10.7.2. Nodes

2.10.7.2.1. bench/0

Keypath	Type	Value
[flowgraph,generate_rcx,bench,0,task]	str	rcx_bench
[flowgraph,generate_rcx,bench,0,taskmodule]	str	siliconcompiler.tools.openroad.rcx_bench/ORXBenchTask
[flowgraph,generate_rcx,bench,0,tool]	str	openroad

2.10.7.2.2. pex/0

Keypath	Type	Value
[flowgraph,generate_rcx,pex,0,input]	[(str,str)]	('bench', '0')
[flowgraph,generate_rcx,pex,0,task]	str	nop
[flowgraph,generate_rcx,pex,0,taskmodule]	str	siliconcompiler.tools.builtin.nop/NOPTask
[flowgraph,generate_rcx,pex,0,tool]	str	builtin

2.10.7.2.3. pex/1

Keypath	Type	Value
[flowgraph,generate_rcx,pex,1,input]	[(str,str)]	('bench', '0')
[flowgraph,generate_rcx,pex,1,task]	str	nop
[flowgraph,generate_rcx,pex,1,taskmodule]	str	siliconcompiler.tools.builtin.nop/NOPTask
[flowgraph,generate_rcx,pex,1,tool]	str	builtin

2.10.7.2.4. pex/2

Keypath	Type	Value
[flowgraph,generate_rcx,pex,2,input]	[(str,str)]	('bench', '0')
[flowgraph,generate_rcx,pex,2,task]	str	nop
[flowgraph,generate_rcx,pex,2,taskmodule]	str	siliconcompiler.tools.builtin.nop/NOPTask
[flowgraph,generate_rcx,pex,2,tool]	str	builtin

2.10.7.2.5. extract/0

Keypath	Type	Value
[flowgraph,generate_rcx,extract,0,input]	[(str,str)]	('pex', '0') ('bench', '0')
[flowgraph,generate_rcx,extract,0,task]	str	rcx_extract
[flowgraph,generate_rcx,extract,0,taskmodule]	str	siliconcompiler.tools.openroad.rcx_extract/ORXExtractTask
[flowgraph,generate_rcx,extract,0,tool]	str	openroad

2.10.7.2.6. extract/1

Keypath	Type	Value
[flowgraph,generate_rcx,extract,1,input]	[(str,str)]	('pex', '1') ('bench', '0')
[flowgraph,generate_rcx,extract,1,task]	str	rcx_extract
[flowgraph,generate_rcx,extract,1,taskmodule]	str	siliconcompiler.tools.openroad.rcx_extract/ORXExtractTask
[flowgraph,generate_rcx,extract,1,tool]	str	openroad

2.10.7.2.7. extract/2

Keypath	Type	Value
[flowgraph,generate_rcx,extract,2,input]	[(str,str)]	('pex', '2') ('bench', '0')
[flowgraph,generate_rcx,extract,2,task]	str	rcx_extract
[flowgraph,generate_rcx,extract,2,taskmodule]	str	siliconcompiler.tools.openroad.rcx_extract/ORXExtractTask
[flowgraph,generate_rcx,extract,2,tool]	str	openroad

2.10.8. generate_rcx / 1

A flow to generate OpenRCX parasitic extraction decks for OpenROAD.

This flow automates the process of characterizing a parasitic extraction tool to generate the necessary configuration files (RCX decks) for OpenROAD’s built-in OpenRCX engine. It works by comparing the output of a third-party “golden” extraction tool against OpenRCX’s results and calibrating OpenRCX accordingly.

The flow consists of the following main steps for each specified corner:

1. bench: A benchmark design with simple structures is created.

2. pex: A user-provided third-party PEX tool is run on the benchmark

   to generate a “golden” SPEF file.

3. extract: The golden SPEF is used to generate a calibrated OpenRCX

   deck.

File: generate_openroad_rcx.py

2.10.8.1. Graph

2.10.8.2. Nodes

2.10.8.2.1. bench/0

Keypath	Type	Value
[flowgraph,generate_rcx,bench,0,task]	str	rcx_bench
[flowgraph,generate_rcx,bench,0,taskmodule]	str	siliconcompiler.tools.openroad.rcx_bench/ORXBenchTask
[flowgraph,generate_rcx,bench,0,tool]	str	openroad

2.10.8.2.2. pex/0

Keypath	Type	Value
[flowgraph,generate_rcx,pex,0,input]	[(str,str)]	('bench', '0')
[flowgraph,generate_rcx,pex,0,task]	str	nop
[flowgraph,generate_rcx,pex,0,taskmodule]	str	siliconcompiler.tools.builtin.nop/NOPTask
[flowgraph,generate_rcx,pex,0,tool]	str	builtin

2.10.8.2.3. extract/0

Keypath	Type	Value
[flowgraph,generate_rcx,extract,0,input]	[(str,str)]	('pex', '0') ('bench', '0')
[flowgraph,generate_rcx,extract,0,task]	str	rcx_extract
[flowgraph,generate_rcx,extract,0,taskmodule]	str	siliconcompiler.tools.openroad.rcx_extract/ORXExtractTask
[flowgraph,generate_rcx,extract,0,tool]	str	openroad

2.10.8.2.4. pex.wait/1

Keypath	Type	Value
[flowgraph,generate_rcx,pex.wait,1,input]	[(str,str)]	('pex', '0')
[flowgraph,generate_rcx,pex.wait,1,task]	str	wait
[flowgraph,generate_rcx,pex.wait,1,taskmodule]	str	siliconcompiler.tools.builtin.wait/Wait
[flowgraph,generate_rcx,pex.wait,1,tool]	str	builtin

2.10.8.2.5. pex/1

Keypath	Type	Value
[flowgraph,generate_rcx,pex,1,input]	[(str,str)]	('bench', '0') ('pex.wait', '1')
[flowgraph,generate_rcx,pex,1,task]	str	nop
[flowgraph,generate_rcx,pex,1,taskmodule]	str	siliconcompiler.tools.builtin.nop/NOPTask
[flowgraph,generate_rcx,pex,1,tool]	str	builtin

2.10.8.2.6. extract/1

Keypath	Type	Value
[flowgraph,generate_rcx,extract,1,input]	[(str,str)]	('pex', '1') ('bench', '0')
[flowgraph,generate_rcx,extract,1,task]	str	rcx_extract
[flowgraph,generate_rcx,extract,1,taskmodule]	str	siliconcompiler.tools.openroad.rcx_extract/ORXExtractTask
[flowgraph,generate_rcx,extract,1,tool]	str	openroad

2.10.8.2.7. pex.wait/2

Keypath	Type	Value
[flowgraph,generate_rcx,pex.wait,2,input]	[(str,str)]	('pex', '1')
[flowgraph,generate_rcx,pex.wait,2,task]	str	wait
[flowgraph,generate_rcx,pex.wait,2,taskmodule]	str	siliconcompiler.tools.builtin.wait/Wait
[flowgraph,generate_rcx,pex.wait,2,tool]	str	builtin

2.10.8.2.8. pex/2

Keypath	Type	Value
[flowgraph,generate_rcx,pex,2,input]	[(str,str)]	('bench', '0') ('pex.wait', '2')
[flowgraph,generate_rcx,pex,2,task]	str	nop
[flowgraph,generate_rcx,pex,2,taskmodule]	str	siliconcompiler.tools.builtin.nop/NOPTask
[flowgraph,generate_rcx,pex,2,tool]	str	builtin

2.10.8.2.9. extract/2

Keypath	Type	Value
[flowgraph,generate_rcx,extract,2,input]	[(str,str)]	('pex', '2') ('bench', '0')
[flowgraph,generate_rcx,extract,2,task]	str	rcx_extract
[flowgraph,generate_rcx,extract,2,taskmodule]	str	siliconcompiler.tools.openroad.rcx_extract/ORXExtractTask
[flowgraph,generate_rcx,extract,2,tool]	str	openroad

2.10.9. interposerflow

A flow to perform Redistribution Layer (RDL) routing and generate a GDS.

This flow is designed for creating interposers or other simple routing layers. It uses OpenROAD for RDL routing and KLayout to export the final layout to a GDSII file.

The flow consists of the following steps:

• rdlroute: Performs RDL routing on the input design.

• write_gds: Exports the routed design to a GDSII file.

File: interposerflow.py

2.10.9.1. Graph

2.10.9.2. Nodes

2.10.9.2.1. rdlroute/0

Keypath	Type	Value
[flowgraph,interposerflow,rdlroute,0,task]	str	rdlroute
[flowgraph,interposerflow,rdlroute,0,taskmodule]	str	siliconcompiler.tools.openroad.rdlroute/RDLRouteTask
[flowgraph,interposerflow,rdlroute,0,tool]	str	openroad

2.10.9.2.2. write_gds/0

Keypath	Type	Value
[flowgraph,interposerflow,write_gds,0,input]	[(str,str)]	('rdlroute', '0')
[flowgraph,interposerflow,write_gds,0,task]	str	export
[flowgraph,interposerflow,write_gds,0,taskmodule]	str	siliconcompiler.tools.klayout.export/ExportTask
[flowgraph,interposerflow,write_gds,0,tool]	str	klayout