1. Pre-Defined Targets#

The following are examples are pre-built targets that come with SiliconCompiler which you can use for your own builds. These are typically “demo” targets which use a specific combination of predefined pdk, library, flow and more configurations.

1.1. asap7_demo#

Configure an ASIC for the ASAP7 PDK with multi-Vt libraries, flows, timing corners, and physical constraints.

Sets the main and additional standard-cell libraries (RVT, LVT, SLVT), installs synthesis and full ASIC flows, selects the “asap7” PDK, creates slow/typical/fast STA scenarios using NLDM delay model, applies area constraints (40% core density, 1 µm core margin), and registers example IP/macro library aliases.

Parameters:

project (ASIC): The siliconcompiler project to configure.
syn_np (int): Parallel process count for synthesis.
floorplan_np (int): Parallel process count for floorplanning.
place_np (int): Parallel process count for placement.
cts_np (int): Parallel process count for clock-tree synthesis.
route_np (int): Parallel process count for routing.
timing_np (int): Parallel process count for timing-analysis synthesis.

File: asap7_demo.py

1.1.1. Code#

def asap7_demo(
        project: ASIC,
        syn_np: int = 1,
        floorplan_np: int = 1, place_np: int = 1, cts_np: int = 1, route_np: int = 1,
        timing_np: int = 1):
    """
        Configure an ASIC for the ASAP7 PDK with multi-Vt libraries, flows, timing corners,
        and physical constraints.

        Sets the main and additional standard-cell libraries (RVT, LVT, SLVT), installs synthesis
        and full ASIC flows, selects the "asap7" PDK, creates slow/typical/fast STA scenarios
        using NLDM delay model, applies area constraints (40% core density, 1 µm core margin),
        and registers example IP/macro library aliases.

        Parameters:
            * project (ASIC): The siliconcompiler project to configure.
            * syn_np (int): Parallel process count for synthesis.
            * floorplan_np (int): Parallel process count for floorplanning.
            * place_np (int): Parallel process count for placement.
            * cts_np (int): Parallel process count for clock-tree synthesis.
            * route_np (int): Parallel process count for routing.
            * timing_np (int): Parallel process count for timing-analysis synthesis.
        """

    # 1. Load Standard Cell Libraries
    # ASAP7 provides cells with different threshold voltages (Vt) to allow for
    # trade-offs between performance and power consumption.
    # RVT (Regular Vt) is set as the default main library.
    # LVT (Low Vt) and SLVT (Super Low Vt) are also added for the tools to use
    # for timing optimization on critical paths.
    project.set_mainlib(ASAP7SC7p5RVT())
    project.add_asiclib(ASAP7SC7p5LVT())
    project.add_asiclib(ASAP7SC7p5SLVT())

    # 2. Configure Compilation Flows
    # Defines the sequence of steps (tools) for the complete ASIC design flow
    # from synthesis to GDSII. Also adds a separate synthesis-only flow.
    project.set_flow(asicflow.ASICFlow(
        syn_np=syn_np,
        floorplan_np=floorplan_np,
        place_np=place_np,
        cts_np=cts_np,
        route_np=route_np))
    project.add_dep(synflow.SynthesisFlow(
        syn_np=syn_np,
        timing_np=timing_np))

    # 3. Set Target PDK
    # Specifies the process development kit to be used, which contains
    # technology-specific information for the ASAP7 process.
    project.set_pdk("asap7")

    # 4. Define Timing Corners for Static Timing Analysis (STA)
    # Sets up different scenarios to analyze timing performance under various
    # process, voltage, and temperature (PVT) conditions.

    # Slow corner: Checks for setup time violations at worst-case conditions.
    scenario = project.constraint.timing.make_scenario("slow")
    scenario.add_libcorner(["slow", "generic"])
    scenario.set_pexcorner("typical")
    scenario.add_check("setup")

    # Typical corner: Used for power analysis under nominal conditions.
    scenario = project.constraint.timing.make_scenario("typical")
    scenario.add_libcorner(["typical", "generic"])
    scenario.set_pexcorner("typical")
    scenario.add_check("power")

    # Fast corner: Checks for hold time violations at best-case conditions.
    scenario = project.constraint.timing.make_scenario("fast")
    scenario.add_libcorner(["fast", "generic"])
    scenario.set_pexcorner("typical")
    scenario.add_check("hold")

    # Set the delay model used for timing calculations. NLDM is a common standard.
    project.set_asic_delaymodel("nldm")

    # 5. Define Physical Design Constraints
    # These constraints guide the place-and-route tools.
    area = project.constraint.area
    # Target a core utilization of 40%.
    area.set_density(40)
    # Set a margin of 1 micron around the core area.
    area.set_coremargin(1)

    # 6. Alias and Register IP/Macro Libraries
    # Makes specialized libraries like SRAM and IO cells available to the flow
    # under a common, standardized naming convention. These are 'fake' libraries
    # for demonstration and academic purposes.
    FakeRAM7Lambdalib_SinglePort.alias(project)
    FakeRAM7Lambdalib_SinglePortRegfile.alias(project)
    FakeRAM7Lambdalib_DoublePort.alias(project)
    FakeRAM7Lambdalib_TrueDoublePort.alias(project)
    FakeIO7Lambdalib_IO.alias(project)

1.1.2. Flowgraph#

1.1.3. PDK#

asap7

1.1.4. StdCellLibrary#

1.1.5. Configuration#

Keypath	Type	Value
`[asic,asiclib]`	`{str}`	`asap7sc7p5t_lvt` `asap7sc7p5t_slvt`
`[asic,delaymodel]`	`str`	`nldm`
`[asic,mainlib]`	`str`	`asap7sc7p5t_rvt`
`[asic,pdk]`	`str`	`asap7`
`[constraint,area,aspectratio]`	`float`	`1.0`
`[constraint,area,coremargin]`	`float`	`1.0`
`[constraint,area,density]`	`float`	`40.0`
`[constraint,timing,scenario,fast,check]`	`{enum}`	`hold`
`[constraint,timing,scenario,fast,libcorner]`	`{str}`	`fast` `generic`
`[constraint,timing,scenario,fast,pexcorner]`	`str`	`typical`
`[constraint,timing,scenario,slow,check]`	`{enum}`	`setup`
`[constraint,timing,scenario,slow,libcorner]`	`{str}`	`generic` `slow`
`[constraint,timing,scenario,slow,pexcorner]`	`str`	`typical`
`[constraint,timing,scenario,typical,check]`	`{enum}`	`power`
`[constraint,timing,scenario,typical,libcorner]`	`{str}`	`generic` `typical`
`[constraint,timing,scenario,typical,pexcorner]`	`str`	`typical`
`[option,autoissue]`	`bool`	`False`
`[option,breakpoint]`	`bool`	`False`
`[option,builddir]`	`dir`	`build`
`[option,clean]`	`bool`	`False`
`[option,continue]`	`bool`	`False`
`[option,flow]`	`str`	`asicflow`
`[option,hash]`	`bool`	`False`
`[option,jobincr]`	`bool`	`False`
`[option,jobname]`	`str`	`job0`
`[option,nodashboard]`	`bool`	`False`
`[option,nodisplay]`	`bool`	`False`
`[option,novercheck]`	`bool`	`False`
`[option,optmode]`	`int`	`0`
`[option,quiet]`	`bool`	`False`
`[option,remote]`	`bool`	`False`
`[option,track]`	`bool`	`False`
`[schemaversion]`	`str`	`0.54.0`

1.2. freepdk45_demo#

Configure an ASIC for the FreePDK45 process: load Nangate45 standard-cell library, set synthesis/implementation flows, select the PDK, apply a typical timing scenario and NLDM delay model, set area constraints, and alias the fake RAM library.

Parameters:

project (ASIC): Project to configure.
syn_np (int): Parallelism (number of worker processes) for synthesis.
floorplan_np (int): Parallelism for floorplanning.
place_np (int): Parallelism for placement.
cts_np (int): Parallelism for clock-tree synthesis.
route_np (int): Parallelism for routing.
timing_np (int): Parallelism for timing analysis.

File: freepdk45_demo.py

1.2.1. Code#

def freepdk45_demo(
        project: ASIC,
        syn_np: int = 1,
        floorplan_np: int = 1, place_np: int = 1, cts_np: int = 1, route_np: int = 1,
        timing_np: int = 1):
    """
        Configure an ASIC for the FreePDK45 process: load Nangate45 standard-cell library,
        set synthesis/implementation flows, select the PDK, apply a typical timing scenario and
        NLDM delay model, set area constraints, and alias the fake RAM library.

        Parameters:
            * project (ASIC): Project to configure.
            * syn_np (int): Parallelism (number of worker processes) for synthesis.
            * floorplan_np (int): Parallelism for floorplanning.
            * place_np (int): Parallelism for placement.
            * cts_np (int): Parallelism for clock-tree synthesis.
            * route_np (int): Parallelism for routing.
            * timing_np (int): Parallelism for timing analysis.
        """

    # 1. Load Standard Cell Library
    # Sets the Nangate45 open-source standard cell library as the primary
    # library for the design.
    project.set_mainlib(Nangate45())

    # 2. Configure Compilation Flows
    # Defines the sequence of steps (tools) for the complete ASIC design flow
    # from synthesis to GDSII. Also adds a separate synthesis-only flow.
    project.set_flow(asicflow.ASICFlow(
        syn_np=syn_np,
        floorplan_np=floorplan_np,
        place_np=place_np,
        cts_np=cts_np,
        route_np=route_np))
    project.add_dep(synflow.SynthesisFlow(
        syn_np=syn_np,
        timing_np=timing_np))

    # 3. Set Target PDK
    # Specifies the process development kit to be used.
    project.set_pdk("freepdk45")

    # 4. Define Timing Constraints
    # For this demonstration target, a single "typical" timing corner is
    # configured to check for both setup and hold violations. In a real
    # production flow, separate slow and fast corners would be used.
    scenario = project.constraint.timing.make_scenario("typical")
    scenario.add_libcorner(["typical", "generic"])
    scenario.set_pexcorner("typical")
    scenario.add_check(["setup", "hold", "power"])

    # Set the delay model used for timing calculations. NLDM is a common standard.
    project.set_asic_delaymodel("nldm")

    # 5. Define Physical Design Constraints
    # These constraints guide the place-and-route tools.
    area = project.constraint.area
    # Target a core utilization of 40%.
    area.set_density(40)
    # Set a margin of 1 micron around the core area.
    area.set_coremargin(1)

    # 6. Alias and Register IP/Macro Libraries
    # Makes the fake SRAM library available to the flow under a common,
    # standardized naming convention.
    FakeRAM45Lambdalib_SinglePort.alias(project)
    FakeRAM45Lambdalib_SinglePortRegfile.alias(project)

1.2.2. Flowgraph#

1.2.3. PDK#

freepdk45

1.2.4. StdCellLibrary#

nangate45

1.2.5. Configuration#

Keypath	Type	Value
`[asic,delaymodel]`	`str`	`nldm`
`[asic,mainlib]`	`str`	`nangate45`
`[asic,pdk]`	`str`	`freepdk45`
`[constraint,area,aspectratio]`	`float`	`1.0`
`[constraint,area,coremargin]`	`float`	`1.0`
`[constraint,area,density]`	`float`	`40.0`
`[constraint,timing,scenario,typical,check]`	`{enum}`	`hold` `power` `setup`
`[constraint,timing,scenario,typical,libcorner]`	`{str}`	`generic` `typical`
`[constraint,timing,scenario,typical,pexcorner]`	`str`	`typical`
`[option,autoissue]`	`bool`	`False`
`[option,breakpoint]`	`bool`	`False`
`[option,builddir]`	`dir`	`build`
`[option,clean]`	`bool`	`False`
`[option,continue]`	`bool`	`False`
`[option,flow]`	`str`	`asicflow`
`[option,hash]`	`bool`	`False`
`[option,jobincr]`	`bool`	`False`
`[option,jobname]`	`str`	`job0`
`[option,nodashboard]`	`bool`	`False`
`[option,nodisplay]`	`bool`	`False`
`[option,novercheck]`	`bool`	`False`
`[option,optmode]`	`int`	`0`
`[option,quiet]`	`bool`	`False`
`[option,remote]`	`bool`	`False`
`[option,track]`	`bool`	`False`
`[schemaversion]`	`str`	`0.54.0`

1.3. gf180_demo#

Configure an ASIC for the GlobalFoundries 180nm (GF180) process by registering the PDK and standard-cell/IP libraries, installing compilation flows, creating STA timing corners, and setting physical area constraints.

Parameters:

project (ASIC): The siliconcompiler project to configure.
syn_np (int): Parallelism for synthesis.
floorplan_np (int): Parallelism for floorplanning.
place_np (int): Parallelism for placement.
cts_np (int): Parallelism for clock-tree synthesis.
route_np (int): Parallelism for routing.
timing_np (int): Parallelism for timing analysis.

File: gf180_demo.py

1.3.1. Code#

def gf180_demo(
        project: ASIC,
        syn_np: int = 1,
        floorplan_np: int = 1, place_np: int = 1, cts_np: int = 1, route_np: int = 1,
        timing_np: int = 1):
    """
        Configure an ASIC for the GlobalFoundries 180nm (GF180) process by registering
        the PDK and standard-cell/IP libraries, installing compilation flows, creating STA
        timing corners, and setting physical area constraints.

        Parameters:
            * project (ASIC): The siliconcompiler project to configure.
            * syn_np (int): Parallelism for synthesis.
            * floorplan_np (int): Parallelism for floorplanning.
            * place_np (int): Parallelism for placement.
            * cts_np (int): Parallelism for clock-tree synthesis.
            * route_np (int): Parallelism for routing.
            * timing_np (int): Parallelism for timing analysis.
        """

    # 1. Load PDK and Standard Cell Libraries
    # Sets the process development kit and the standard cell libraries
    # that provide the basic logic gates and flip-flops for the design.
    project.set_pdk(GF180_5LM_1TM_9K_9t())
    project.add_asiclib(GF180_MCU_9T_5LMLibrary())
    project.set_mainlib(GF180_MCU_9T_5LMLibrary())

    # 2. Configure Compilation Flows
    # Defines the sequence of steps (tools) for the complete ASIC design flow
    # from synthesis to GDSII. Also adds a separate synthesis-only flow.
    project.set_flow(asicflow.ASICFlow(
        syn_np=syn_np,
        floorplan_np=floorplan_np,
        place_np=place_np,
        cts_np=cts_np,
        route_np=route_np))
    project.add_dep(synflow.SynthesisFlow(
        syn_np=syn_np,
        timing_np=timing_np))

    # 3. Define Timing Corners for Static Timing Analysis (STA)
    # Sets up different scenarios to analyze timing performance under various
    # process, voltage, and temperature (PVT) conditions. Note the specific
    # voltages set for each corner.

    # Slow corner: Checks for setup time violations at worst-case conditions
    # (slow process, low voltage).
    scenario = project.constraint.timing.make_scenario("slow")
    scenario.add_libcorner("slow")
    scenario.set_pexcorner("wst")
    scenario.add_check("setup")
    scenario.set_pin_voltage("VDD", 4.5)

    # Typical corner: Used for power analysis under nominal conditions.
    scenario = project.constraint.timing.make_scenario("typical")
    scenario.add_libcorner("typical")
    scenario.set_pexcorner("typ")
    scenario.add_check("power")
    scenario.set_pin_voltage("VDD", 5.0)

    # Fast corner: Checks for hold time violations at best-case conditions
    # (fast process, high voltage).
    scenario = project.constraint.timing.make_scenario("fast")
    scenario.add_libcorner("fast")
    scenario.set_pexcorner("bst")
    scenario.add_check("hold")
    scenario.set_pin_voltage("VDD", 5.5)

    # Set the delay model used for timing calculations. NLDM is a common standard.
    project.set_asic_delaymodel("nldm")

    # 4. Define Physical Design Constraints
    # These constraints guide the place-and-route tools.
    area = project.constraint.area
    # Target a core utilization of 40%.
    area.set_density(40)
    # Set a margin of 1 micron around the core area.
    area.set_coremargin(1)

    # 5. Alias and Register IP/Macro Libraries
    # Makes specialized libraries like SRAM and IO cells available to the flow
    # under a common, standardized naming convention.
    GF180Lambdalib_SinglePort.alias(project)
    GF180Lambdalib_SinglePortRegfile.alias(project)
    GF180Lambdalib_IO_5LM.alias(project)

1.3.2. Flowgraph#

1.3.3. PDK#

1.3.4. StdCellLibrary#

gf180mcu_fd_sc_mcu9t5v0_5LM

1.3.5. Configuration#

Keypath	Type	Value
`[asic,asiclib]`	`{str}`	`gf180mcu_fd_sc_mcu9t5v0_5LM`
`[asic,delaymodel]`	`str`	`nldm`
`[asic,mainlib]`	`str`	`gf180mcu_fd_sc_mcu9t5v0_5LM`
`[asic,pdk]`	`str`	`GF180_5LM_1TM_9K_9t`
`[constraint,area,aspectratio]`	`float`	`1.0`
`[constraint,area,coremargin]`	`float`	`1.0`
`[constraint,area,density]`	`float`	`40.0`
`[constraint,timing,scenario,fast,check]`	`{enum}`	`hold`
`[constraint,timing,scenario,fast,libcorner]`	`{str}`	`fast`
`[constraint,timing,scenario,fast,pexcorner]`	`str`	`bst`
`[constraint,timing,scenario,fast,voltage,VDD]`	`float`	`5.5`
`[constraint,timing,scenario,slow,check]`	`{enum}`	`setup`
`[constraint,timing,scenario,slow,libcorner]`	`{str}`	`slow`
`[constraint,timing,scenario,slow,pexcorner]`	`str`	`wst`
`[constraint,timing,scenario,slow,voltage,VDD]`	`float`	`4.5`
`[constraint,timing,scenario,typical,check]`	`{enum}`	`power`
`[constraint,timing,scenario,typical,libcorner]`	`{str}`	`typical`
`[constraint,timing,scenario,typical,pexcorner]`	`str`	`typ`
`[constraint,timing,scenario,typical,voltage,VDD]`	`float`	`5.0`
`[option,autoissue]`	`bool`	`False`
`[option,breakpoint]`	`bool`	`False`
`[option,builddir]`	`dir`	`build`
`[option,clean]`	`bool`	`False`
`[option,continue]`	`bool`	`False`
`[option,flow]`	`str`	`asicflow`
`[option,hash]`	`bool`	`False`
`[option,jobincr]`	`bool`	`False`
`[option,jobname]`	`str`	`job0`
`[option,nodashboard]`	`bool`	`False`
`[option,nodisplay]`	`bool`	`False`
`[option,novercheck]`	`bool`	`False`
`[option,optmode]`	`int`	`0`
`[option,quiet]`	`bool`	`False`
`[option,remote]`	`bool`	`False`
`[option,track]`	`bool`	`False`
`[schemaversion]`	`str`	`0.54.0`

1.4. ihp130_demo#

Configure a siliconcompiler ASIC for the IHP 130nm PDK, including libraries, flows, timing scenarios, and basic physical constraints.

Sets the project’s main standard-cell library, configures full ASIC and synthesis-only flows with provided parallelism, selects the “ihp130” PDK, creates slow/typical/fast STA scenarios, sets the ASIC delay model to “nldm”, applies core area density and margin constraints, and registers the IHP130 SRAM and IO libraries.

Parameters:

project (ASIC): The siliconcompiler project to configure.
syn_np (int): Parallelism for synthesis-related steps.
floorplan_np (int): Parallelism for floorplanning.
place_np (int): Parallelism for placement.
cts_np (int): Parallelism for clock-tree synthesis.
route_np (int): Parallelism for routing.
timing_np (int): Parallelism for timing analysis (synthesis-only flow).

File: ihp130_demo.py

1.4.1. Code#

def ihp130_demo(
        project: ASIC,
        syn_np: int = 1,
        floorplan_np: int = 1, place_np: int = 1, cts_np: int = 1, route_np: int = 1,
        timing_np: int = 1):
    """
        Configure a siliconcompiler ASIC for the IHP 130nm PDK, including libraries,
        flows, timing scenarios, and basic physical constraints.

        Sets the project's main standard-cell library, configures full ASIC and synthesis-only
        flows with provided parallelism, selects the "ihp130" PDK, creates slow/typical/fast STA
        scenarios, sets the ASIC delay model to "nldm", applies core area density and margin
        constraints, and registers the IHP130 SRAM and IO libraries.

        Parameters:
            * project (ASIC): The siliconcompiler project to configure.
            * syn_np (int): Parallelism for synthesis-related steps.
            * floorplan_np (int): Parallelism for floorplanning.
            * place_np (int): Parallelism for placement.
            * cts_np (int): Parallelism for clock-tree synthesis.
            * route_np (int): Parallelism for routing.
            * timing_np (int): Parallelism for timing analysis (synthesis-only flow).
        """

    # 1. Load Standard Cell Library
    # Sets the primary standard cell library for the design. This library
    # contains the basic building blocks (gates, flip-flops) for synthesis.
    project.set_mainlib(IHP130StdCell_1p2())

    # 2. Configure Compilation Flows
    # Defines the sequence of steps (tools) for the complete ASIC design flow
    # from synthesis to GDSII. Also adds a separate synthesis-only flow.
    project.set_flow(asicflow.ASICFlow(
        syn_np=syn_np,
        floorplan_np=floorplan_np,
        place_np=place_np,
        cts_np=cts_np,
        route_np=route_np))
    project.add_dep(synflow.SynthesisFlow(
        syn_np=syn_np,
        timing_np=timing_np))

    # 3. Set Target PDK
    # Specifies the process development kit to be used.
    project.set_pdk("ihp130")

    # 4. Define Timing Corners for Static Timing Analysis (STA)
    # Sets up different scenarios to analyze timing performance under various
    # process, voltage, and temperature (PVT) conditions.

    # Slow corner: Checks for setup time violations at worst-case conditions.
    scenario = project.constraint.timing.make_scenario("slow")
    scenario.add_libcorner("slow")
    scenario.set_pexcorner("typical")
    scenario.add_check("setup")

    # Typical corner: Used for power analysis under nominal conditions.
    scenario = project.constraint.timing.make_scenario("typical")
    scenario.add_libcorner("typical")
    scenario.set_pexcorner("typical")
    scenario.add_check("power")

    # Fast corner: Checks for hold time violations at best-case conditions.
    scenario = project.constraint.timing.make_scenario("fast")
    scenario.add_libcorner("fast")
    scenario.set_pexcorner("typical")
    scenario.add_check("hold")

    # Set the delay model used for timing calculations. NLDM is a common standard.
    project.set_asic_delaymodel("nldm")

    # 5. Define Physical Design Constraints
    # These constraints guide the place-and-route tools.
    area = project.constraint.area
    # Target a core utilization of 40%.
    area.set_density(40)
    # Set a margin of 4.8 microns around the core area.
    area.set_coremargin(4.8)

    # 6. Alias and Register IP/Macro Libraries
    # Makes specialized libraries like SRAM and IO cells available to the flow
    # under a common, standardized naming convention.
    IHP130Lambdalib_SinglePort.alias(project)
    IHP130Lambdalib_SinglePortRegfile.alias(project)
    IHP130LambdaLib_IO_1p2.alias(project)

1.4.2. Flowgraph#

1.4.3. PDK#

ihp130

1.4.4. StdCellLibrary#

sg13g2_stdcell_1p2

1.4.5. Configuration#

Keypath	Type	Value
`[asic,delaymodel]`	`str`	`nldm`
`[asic,mainlib]`	`str`	`sg13g2_stdcell_1p2`
`[asic,pdk]`	`str`	`ihp130`
`[constraint,area,aspectratio]`	`float`	`1.0`
`[constraint,area,coremargin]`	`float`	`4.8`
`[constraint,area,density]`	`float`	`40.0`
`[constraint,timing,scenario,fast,check]`	`{enum}`	`hold`
`[constraint,timing,scenario,fast,libcorner]`	`{str}`	`fast`
`[constraint,timing,scenario,fast,pexcorner]`	`str`	`typical`
`[constraint,timing,scenario,slow,check]`	`{enum}`	`setup`
`[constraint,timing,scenario,slow,libcorner]`	`{str}`	`slow`
`[constraint,timing,scenario,slow,pexcorner]`	`str`	`typical`
`[constraint,timing,scenario,typical,check]`	`{enum}`	`power`
`[constraint,timing,scenario,typical,libcorner]`	`{str}`	`typical`
`[constraint,timing,scenario,typical,pexcorner]`	`str`	`typical`
`[option,autoissue]`	`bool`	`False`
`[option,breakpoint]`	`bool`	`False`
`[option,builddir]`	`dir`	`build`
`[option,clean]`	`bool`	`False`
`[option,continue]`	`bool`	`False`
`[option,flow]`	`str`	`asicflow`
`[option,hash]`	`bool`	`False`
`[option,jobincr]`	`bool`	`False`
`[option,jobname]`	`str`	`job0`
`[option,nodashboard]`	`bool`	`False`
`[option,nodisplay]`	`bool`	`False`
`[option,novercheck]`	`bool`	`False`
`[option,optmode]`	`int`	`0`
`[option,quiet]`	`bool`	`False`
`[option,remote]`	`bool`	`False`
`[option,track]`	`bool`	`False`
`[schemaversion]`	`str`	`0.54.0`

1.5. interposer_demo#

Configure a siliconcompiler project for generating a passive interposer layout.

This configures the project for a passive interposer target by selecting the interposer PDK and bump library, setting an interposer-focused flow with DRC dependency, creating a basic “typical” timing scenario (libcorner, pexcorner, and setup/hold/power checks), setting the ASIC delay model to “nldm”, and applying physical area constraints (40% routing density and 1 unit core margin). No lambdalib/IP aliases are defined.

Parameters:

project (ASIC): The siliconcompiler project to configure.

File: interposer_demo.py

1.5.1. Code#

def interposer_demo(project: ASIC):
    """
    Configure a siliconcompiler project for generating a passive interposer layout.

    This configures the project for a passive interposer target by selecting the interposer PDK
    and bump library, setting an interposer-focused flow with DRC dependency, creating a basic
    "typical" timing scenario (libcorner, pexcorner, and setup/hold/power checks), setting the
    ASIC delay model to "nldm", and applying physical area constraints
    (40% routing density and 1 unit core margin). No lambdalib/IP aliases are defined.

    Parameters:
        * project (ASIC): The siliconcompiler project to configure.
    """

    # 1. Load Interposer PDK and Bump Library
    # Sets the process development kit specifically designed for the interposer's
    # manufacturing process and loads the library defining the physical
    # characteristics of the connection bumps.
    project.set_pdk(Interposer_3ML_0400())
    project.set_mainlib(BumpLibrary())

    # 2. Configure Compilation Flows
    # The 'interposerflow' is a specialized flow for generating the layout of a
    # passive interposer. It focuses on routing between bump locations.
    # A 'drcflow' (Design Rule Check) is added as a dependency to ensure the
    # final layout adheres to the PDK's manufacturing rules.
    project.set_flow(interposerflow.InterposerFlow())
    project.add_dep(drcflow.DRCFlow())

    # 3. Define a Basic Timing Scenario
    # While passive interposers do not have active logic for traditional setup/hold
    # timing analysis, a basic scenario is defined. This can be used for signal
    # integrity analysis, delay extraction, or to satisfy tool requirements.
    scenario = project.constraint.timing.make_scenario("typical")
    scenario.add_libcorner("typical")
    scenario.set_pexcorner("typical")
    # Checks for setup, hold, and power are included mainly for tool compatibility.
    scenario.add_check(["setup", "hold", "power"])

    # Set a delay model, though its application is limited in a passive context.
    project.set_asic_delaymodel("nldm")

    # 4. Define Physical Design Constraints
    # These constraints guide the routing tools.
    area = project.constraint.area
    # Target a routing density of 40%.
    area.set_density(40)
    # Set a margin of 1 unit (e.g., microns) around the interposer area.
    area.set_coremargin(1)

    # 5. Assign Lambdalib Aliases
    # No specialized IP aliases (like SRAM or IOs) are needed for this
    # simple passive interposer target.

1.5.2. Flowgraph#

1.5.3. PDK#

1.5.4. StdCellLibrary#

interposer_bumps

1.5.5. Configuration#

Keypath	Type	Value
`[asic,delaymodel]`	`str`	`nldm`
`[asic,mainlib]`	`str`	`interposer_bumps`
`[asic,pdk]`	`str`	`interposer_3ML_0400`
`[constraint,area,aspectratio]`	`float`	`1.0`
`[constraint,area,coremargin]`	`float`	`1.0`
`[constraint,area,density]`	`float`	`40.0`
`[constraint,timing,scenario,typical,check]`	`{enum}`	`hold` `power` `setup`
`[constraint,timing,scenario,typical,libcorner]`	`{str}`	`typical`
`[constraint,timing,scenario,typical,pexcorner]`	`str`	`typical`
`[option,autoissue]`	`bool`	`False`
`[option,breakpoint]`	`bool`	`False`
`[option,builddir]`	`dir`	`build`
`[option,clean]`	`bool`	`False`
`[option,continue]`	`bool`	`False`
`[option,flow]`	`str`	`interposerflow`
`[option,hash]`	`bool`	`False`
`[option,jobincr]`	`bool`	`False`
`[option,jobname]`	`str`	`job0`
`[option,nodashboard]`	`bool`	`False`
`[option,nodisplay]`	`bool`	`False`
`[option,novercheck]`	`bool`	`False`
`[option,optmode]`	`int`	`0`
`[option,quiet]`	`bool`	`False`
`[option,remote]`	`bool`	`False`
`[option,track]`	`bool`	`False`
`[schemaversion]`	`str`	`0.54.0`

1.6. skywater130_demo#

Configures a siliconcompiler project for the Skywater130 process development kit (PDK).

This function sets up the entire compilation pipeline, including the standard cell library, compilation flows, timing constraints, and physical design parameters for a Skywater130 target.

Args:

project (ASIC): The siliconcompiler project to configure.
syn_np (int): Number of parallel processes for synthesis.
floorplan_np (int): Number of parallel processes for floorplanning.
place_np (int): Number of parallel processes for placement.
cts_np (int): Number of parallel processes for clock tree synthesis.
route_np (int): Number of parallel processes for routing.
timing_np (int): Number of parallel processes for timing analysis.

File: skywater130_demo.py

1.6.1. Code#

def skywater130_demo(
        project: ASIC,
        syn_np: int = 1,
        floorplan_np: int = 1, place_np: int = 1, cts_np: int = 1, route_np: int = 1,
        timing_np: int = 1):
    '''
    Configures a siliconcompiler project for the Skywater130 process development kit (PDK).

    This function sets up the entire compilation pipeline, including the
    standard cell library, compilation flows, timing constraints, and
    physical design parameters for a Skywater130 target.

    Args:
        * project (:class:`ASIC`): The siliconcompiler project to configure.
        * syn_np (int): Number of parallel processes for synthesis.
        * floorplan_np (int): Number of parallel processes for floorplanning.
        * place_np (int): Number of parallel processes for placement.
        * cts_np (int): Number of parallel processes for clock tree synthesis.
        * route_np (int): Number of parallel processes for routing.
        * timing_np (int): Number of parallel processes for timing analysis.
    '''

    # 1. Load Standard Cell Library
    # Sets the primary standard cell library for the design. This library
    # contains the basic building blocks (gates, flip-flops) for synthesis.
    project.set_mainlib(Sky130_SCHDLibrary())

    # 2. Configure Compilation Flows
    # Defines the sequence of steps (tools) for the complete ASIC design flow
    # from synthesis to GDSII. Also adds a separate synthesis-only flow.
    project.set_flow(asicflow.ASICFlow(
        syn_np=syn_np,
        floorplan_np=floorplan_np,
        place_np=place_np,
        cts_np=cts_np,
        route_np=route_np))
    project.add_dep(synflow.SynthesisFlow(
        syn_np=syn_np,
        timing_np=timing_np))

    # 3. Set Target PDK
    # Specifies the process development kit to be used.
    project.set_pdk("skywater130")

    # 4. Define Timing Corners for Static Timing Analysis (STA)
    # Sets up different scenarios to analyze timing performance under various
    # process, voltage, and temperature (PVT) conditions.

    # Slow corner: Checks for setup time violations at worst-case conditions.
    scenario = project.constraint.timing.make_scenario("slow")
    scenario.add_libcorner(["slow", "generic"])
    scenario.set_pexcorner("typical")
    scenario.add_check("setup")

    # Typical corner: Used for power analysis under nominal conditions.
    scenario = project.constraint.timing.make_scenario("typical")
    scenario.add_libcorner(["typical", "generic"])
    scenario.set_pexcorner("typical")
    scenario.add_check("power")

    # Fast corner: Checks for hold time violations at best-case conditions.
    scenario = project.constraint.timing.make_scenario("fast")
    scenario.add_libcorner(["fast", "generic"])
    scenario.set_pexcorner("typical")
    scenario.add_check("hold")

    # Set the delay model used for timing calculations. NLDM is a common standard.
    project.set_asic_delaymodel("nldm")

    # 5. Define Physical Design Constraints
    # These constraints guide the place-and-route tools.
    area = project.constraint.area
    # Target a core utilization of 40%.
    area.set_density(40)
    # Set a margin of 1 micron around the core area.
    area.set_coremargin(1)

    # 6. Alias and Register IP/Macro Libraries
    # Makes specialized libraries like SRAM and IO cells available to the flow
    # under a common, standardized naming convention.
    Sky130Lambdalib_SinglePort.alias(project)
    Sky130Lambdalib_SinglePortRegfile.alias(project)
    Sky130LambdaLib_IO.alias(project)

1.6.2. Flowgraph#

1.6.3. PDK#

skywater130

1.6.4. StdCellLibrary#

sky130hd

1.6.5. Configuration#

Keypath	Type	Value
`[asic,delaymodel]`	`str`	`nldm`
`[asic,mainlib]`	`str`	`sky130hd`
`[asic,pdk]`	`str`	`skywater130`
`[constraint,area,aspectratio]`	`float`	`1.0`
`[constraint,area,coremargin]`	`float`	`1.0`
`[constraint,area,density]`	`float`	`40.0`
`[constraint,timing,scenario,fast,check]`	`{enum}`	`hold`
`[constraint,timing,scenario,fast,libcorner]`	`{str}`	`fast` `generic`
`[constraint,timing,scenario,fast,pexcorner]`	`str`	`typical`
`[constraint,timing,scenario,slow,check]`	`{enum}`	`setup`
`[constraint,timing,scenario,slow,libcorner]`	`{str}`	`generic` `slow`
`[constraint,timing,scenario,slow,pexcorner]`	`str`	`typical`
`[constraint,timing,scenario,typical,check]`	`{enum}`	`power`
`[constraint,timing,scenario,typical,libcorner]`	`{str}`	`generic` `typical`
`[constraint,timing,scenario,typical,pexcorner]`	`str`	`typical`
`[option,autoissue]`	`bool`	`False`
`[option,breakpoint]`	`bool`	`False`
`[option,builddir]`	`dir`	`build`
`[option,clean]`	`bool`	`False`
`[option,continue]`	`bool`	`False`
`[option,flow]`	`str`	`asicflow`
`[option,hash]`	`bool`	`False`
`[option,jobincr]`	`bool`	`False`
`[option,jobname]`	`str`	`job0`
`[option,nodashboard]`	`bool`	`False`
`[option,nodisplay]`	`bool`	`False`
`[option,novercheck]`	`bool`	`False`
`[option,optmode]`	`int`	`0`
`[option,quiet]`	`bool`	`False`
`[option,remote]`	`bool`	`False`
`[option,track]`	`bool`	`False`
`[schemaversion]`	`str`	`0.54.0`